LINER LTC3413EFE 3a, 2mhz monolithic synchronous regulator for ddr/qdr memory termination Datasheet

LTC3413
3A, 2MHz Monolithic
Synchronous Regulator for
DDR/QDR Memory Termination
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FEATURES
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DESCRIPTIO
The LTC®3413 is a high efficiency monolithic synchronous step-down DC/DC converter utilizing a constant
frequency, current mode architecture. It operates from an
input voltage range of 2.25V to 5.5V and provides a
regulated output voltage equal to (0.5)VREF while sourcing
or sinking up to 3A of output current. An internal voltage
divider reduces component count and eliminates the need
for external resistors by dividing the reference voltage in
half. The internal synchronous power switch with 85mΩ
on-resistance increases efficiency and eliminates the need
for an external Schottky diode. Switching frequencies up
to 2MHz are set by an external resistor.
High Efficiency: Up to 90%
±3A Output Current
Symmetrical Source and Sink Output Current Limit
Low RDS(ON) Internal Switch: 85mΩ
No Schottky Diode Required
2.25V to 5.5V Input Voltage Range
VOUT = VREF /2
±1% Output Voltage Accuracy
Programmable Switching Frequency: Up to 2MHz
Power Good Output Voltage Monitor
Overtemperature Protected
Available in 16-Lead TSSOP Exposed Pad Package
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APPLICATIO S
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Forced-continuous operation in the LTC3413 reduces
noise and RF interference. Fault protection is provided by
an overcurrent comparator that limits output current during both sourcing and sinking operations. Adjustable
compensation allows the transient response to be optimized over a wide range of loads and output capacitors.
Bus Termination: DDR and QDRTM Memory,
SSTL, HSTL, ...
Notebook Computers
Distributed Power Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, Hitachi, IDT, Micron Technology, Inc. and Samsung.
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TYPICAL APPLICATIO
100
VIN
2.5V
90
22µF
VIN = 2.5V
f = 1MHz
PVIN
PGOOD
VREF
4.7M
SW
COUT
100µF
×2
LTC3413
RUN/SS
330pF
L1
0.47µH
PGND
SGND
5.11k
70
60
50
40
30
ITH
2200pF
VOUT
1.25V
±3A
EFFICIENCY (%)
80
SVIN
20
RT
VFB
309k
10
3413 F01a
L1: VISHAY DALE IHLP-2525CZ-01 0.47
COUT: TDK C4532X5R0J107M
0
0.01
0.1
1
LOAD CURRENT (A)
10
3413 F01b
Figure 1a. High Efficiency Bus Termination Supply
Figure 1b. Efficiency vs Load Current
sn3413 3413fs
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LTC3413
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
SVIN, PVIN Supply Voltages ........................ – 0.3V to 6V
ITH, RUN/SS, VFB, PGOOD Voltages ........... – 0.3V to VIN
VREF Voltage .............................................. – 0.3V to VIN
SW Voltage .................................. – 0.3V to (VIN + 0.3V)
Peak SW Sink and Source Current ........................ 7.2A
Operating Ambient Temperature Range
(Note 2) .............................................. – 40°C to 85°C
Junction Temperature (Notes 5, 8) ...................... 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ORDER PART
NUMBER
TOP VIEW
SVIN
1
16 PVIN
PGOOD
2
15 SW
ITH
3
14 SW
VFB
4
17
LTC3413EFE
13 PGND
RT
5
12 PGND
VREF
6
11 SW
RUN/SS
7
10 SW
SGND
8
9
FE PART
MARKING
PVIN
FE PACKAGE
16-LEAD PLASTIC TSSOP
EXPOSED PAD (PIN 17)
MUST BE SOLDERED TO SGND
3413EFE
TJMAX = 125°C, θJA = 38°C/ W, θJC = 10°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V, unless otherwise noted.
SYMBOL
PARAMETER
VIN
Input Voltage Range
CONDITIONS
MIN
TYP
VFB
Feedback Voltage Accuracy
IFB
Voltage Feedback Leakage Current
IRUN
RUN/SS Leakage Current
1
µA
∆VFB
Feedback Voltage Line Regulation
VIN = 2.7V to 5.5V (Note 3)
●
0.04
0.2
%/V
VLOADREG
Feedback Voltage Load Regulation
Measured in Servo Loop, VITH = 0.36V
Measured in Servo Loop, VITH = 0.84V
●
●
0.02
– 0.02
0.2
– 0.2
%
%
∆VPGOOD
Power Good Range
±10
±12
%
RPGOOD
Power Good Pull-Down Resistance
120
200
Ω
IQ
Input DC Bias Current
Active Current
Shutdown
(Note 4)
VFB = 1.5V, VITH = 1.4V, VREF = 2.5V
VRUN = 0V (Note 7)
250
0.02
330
1
µA
µA
fOSC
Switching Frequency
Switching Frequency Range
ROSC = 309k
(Note 6)
1.00
1.12
2.00
MHz
MHz
RPFET
RDS(ON) of P-Channel FET
ISW = 300mA
85
110
mΩ
RNFET
RDS(ON) of N-Channel FET
ISW = 300mA
65
90
mΩ
ILIMIT
Peak Current Limit
3.8
5.4
VUVLO
Undervoltage Lockout Threshold
1.75
2
ILSW
SW Leakage Current
VRUN
RUN Threshold
0.5
2.25
(Note 3)
●
0.88
0.30
VRUN = 0V, VIN = 5.5V (Note 7)
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3413E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: The LTC3413E is tested in a feedback loop that adjusts VFB to
achieve a specified error amplifier output voltage (ITH).
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
MAX
UNITS
5.5
V
±1
%
0.4
µA
A
2.25
V
0.1
1
µA
0.65
0.8
V
Note 5: TJ is calculated from the ambient temperature TA and power
dissipation PD as follows: LTC3413E: TJ = TA + (PD • 38°C/W)
Note 6: 2MHz operation is guaranteed by design and not production tested.
Note 7: Shutdown current and SW leakage current are only tested during
wafer sort.
Note 8: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
sn3413 3413fs
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LTC3413
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TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Load Current
Efficiency vs Input Voltage
100
VIN = 2.5V
70
VIN = 3.3V
60
50
40
30
–0.05
70
LOAD = 100mA
60
50
0
0.01
0.1
1
LOAD CURRENT (A)
20
2.5
10
3.5
4.5
4.0
INPUT VOLTAGE (V)
5.0
VIN = 3.3V
TA = 25°C
NFET
ON-RESISTANCE
40
20
PFET ON-RESISTANCE
LEAKAGE CURRENT (nA)
ON-RESISTANCE (mΩ)
ON-RESISTANCE (mΩ)
80
80
60
NFET ON-RESISTANCE
40
0
20 40 60 80
TEMPERATURE (°C)
2.5
3
PFET
1.0
NFET
VIN = 3.3V
TA = 25°C
TA = 25°C
1008
1040
VIN = 3.3V
1006
FREQUENCY (kHz)
FREQUENCY (kHz)
1500
5.5
Frequency vs Temperature
1010
3500
2000
5
3.5
4
4.5
INPUT VOLTAGE (V)
3
3413 G06
Frequency vs Input Voltage
1050
2500
2.5
3413 G05
Frequency vs ROSC
FREQUENCY (kHz)
1.5
5
3.5
4
4.5
INPUT VOLTAGE (V)
3413 G04
3000
TA = 25°C
2.0
0
0
100 120
3.0
0.5
20
0
–40 –20
2.5
1.0
1.5
2.0
LOAD CURRENT (A)
0.5
Switch Leakage vs Input Voltage
2.5
100
PFET
ON-RESISTANCE
0
3413 G03
Switch On-Resistance
vs Input Voltage
120
60
5.5
3413 G02
Switch On-Resistance
vs Temperature
4000
–0.20
–0.30
3.0
3413 G01
4500
–0.15
–0.25
30
10
100
–0.10
40
20
120
TA = 25°C
LOAD = 1A
LOAD = 3A
80
EFFICIENCY (%)
EFFICIENCY (%)
VOUT = 1.25V
90 TA = 25°C
∆VOUT/VOUT (%)
VOUT = 1.25V
90 TA = 25°C
80
Load Regulation
0
100
1030
1020
1010
1000
1004
1002
1000
998
996
994
1000
500
992
0
990
54 154 254 354 454 554 654 754 854 954
ROSC (kΩ)
3413 G07
2.5
3
3.5
4
4.5
INPUT VOLTAGE (V)
5
5.5
3213 G08
990
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
100 120
3413 G09
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LTC3413
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TYPICAL PERFOR A CE CHARACTERISTICS
Quiescent Current vs Input Voltage
350
OUTPUT
VOLTAGE
100mV/DIV
TA = 25°C
300
QUIESCENT CURRENT (µA)
Load Step Transient
250
INDUCTOR
CURRENT
1A/DIV
200
150
100
VIN = 2.5V
20µs/DIV
VOUT = 1.25V
LOAD STEP = 0A TO 3A
50
0
2.0
2.5
4.5
3.0 3.5 4.0
INPUT VOLTAGE (V)
5.0
3413 G11
5.5
3413 G10
Load Step Transient
Start-Up
OUTPUT
VOLTAGE
100mV/DIV
OUTPUT
VOLTAGE
500mV/DIV
INDUCTOR
CURRENT
1A/DIV
INDUCTOR
CURRENT
1A/DIV
20µs/DIV
VIN = 2.5V
VOUT = 1.25V
LOAD STEP = 0A TO –3A
3413 G12
VIN = 2.5V
VOUT = 1.25V
LOAD = 0.4Ω
1ms/DIV
3413 G13
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LTC3413
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SVIN (Pin 1): Signal Input Supply. Decouple this pin to
SGND with a capacitor. SVIN must be greater or equal to
PVIN, however, the difference between SVIN and PVIN must
be less than 0.5V.
PGOOD (Pin 2): Power Good Output. Open-drain logic
output that is pulled to ground when the output voltage is
not within ±10% of regulation point.
ITH (Pin 3): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is from 0.2V to
1.4V with 0.6V corresponding to the zero-sense voltage
(zero current).
VFB (Pin 4): Feedback Pin. Receives the feedback voltage
from the output.
RT (Pin 5): Oscillator Resistor Input. Connecting a resistor
to ground from this pin sets the switching frequency.
RUN/SS (Pin 7): Run Control and Soft-Start Input. Forcing
this pin below 0.5V shuts down the LTC3413. In shutdown
all functions are disabled drawing < 1µA of supply current.
A capacitor to ground from this pin sets the ramp time to
full output current.
SGND (Pin 8): Signal Ground. All small-signal components and compensation components should connect to
this ground, which in turn connects to PGND at one point.
PVIN (Pins 9, 16): Power Input Supply. Decouple this pin
to PGND with a capacitor.
SW (Pins 10, 11, 14, 15): Switch Node Connection to
Inductor. This pin connects to the drains of the internal
main and synchronous power MOSFET switches.
PGND (Pins 12, 13): Power Ground. Connect this pin
closely to the (–) terminal of CIN and COUT.
EXPOSED PAD (Pin 17): Should be connected to SGND.
VREF (Pin 6): Reference Voltage Input. The positive input
of the internal error amplifier senses one-half of the
voltage at this pin through a resistor divider.
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FU CTIO AL DIAGRA
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SVIN
VREF
ITH
1
6
3
PVIN PVIN
9
SVIN
SGND
SLOPE
COMPENSATION
RECOVERY
+
8
VFB
16
PMOS CURRENT
COMPARATOR
+
–
4
ERROR
AMPLIFIER
0.9VREF
2
–
+
–
SLOPE
COMPENSATION
OSCILLATOR
10 SW
11 SW
LOGIC
+
PGOOD
1.1VREF
2
–
–
14 SW
15 SW
+
2
RUN
NMOS CURRENT
COMPARATOR
12 PGND
13 PGND
3413 BD
5
7
RT
RUN/SS
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LTC3413
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OPERATIO
Main Control Loop
The LTC3413 is a monolithic, constant frequency, current
mode step-down DC/DC converter that is capable of sourcing and sinking current at the output. During normal operation, the internal top power switch (P-channel MOSFET)
is turned on at the beginning of each clock cycle. Current
in the inductor increases until the current comparator trips
and turns off the top power MOSFET. The peak inductor
current at which the current comparator shuts off the top
power switch is controlled by the voltage on the ITH pin.
The error amplifier adjusts the voltage on the ITH pin by
comparing the feedback signal on the VFB pin with a reference voltage that is equal to one-half of the voltage on the
VREF pin. When the load current increases, it causes a
reduction in the feedback voltage relative to the reference.
The error amplifier raises the ITH voltage until the average
inductor current matches the new load current. When the
top power MOSFET shuts off, the synchronous power
switch (N-channel MOSFET) turns on until either the bottom current limit is reached or the beginning of the next
clock cycle. The bottom current limit is set at – 7A.
The operating frequency is set by an external resistor
connected between the RT pin and ground. The switching
frequency can range from 300kHz to 2MHz.
Overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage comes out of
regulation by ±10%. In an overvoltage condition, the top
power MOSFET is turned off and the bottom power MOSFET
is switched on until either the overvoltage condition clears
or the bottom MOSFET’s current limit is reached.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one
cycle until it reaches 100% duty cycle. The output voltage
will then be determined by the input voltage minus the
voltage drop across the internal P-channel MOSFET and
the inductor.
Low Supply Operation
The LTC3413 is designed to operate down to an SVIN input
supply voltage of 2.25V. One important consideration at
low input supply voltages is that the RDS(ON) of the Pchannel and N-channel power switches increases. The
user should calculate the power dissipation when the
LTC3413 is used at 100% duty cycle with low input
voltages to ensure that thermal limits are not exceeded.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at duty cycles greater than 50%. It is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40%. Normally,
the maximum inductor peak current is reduced when slope
compensation is added. In the LTC3413, however, slope
compensation recovery is implemented to keep the maximum inductor peak current constant throughout the range
of duty cycles.
Short-Circuit Protection
When the output is shorted to ground, the inductor current
decays very slowly during a single switching cycle. To
prevent current runaway from occurring, a secondary
current limit is imposed on the inductor current. If the
inductor valley current increases greater than 5A, the top
power MOSFET will be held off and switching cycles will be
skipped until the inductor current is reduced.
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LTC3413
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APPLICATIO S I FOR ATIO
The basic LTC3413 application circuit is shown in Figure
1a. External component selection is determined by the
maximum load current and begins with the selection of the
inductor value and operating frequency followed by CIN
and COUT.
Having a lower ripple current reduces the core losses in
the inductor, the ESR losses in the output capacitors and
the output voltage ripple. Highest efficiency operation is
achieved at low frequency with small ripple current. This,
however, requires a large inductor.
Operating Frequency
A reasonable starting point for selecting the ripple current
is ∆IL = 0.4(IMAX). The largest ripple current occurs at the
highest VIN. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation:
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
The operating frequency of the LTC3413 is determined by
an external resistor that is connected between pin RT and
ground. The value of the resistor sets the ramp current that
is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the
following equation.
ROSC =
3.23 • 1011
(Ω) – 10kΩ
f
Although frequencies as high as 2MHz are possible, the
minimum on-time of the LTC3413 imposes a minimum
limit on the operating duty cycle. The minimum on-time is
typically 110ns. Therefore, the minimum duty cycle is
equal to 100 • 110ns • f (Hz).
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ∆IL increases with higher VIN or VOUT and
decreases with higher inductance.
 V  V 
∆IL =  OUT   1– OUT 
VIN 
 fL  
 V


V
L =  OUT   1 – OUT 
 f∆IL(MAX)   VIN(MAX) 
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. Actual core loss is independent of core size for
a fixed inductor value, but it is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will
increase.
Ferrite designs have very low core losses and are used
often at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy
materials are small and don’t radiate much energy, but
generally cost more than powdered iron core inductors
with similar characteristics. The choice of which style
inductor to use mainly depends on the price versus size
requirements and any radiated field/EMI requirements.
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LTC3413
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APPLICATIO S I FOR ATIO
Table 1 shows some recommended surface mount
inductors for LTC3413 applications.
Table 1. Recommended Surface Mount Inductors
Manufacturer
Part Number
Value
(µH)
DCR
(mΩ)
Murata
LQH55DNR47M01
0.47
13.0
Vishay/Dale
IHLP2525CZPJR47M01
0.47
4.2
Pulse
P1166.681T
0.44
6.0
Cooper
SD20-R47
0.47
20.0
CIN and COUT Selection
The input capacitance, CIN, is needed to filter the trapezoidal wave current at the source of the top MOSFET. To
prevent large voltage transients from occurring, a low ESR
input capacitor sized for the maximum RMS current
should be used. The maximum RMS current is given by:
IRMS = IOUT (MAX)
VOUT
VIN
VIN
–1
VOUT
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life which makes it advisable to further derate the
capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design.
The selection of COUT is determined by the effective series
resistance (ESR) that is required to minimize voltage
ripple and load step transients as well as the amount of
bulk capacitance that is necessary to ensure that the
control loop is stable. Loop stability can be checked by
viewing the load transient response as described in a later
section. The output ripple, ∆VOUT, is determined by:
The output ripple is highest at maximum input voltage
since ∆IL increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and RMS
current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all
available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only use
types that have been surge tested for use in switching
power supplies.
Aluminum electrolytic capacitors have significantly higher
ESR, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings
and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage
coefficient and audible piezoelectric effects. The high Q of
ceramic capacitors with trace inductance can also lead to
significant ringing.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input and
the power is supplied by a wall adapter through long wires,
a load step at the output can induce ringing at the input,
VIN. At best, this ringing can couple to the output and be
mistaken as loop instability. At worst, a sudden inrush of
current through the long wires can potentially cause a
voltage spike at VIN large enough to damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These

1 
∆VOUT ≤ ∆IL  ESR +

8fC OUT 

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LTC3413
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APPLICATIO S I FOR ATIO
dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.
Output Voltage Programming
In most applications, VOUT is connected directly to VFB.
The output voltage will be equal to one-half of the voltage
on the VREF pin for this case.
VOUT =
VREF
2
If a different output voltage relationship is desired, an
external resistor divider from VOUT to VFB can be used. The
output voltage will then be set according to the following
equation:
VOUT
R2
VFB
R1
LTC3413
SGND
3413 F02
Figure 2. Setting the Output Voltage
VOUT
V  R2
= REF  1 + 
2  R1
Soft-Start
The RUN/SS pin provides a means to shut down the
LTC3413 as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5V places the LTC3413 in a low
quiescent current shutdown state (IQ < 1µA).
The LTC3413 contains an internal soft-start clamp that
gradually raises the clamp on ITH after the RUN/SS pin is
pulled above 2V. The full current range becomes available
on ITH after 1024 switching cycles. If a longer soft-start
period is desired, the clamp on ITH can be set externally
with a resistor and capacitor on the RUN/SS pin as shown
in Figure 1a. The soft-start duration can be calculated by
using the following formula:

VIN 
tSS = RSS • C SS ln 
 (Seconds)
 VIN – 1.8V 
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% - (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: VIN quiescent current and I2R losses.
The VIN quiescent current loss dominates the efficiency
loss at very low load currents whereas the I2R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence.
1. The VIN quiescent current is due to two components:
the DC bias current as given in the Electrical Characteristics and the internal main switch and synchronous switch
gate charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
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LTC3413
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APPLICATIO S I FOR ATIO
high to low to high again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is the current out
of VIN that is typically larger than the DC bias current. In
continuous mode, IGATECHG = f(QT + QB) where QT and QB
are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to VIN and thus their effects will be more
pronounced at higher supply voltages.
2. I2R losses are calculated from the resistances of the
internal switches, RSW, and external inductor RL. In continuous mode the average output current flowing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET RDS(ON) and the duty cycle (DC) as follows:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses, simply add RSW to RL
and multiply the result by the square of the average output
current.
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3413 does not dissipate
much heat due to its high efficiency.
But, in applications where the LTC3413 is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will be turned off and the SW node
will become high impedance.
To avoid the LTC3413 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The temperature rise is given by:
TR = (PD)(θJA)
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, TJ, is given by:
TJ = TA + TR
where TA is the ambient temperature.
As an example, consider the LTC3413 in dropout at an
input voltage of 3.3V, a load current of 3A and an ambient
temperature of 70°C. From the Typical Performance graph
of switch resistance, the RDS(ON) of the P-channel switch
at 70°C is approximately 97mΩ. Therefore, power dissipated by the part is:
PD = (ILOAD2)(RDS(ON)) = (3A)2(97mΩ) = 0.87W
For the TSSOP package, the θJA is 38°C/W. Thus the
junction temperature of the regulator is:
TJ = 70°C + (0.87W)(38°C/W) = 103°C
which is below the maximum junction temperature of
sn3413 3413fs
10
LTC3413
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APPLICATIO S I FOR ATIO
125°C.
Design Example
Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)).
As a design example, consider using the LTC3413 in an
application with the following specifications: VIN = 2.5V,
VOUT = 1.25V, IOUT(MAX) = ±3A, f = 1MHz.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ∆ILOAD(ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating a feedback error signal used by
the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability problem. The ITH pin external components and output capacitor shown in Figure 1a will provide adequate compensation for most applications.
Output Voltage Tracking of VREF
For applications in which the VREF pin is connected to the
VIN pin, the output voltage will be equal to one-half of the
voltage on the VIN pin. Because the output voltage will
track the input voltage, any disturbance on VIN will appear
on VOUT. For example, a load step transient could cause
the input voltage to drop if there is insufficient bulk
capacitance at the VIN pin. The corresponding drop in the
output voltage during the load step transient is caused by
the VOUT tracking of VIN and should not be confused with
poor load regulation.
First, calculate the timing resistor:
ROSC =
3.23 • 1011
1• 106
– 10kΩ = 313kΩ
Use a standard value of 309k. Next, calculate the inductor
value for about 40% ripple current:
 1.25V   1.25V 
L=
 1–
 = 0.47µH
2.5V 
 1MHz • 1.2A  
Using a 0.47µH inductor results in a maximum ripple
current of:

  1.25V 
1.25V
∆IL = 
 1–
 = 1.33A
2.5V 
 1MHz • 0.47µH  
COUT will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, two
100µF ceramic capacitors will be used. CIN should be sized
for a maximum current rating of:
 1.25V  2.5V
IRMS = 3A
– 1 = 1.5ARMS

 2.5V  1.25V
Decoupling the PVIN pins with two 100µF capacitors is
sn3413 3413fs
11
LTC3413
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APPLICATIO S I FOR ATIO
VIN
2.5V
1
RPG
100k
PGOOD
RITH
5.11k
CITH
CC
2200pF 100pF
X7R
2
3
4
RSS
4.7M
CSS
330pF X7R
PVIN
PGOOD
SW
ITH
SWVFB
VFB
PGND
CIN1**
100µF
16
15
14
13
L1*
0.47µH
VOUT
1.25V
±3A
LTC3413
5
ROSC
309k
SVIN
6
7
8
RT
PGND
VREF
SW
RUN/SS
SW
SGND
PVIN
12
11
COUT**
100µF
×2
10
9
GND
CIN2**
100µF
3413 F03
*VISHAY DALE IHLP-2525CZ-01 0.47µH
**TDK C4532X5R0J107M
Figure 3. One-Half VREF, ±3A DDR Memory Termination Supply at 1MHz
(Efficiency Curve is Shown in Figure 1b)
adequate for most applications. Connect the VREF pin
directly to SVIN. Connecting the VFB pin directly to VOUT
will set the output voltage equal to one-half of the voltage
on the VREF pin. The complete circuit for this design
example is illustrated in Figure 3.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3413. Check the following in your layout.
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning to
the SGND pin at one point which is then connected to the
PGND pin close to the LTC3413.
2. Connect the (+) terminal of the input capacitor(s), CIN,
as close as possible to the PVIN pin. This capacitor
provides the AC current into the internal power MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
4. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power
components. You can connect the copper areas to any DC
net (PVIN, SVIN, VOUT, PGND, SGND or any other DC rail in
your system).
5. Connect the VFB pin directly to the VOUT pin.
sn3413 3413fs
12
LTC3413
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APPLICATIO S I FOR ATIO
(4a) Top Layer
(4b) Bottom Layer
(4c) PCB Photo
Figure 4. LTC3413 Layout Diagram
sn3413 3413fs
13
LTC3413
U
TYPICAL APPLICATIO
1.25V, ±3A DDR Memory Termination Supply at 1MHz
VIN
3.3V
1
RPG
100k
2
PGOOD
RITH
5.11k
3
CITH
CC
2200pF 100pF
X7R
4
SVIN
PVIN
PGOOD
SW
ITH
SWVFB
VFB
PGND
CIN1**
100µF
16
15
14
13
L1*
0.47µH
LTC3413
5
ROSC
309k
6
2.5V
RSS
4.7M
7
CSS
330pF X7R
8
RT
PGND
VREF
SW
RUN/SS
SW
SGND
PVIN
12
11
VOUT
1.25V
±3A
COUT**
100µF
×2
10
9
GND
CIN2**
100µF
3413 TA01
*VISHAY DALE IHLP-2525CZ-01 0.47µH
**TDK C4532X5R0J107M
Efficiency vs Load Current,
VIN = 3.3V, VOUT = 1.25V, f = 1MHz
100
90
EFFICIENCY (%)
80
70
60
50
40
30
20
10
0
0.01
0.1
1
LOAD CURRENT (A)
10
3413 TA01b
sn3413 3413fs
14
LTC3413
U
PACKAGE DESCRIPTIO
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663,
Exposed Pad Variation BA)
4.90 – 5.10*
(.193 – .201)
2.74
(.108)
2.74
(.108)
16 1514 13 12 1110
6.60 ±0.10
9
2.74
(.108)
4.50 ±0.10
SEE NOTE 4
2.74 6.40
(.108) BSC
0.45 ±0.05
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8
RECOMMENDED SOLDER PAD LAYOUT
1.10
(.0433)
MAX
4.30 – 4.50*
(.169 – .177)
0° – 8°
0.09 – 0.20
(.0036 – .0079)
0.45 – 0.75
(.018 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
0.05 – 0.15
(.002 – .006)
FE16 (BA) TSSOP 0203
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
sn3413 3413fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC3413
U
TYPICAL APPLICATIO
3.3V to 0.75V, ±3A HSTL Application
VIN
3.3V
1
RPG
100k
PGOOD
RITH
10k
CITH
CC
2200pF 100pF
X7R
2
3
4
1.5V
RSS
4.7M
CSS
330pF X7R
PVIN
PGOOD
SW
ITH
SWVFB
VFB
PGND
15
14
13
L1*
0.47µH
VOUT
0.75V
±3A
LTC3413
5
ROSC
309k
SVIN
CIN1**
100µF
16
6
7
8
RT
PGND
VREF
SW
RUN/SS
SW
SGND
PVIN
12
11
COUT1†
22µF
+
COUT2††
470µF
10
9
GND
CIN2**
100µF
3413 TA02
*VISHAY DALE IHLP-2525CZ-01 0.47µH
**TDK C4532X5R0J107M
†TAIYO YUDEN JMK325BJ226MM
††
SANYO POSCAP 4TPD470M
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PART NUMBER
DESCRIPTION
COMMENTS
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LTC3412
2.5A, (IOUT) 4MHz, Monolithic Synchronous Step-Down Regulator
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4A, (IOUT) 4MHz, Monolithic Synchronous Step-Down Regulator
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TM
LTC3713
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VIN: 1.5V to 10V, VOUT(MIN): 0.8V, SSOP-24
LTC3717
No RSENSE Controller for DDR Memory Termination
VIN: 5V to 36V, VOUT(MIN): 0.8V, SSOP-24
LTC3718
Low Input Voltage, No RSENSE Controller for DDR Memory Termination
VIN: 1.5V to 10V,VOUT(MIN): 0.8V, SSOP-24
No RSENSE is a trademark of Linear Technology Corporation.
sn3413 3413fs
16
Linear Technology Corporation
LT/TP 0703 1K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2002
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