Hynix HY5V22GF-P 4 banks x 1m x 32bit synchronous dram Datasheet

HY5V22GF
4 Banks x 1M x 32Bit Synchronous DRAM
DESCRIPTION
The Hynix HY5V22G is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the memory applications
which require wide data I/O and high bandwidth. HY5V22G is organized as 4banks of 1,048,576x32.
HY5V22G is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
•
JEDEC standard 3.3V power supply
•
Auto refresh and self refresh
•
All device pins are compatible with LVTTL interface
•
4096 refresh cycles / 64ms
•
90Ball FBGA with 0.8mm of pin pitch
•
Programmable Burst Length and Burst Type
•
All inputs and outputs referenced to positive edge of
system clock
•
Data mask function by DQM0,1,2 and 3
•
Internal four banks operation
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
Programmable CAS Latency ; 2, 3 Clocks
•
Burst Read Single Write operation
ORDERING INFORMATION
Part No.
Clock Frequency
HY5V22GF-H
133MHz
HY5V22GF-P
100MHz
Power
Organization
Interface
Package
Normal
4Banks x 1Mbits
x32
LVTTL
90Ball FBGA
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.3/Nov. 01
HY5V22GF
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
D Q 26
D Q 24
VSS
VDD
DQ 23
DQ 21
D Q 28
VD DQ
VSS Q
VDD Q
VSS Q
DQ 19
V SSQ
D Q 27
DQ 25
DQ 22
DQ 20
VD DQ
V SSQ
D Q 29
DQ 30
DQ 17
DQ 18
VD DQ
VDD Q
D Q 31
NC
NC
DQ 16
VSS Q
VSS
DQM3
A3
A2
DQM2
VD D
A4
A5
A6
A10
A0
A1
NC
BA1
A11
A
B
C
D
E
F
G
Top View
H
(11m m x13m m )
A7
A8
NC
C LK
CK E
A9
BA0
CS#
RAS #
DQM1
NC
NC
C AS#
W E#
DQM0
VD DQ
DQ8
VSS
VD D
DQ7
VSSQ
VSS Q
DQ 10
DQ 9
DQ 6
DQ5
VD D Q
VSS Q
DQ 12
D Q 14
DQ 1
DQ3
VD D Q
DQ 11
VD DQ
V SSQ
VD DQ
VSSQ
DQ4
DQ 13
DQ 15
VSS
VDD
DQ 0
J
K
L
M
N
P
R
DQ2
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK.
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS
Chip Select
Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1
Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11
Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
DQM0~3
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ31
Data Input/Output
Multiplexed data input / output pin
VDD/VSS
Power Supply/Ground
Power supply for internal circuits and input buffers
VDDQ/VSSQ
Data Output Power/Ground
Power supply for output buffers
NC
No Connection
No connection
Rev. 0.3/Nov. 01
3
HY5V22GF
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 32 I/O Synchronous DRAM
Self Refresh Logic
& Timer
Refresh
Counter
1M x32 Bank 3
CLK
Row Active
Y decoder
A0
A1
DQ1
DQ30
DQ31
Column Add
Counter
Address
Register
Address buffers
Rev. 0.3/Nov. 01
DQ0
I/O Buffer & Logic
Column
Pre
Decoder
Bank Select
A10
BA0
BA1
Memory
Cell
Array
Sense AMP & I/O Gate
Column
Active
1M x32 Bank 0
X decoder
WE
DQM0
DQM1
DQM2
DQM3
1M x32 Bank 1
X decoder
CAS
1M x32 Bank 2
X decoder
RAS
State Machine
CS
Row
Pre
Decoder
X decoder
CKE
Burst
Counter
Mode Register
CAS Latency
Data Out Control
Pipe Line Control
4
HY5V22GF
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
°C
Storage Temperature
TSTG
-55 ~ 125
°C
Voltage on Any Pin relative to VSS
VIN, VOUT
-1.0 ~ 4.6
V
Voltage on VDD relative to VSS
VDD, VDDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD
1
W
Soldering Temperature ⋅ Time
TSOLDER
260 ⋅ 10
°C ⋅ Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70°C)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
VDD, VDDQ
3.0
3.3
3.6
V
1,2
Input high voltage
VIH
2.0
3.0
VDDQ + 0.3
V
1,3
Input low voltage
VIL
VSSQ - 0.3
0
0.8
V
1,4
Note
Note :
1.All voltages are referenced to VSS = 0V
2.VDD/VDDQ(min) is 3.15V for HY5V22GF-H/P
3.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration with no input clamp diodes
4.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration with no input clamp diodes
AC OPERATING CONDITION (TA=0 to 70°C, 3.0V ≤VDD ≤3.6V, VSS=0V - Note1)
Parameter
Symbol
Value
Unit
VIH / VIL
2.4/0.4
V
Vtrip
1.4
V
Input rise / fall time
tR / tF
1
ns
Output timing measurement reference level
Voutref
1.4
V
CL
30
pF
AC input high / low level voltage
Input timing measurement reference level voltage
Output load capacitance for access time measurement
2
Note :
1.3.15V ≤VDD ≤3.6V is applied for HY5V22GF-H/P
2.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF)
For details, refer to AC/DC output load circuit
Rev. 0.3/Nov. 01
5
HY5V22GF
CAPACITANCE (TA=25°C, f=1MHz, VDD=3.3V)
Parameter
Pin
Input capacitance
Data input / output capacitance
Symbol
Min
Max
Unit
CLK
CI1
2.5
3.5
pF
A0 ~ A10, BA0, BA1, CKE, CS, RAS,
CAS, WE, DQM0~3
CI2
2.5
3.8
pF
DQ0 ~ DQ31
CI/O
4
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
Vtt=1.4V
RT=500 Ω
Output
RT=50 Ω
Z0 = 50Ω
Output
30pF
30pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (DC operating conditions unless otherwise noted)
Parameter
Symbol
Min.
Max
Unit
Note
Input leakage current
ILI
-1
1
uA
1
Output leakage current
ILO
-1
1
uA
2
Output high voltage
VOH
2.4
-
V
IOH = -2mA
Output low voltage
VOL
-
0.4
V
IOL = +2mA
Note :
1.VIN = 0 to 3.6V, All other pins are not under test = 0V
2.DOUT is disabled, VOUT=0 to 3.6V
Rev. 0.3/Nov. 01
6
HY5V22GF
DC CHARACTERISTICS II (DC operating conditions unless otherwise noted)
Speed
Parameter
Symbol
Test Condition
-H
-P
150
140
IDD1
Burst Length=1, One bank active
tRAS ≥ tRAS(min), tRP ≥ tRP(min),
IOL=0mA
IDD2P
CKE ≤ VIL(max), tCK = 15ns
4
IDD2PS
CKE ≤ VIL(max), tCK = ∞
4
IDD2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
30
IDD2NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
20
IDD3P
CKE ≤ VIL(max), tCK = 15ns
6
IDD3PS
CKE ≤ VIL(max), tCK = ∞
6
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
80
IDD3NS
CKE ≥ VIH(min), tCK = ∞
Input signals are stable
50
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min),
tRAS ≥ tRAS(min), IOL=0mA
All banks active
Auto Refresh Current
IDD5
tRRC ≥ tRRC(min), 2 banks active
Self Refresh Current
IDD6
CKE ≤ 0.2V
Operating Current
Precharge Standby Current
in power down mode
Precharge Standby Current
in non power down mode
Active Standby Current
in power down mode
Active Standby Current
in non power down mode
Unit
Note
mA
1
mA
mA
mA
mA
CL=3
250
230
mA
1
350
330
mA
2
CL=2
4
mA
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS I
Rev. 0.3/Nov. 01
7
HY5V22GF
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-H
Parameter
Unit
Min
System clock
cycle time
CAS Latency = 3
-P
Symbol
tCK3
Max
7.5
Min
10
1000
CAS Latency = 2
Note
Max
ns
1000
tCK2
10
10
ns
Clock high pulse width
tCHW
2.5
-
3
-
ns
1
Clock low pulse width
tCLW
2.5
-
3
-
ns
1
6
ns
CAS Latency = 3
tAC3
5.4
CAS Latency = 2
tAC2
6
-
6
ns
Access time from clock
2
Data-out hold time
tOH
2.7
-
3
-
ns
3
Data-Input setup time
tDS
1.5
-
2
-
ns
1
Data-Input hold time
tDH
0.8
-
1
-
ns
1
Address setup time
tAS
1.5
-
2
-
ns
1
Address hold time
tAH
0.8
-
1
-
ns
1
CKE setup time
tCKS
1.5
-
2
-
ns
1
CKE hold time
tCKH
0.8
-
1
-
ns
1
Command setup time
tCS
1.5
-
2
-
ns
1
Command hold time
tCH
0.8
-
1
-
ns
1
CLK to data output in low Z-time
tOLZ
1.5
-
1
-
ns
CLK to data output in
high Z-time
CAS Latency = 3
tOHZ3
ns
5.4
CAS Latency = 2
tOHZ2
6
ns
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v
3.Data-out hold time to be measured under 30pF load condition, without Vt termination
Rev. 0.3/Nov. 01
8
HY5V22GF
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
-H
Parameter
-P
Symbol
Unit
Min
Max
Min
Max
Operation
tRC
65
-
70
-
ns
Auto Refresh
tRRC
65
-
70
-
ns
RAS to CAS delay
tRCD
20
-
20
-
ns
RAS active time
tRAS
45
120K
50
120K
ns
RAS precharge time
tRP
20
-
20
-
ns
RAS to RAS bank active delay
tRRD
15
-
20
-
CLK
CAS to CAS delay
tCCD
1
-
1
-
CLK
Write command to data-in delay
tWTL
0
-
0
-
CLK
Data-in to precharge command
tDPL
1
-
1
-
CLK
Data-in to active command
tDAL
4
-
3
-
CLK
DQM to data-out Hi-Z
tDQZ
2
-
2
-
CLK
DQM to data-in mask
tDQM
0
-
0
-
CLK
MRS to new command
tMRD
1
-
1
-
CLK
CAS Latency = 3
tPROZ3
3
-
3
-
CLK
CAS Latency = 2
tPROZ2
2
-
2
-
CLK
Power down exit time
tPDE
1
-
1
-
CLK
Self refresh exit time
tSRE
1
-
1
-
CLK
Refresh Time
tREF
-
64
-
64
ms
Note
RAS cycle time
Precharge to data
output Hi-Z
1
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 0.3/Nov. 01
9
HY5V22GF
DEVICE OPERATING OPTION TABLE
HY5V22GF-H
133MHz(7.5ns)
125MHz(8ns)
100MHz(10ns)
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
3CLKs
3CLKs
2CLKs
3CLKs
3CLKs
2CLKs
6CLKs
6CLKs
5CLKs
9CLKs
9CLKs
7CLKs
3CLKs
3CLKs
2CLKs
5.4ns
6ns
6ns
2.7ns
3ns
3ns
HY5V22GF-P
100MHz(10ns)
83MHz(12ns)
66MHz(15ns)
Rev. 0.3/Nov. 01
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
5CLKs
5CLKs
4CLKs
7CLKs
7CLKs
6CLKs
2CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
10
HY5V22GF
COMMAND TRUTH TABLE
Command
A10/
AP
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
Mode Register Set
H
X
L
L
L
L
X
OP code
H
X
X
X
No Operation
H
X
X
X
L
H
H
H
Bank Active
H
X
L
L
H
H
X
H
X
L
H
L
H
X
ADDR
RA
Read
L
V
H
Write
L
H
X
L
H
L
L
X
CA
Write with Autoprecharge
H
X
L
L
H
L
X
Burst Stop
H
DQM
H
Auto Refresh
H
H
L
L
L
Entry
H
L
L
L
H
X
Exit
L
H
H
X
L
H
H
L
X
L
V
X
X
V
X
H
X
X
L
H
X
X
X
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
L
Precharge
power down
H
X
Precharge selected Bank
Entry
V
H
Precharge All Banks
X
X
Exit
Clock
Suspend
Note
V
CA
Read with Autoprecharge
Self Refresh1
BA
Entry
Exit
L
H
L
H
X
L
H
X
X
X
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Rev. 0.3/Nov. 01
11
HY5V22GF
PACKAGE INFORMATION
Rev. 0.3/Nov. 01
12
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