Cypress CY7C1049BNV33-15VC 512k x 8 static ram Datasheet

CY7C1049BNV33
512K x 8 Static RAM
Functional Description[1]
Features
• High speed
— tAA = 12 ns
• Low active power
— 504 mW (max.)
• Low CMOS standby power (Commercial L version)
— 1.8 mW (max.)
• 2.0V Data Retention (660 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
The CY7C1049BNV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049BNV33 is available in a standard 400-mil-wide
36-pin SOJ and 44-pin TSOPII packages with center power
and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configuration
TSOP
Top View
SOJ
Top View
I/O0
INPUTBUFFER
CE
I/O1
I/O2
512K x 8
ARRAY
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
I/O3
I/O4
I/O5
COLUMN
DECODER
I/O6
POWER
DOWN
I/O7
OE
A 11
A 12
A 13
A 14
A 15
A 16
A17
A18
WE
Cypress Semiconductor Corporation
Document #: 001-06432 Rev. **
•
198 Champion Court
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
•
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VCC
VSS
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
VSS
VCC
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
San Jose, CA 95134-1709
•
408-943-2600
Revised February 1, 2006
[+] Feedback
CY7C1049BNV33
Selection Guide
-12
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
-15
-20
12
15
20
Com’l
200
180
160
Ind’l
220
200
170
8
8
8
0.5
0.5
0.5
Com’l/Ind’l
Com’l
L
DC Input Voltage[2] ................................ –0.5V to VCC + 0.5V
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Operating Range
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Range
Ambient
Temperature
VCC
Supply Voltage on VCC to Relative GND[2].....–0.5V to +4.6V
Commercial
0°C to +70°C
3.3V ± 0.3V
Industrial
DC Voltage Applied to Outputs[2]
in High Z State .......................................–0.5V to VCC + 0.5V
–40°C to +85°C
DC Electrical Characteristics Over the Operating Range
-12
Parameter
Description
Test Conditions
VOH
Output HIGH
Voltage
VOL
Output LOW Voltage VCC = Min.,
IOL = 8.0 mA
Min.
VCC = Min.,
IOH = –4.0 mA
-15
Max.
2.4
Min.
-20
Max.
2.4
0.4
Min.
Max.
2.4
0.4
Unit
V
0.4
V
VIH
Input HIGH Voltage
2.2 VCC + 0.5
2.2
VCC + 0.5
2.2
VCC + 0.5
V
VIL
Input LOW Voltage[2]
–0.5
0.8
–0.5
0.8
–0.5
0.8
V
IIX
Input Leakage
Current
GND < VI < VCC
–1
+1
–1
+1
–1
+1
µA
IOZ
Output Leakage
Current
GND < VOUT < VCC,
Output Disabled
–1
+1
–1
+1
–1
+1
µA
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
ISB1
Automatic CE
Power-Down
Current
—TTL Inputs
ISB2
Automatic CE
Power-Down
Current
—CMOS Inputs
Com’l
200
180
160
mA
Ind’l
220
200
170
mA
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
30
30
30
mA
Max. VCC,
Com’l/Ind’l
CE > VCC – 0.3V,
Com’l L
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
8
8
8
mA
0.5
0.5
0.5
mA
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max.
Unit
8
pF
8
pF
Notes:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
2. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06432 Rev. **
Page 2 of 8
[+] Feedback
CY7C1049BNV33
AC Test Loads and Waveforms
R1 317Ω
3.3V
THÉVENIN EQUIVALENT
167Ω
OUTPUT
OUTPUT
30 pF
R2
351Ω
ALL INPUT PULSES
1.73V
3.3V
90%
(b)
GND
INCLUDING
JIG AND
SCOPE
(a)
90%
10%
10%
RiseTime:1 V/ns
Fall time:
1 V/ns
AC Switching Characteristics[4] Over the Operating Range
-12
Parameter
Description
Min.
-15
Max.
Min.
-20
Max.
Min.
Max.
Unit
Read Cycle
tpower
VCC (typical) to the First Access[5]
1
1
1
µs
tRC
Read Cycle Time
12
15
20
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
12
3
15
3
20
3
ns
ns
tACE
CE LOW to Data Valid
12
15
20
ns
tDOE
OE LOW to Data Valid
6
7
8
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High
0
Z[6, 7]
Z[7]
tLZCE
CE LOW to Low
tHZCE
CE HIGH to High Z[6, 7]
tPU
CE LOW to Power-Up
tPD
Write Cycle
0
6
3
7
3
6
0
CE HIGH to Power-Down
0
8
3
7
0
12
ns
ns
8
0
15
ns
ns
ns
20
ns
[8, 9]
tWC
Write Cycle Time
12
15
20
ns
tSCE
CE LOW to Write End
10
12
13
ns
tAW
Address Set-Up to Write End
10
12
13
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
10
12
13
ns
tSD
Data Set-Up to Write End
7
8
9
ns
tHD
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z[7]
3
3
3
ns
tHZWE
[6, 7]
WE LOW to High Z
6
7
8
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. T.power time has to be provided initially before a read/write operation is
started.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
10. No input may exceed VCC + 0.5V
11. .tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 ns and slower speeds.
Document #: 001-06432 Rev. **
Page 3 of 8
[+] Feedback
CY7C1049BNV33
Data Retention Characteristics Over the Operating Range (For L version only)
Parameter
Conditions[10]
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[3]
Chip Deselect to Data Retention
Time
tR[11]
Operation Recovery Time
Min.
Max
2.0
VCC = VDR = 2.0V,
CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V
Unit
V
330
µA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
3.0V
VCC
3.0V
VDR > 2V
tR
tCDR
CE
Switching Waveforms
Read Cycle No. 1[12, 13]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZCE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
ICC
50%
ISB
Notes:
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 001-06432 Rev. **
Page 4 of 8
[+] Feedback
CY7C1049BNV33
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled, OE HIGH During Write)[15, 16]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 17
tHZOE
Write Cycle No. 2 (WE Controlled, OE LOW)[16]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
NOTE 17
DATA I/O
tHD
DATA VALID
tLZWE
tHZWE
Truth Table
CE
OE
WE
I/O0 – I/O7
Mode
Power
H
X
X
High Z
Power-Down
Standby (ISB)
L
L
H
Data Out
Read
Active (ICC)
L
X
L
Data In
Write
Active (ICC)
L
H
H
High Z
Selected, Outputs Disabled
Active (ICC)
Notes:
15. Data I/O is high-impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
17. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 001-06432 Rev. **
Page 5 of 8
[+] Feedback
CY7C1049BNV33
Ordering Information
Speed
(ns)
12
15
20
Package
Name
Ordering Code
Package Type
CY7C1049BNV33-12ZC
51-85087
44-Pin TSOP II Z44
CY7C1049BNV33-12VXC
51-85090
36-Lead (400-Mil) Molded SOJ (Pb-free)
CY7C1049BNV33-12VI
51-85090
36-Lead (400-Mil) Molded SOJ
CY7C1049BNV33-12VXI
51-85090
36-Lead (400-Mil) Molded SOJ (Pb-free)
CY7C1049BNV33-15VC
51-85090
36-Lead (400-Mil) Molded SOJ
CY7C1049BNV33-15VXC
51-85090
36-Lead (400-Mil) Molded SOJ (Pb-free)
CY7C1049BNV33L-15VXC
51-85090
36-Lead (400-Mil) Molded SOJ (Pb-free)
CY7C1049BNV33-15ZC
51-85087
44-Pin TSOP II Z44
CY7C1049BNV33-15VI
51-85090
36-Lead (400-Mil) Molded SOJ
CY7C1049BNV33-15VXI
51-85090
36-Lead (400-Mil) Molded SOJ (Pb-free)
CY7C1049BNV33-15ZI
51-85087
44-Pin TSOP II Z44
CY7C1049BNV33-20VC
51-85090
36-Lead (400-Mil) Molded SOJ
CY7C1049BNV33-20VXC
51-85090
36-Lead (400-Mil) Molded SOJ (Pb-free)
CY7C1049BNV33-20VXI
51-85090
36-Lead (400-Mil) Molded SOJ (Pb-free)
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Please contact local sales representative regarding availability of these parts
\\
Package Diagrams
36-pin (400-Mil) Molded SOJ (51-85090)
51-85090-*B
Document #: 001-06432 Rev. **
Page 6 of 8
[+] Feedback
CY7C1049BNV33
Package Diagrams (continued)
44-Pin TSOP II Z44 (51-85087)
51-85087-*A
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-06432 Rev. **
Page 7 of 8
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
CY7C1049BNV33
Document History Page
Document Title: CY7C1049BNV33 512K x 8 Static RAM
Document Number: 001-06432
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
423847
See ECN
NXR
Document #: 001-06432 Rev. **
Description of Change
New Data Sheet
Page 8 of 8
[+] Feedback
Similar pages