MOTOROLA MCM69L736AZP7.5R 4m late write hstl Datasheet

MOTOROLA
Order this document
by MCM69L736A/D
SEMICONDUCTOR TECHNICAL DATA
Advance Information
4M Late Write HSTL
MCM69L736A
MCM69L818A
The MCM69L736A/818A is a 4M synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM69L818A
(organized as 256K words by 18 bits) and the MCM69L736A (organized as 128K
words by 36 bits) are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.
The differential clock (CK) inputs control the timing of read/write operations of
the RAM. At the rising edge of CK, all addresses, write enables, and synchronous
selects are registered. An internal buffer and special logic enable the memory to
accept write data on the rising edge of CK a cycle after address and control
signals. Read data is available at the falling edge of CK.
The RAM uses HSTL inputs and outputs. The adjustable input trip–point (Vref)
and output voltage (VDDQ) gives the system designer greater flexibility in
optimizing system performance.
The synchronous write and byte enables allow writing to individual bytes or the
entire word.
The impedance of the output buffers is programmable, allowing the outputs to
match the impedance of the circuit traces which reduces signal reflections.
ZP PACKAGE
PBGA
CASE 999–01
•
•
•
•
•
•
•
•
•
•
•
Byte Write Control
Single 3.3 V +10%, – 5% Operation
HSTL — I/O (JEDEC Standard JESD8–6 Class I)
HSTL — User Selectable Input Trip–Point
HSTL — Compatible Programmable Impedance Output Drivers
Register to Latch Synchronous Operation
Asynchronous Output Enable
Boundary Scan (JTAG) IEEE 1149.1 Compatible
Differential Clock Inputs
Optional x18 or x36 Organization
MCM69L736A/818A–7.5 = 7.5 ns
MCM69L736A/818A–8.5 = 8.5 ns
MCM69L736A/818A–9.5 = 9.5 ns
MCM69L736A/818A–10.5 = 10.5 ns
• 119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array
(PBGA) Package
This document contains information on a new product. Specifications and information herein are subject to change without notice.
4/3/97
 Motorola, Inc. 1997
MOTOROLA
FAST SRAM
MCM69L736A•MCM69L818A
1
FUNCTIONAL BLOCK DIAGRAM
ADDRESS
REGISTERS
SA
DATA IN
REGISTER
MEMORY
ARRAY
DQ
DATA OUT
LATCH
SW
SW
REGISTERS
SBx
CONTROL
LOGIC
CK
G
SS
REGISTERS
SS
PIN ASSIGNMENTS
TOP VIEW
MCM69L736A
A
B
C
D
MCM69L818A
1
2
3
4
5
6
7
VDDQ
SA
SA
NC
SA
SA
VDDQ
NC
NC
DQc
NC
SA
DQc
SA
SA
VSS
NC
VDD
ZQ
SA
SA
VSS
NC
SA
DQb
NC
NC
DQb
E
DQc
VDDQ DQc
VSS
SS
VSS
G
VSS
VSS
DQb
K
DQb VDDQ
DQc
DQc
DQc
VDDQ VDD
DQd
DQd
SBc
VSS
Vref
VSS
NC
NC
VDD
CK
SBb
VSS
Vref
VSS
DQb
DQb
DQb
VDD VDDQ
DQa
DQa
DQd
DQd
T
U
4
5
6
7
VDDQ
SA
SA
NC
SA
SA
VDDQ
NC
NC
SA
NC
SA
NC
NC
NC
SA
SA
VDD
SA
SA
NC
DQb
NC
VSS
ZQ
VSS
DQa
NC
NC
DQb
VSS
SS
VSS
NC
DQa
VDDQ
NC
VSS
G
VSS
DQa VDDQ
NC
DQb
SBb
NC
VSS
NC
DQa
J
DQb
NC
VSS
NC
VSS
DQa
NC
K
VDDQ VDD
Vref
VDD
Vref
VDD VDDQ
SBd
CK
SBa
DQa
DQa
NC
DQb
VSS
CK
VSS
NC
DQa
DQb
NC
VSS
CK
SBa
DQa
NC
VDDQ DQb
VSS
SW
VSS
NC VDDQ
M
VDDQ DQd
R
H
L
M
P
F
DQb
L
N
D
3
G
DQc
J
C
DQb
G
H
B
2
E
DQc
F
A
1
DQd
DQd
NC
NC
DQd
DQd
SA
NC
VDDQ TMS
VSS
VSS
VSS
VDD
SA
TDI
SW
SA
SA
VDD
SA
TCK
MCM69L736A•MCM69L818A
2
VSS
VSS
VSS
VSS
SA
TDO
DQa VDDQ
DQa
DQa
SA
NC
DQa
DQa
NC
ZZ
NC VDDQ
N
P
R
DQb
NC
VSS
SA
VSS
DQa
NC
NC
DQb
VSS
SA
VSS
NC
DQa
NC
SA
VDD
VDD
VSS
SA
NC
NC
SA
SA
NC
SA
SA
ZZ
TDI
TCK
TDO
T
U
VDDQ TMS
NC VDDQ
MOTOROLA FAST SRAM
MCM69L736A PIN DESCRIPTIONS
PBGA Pin Locations
Symbol
Type
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,
5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T
SA
Input
Synchronous Address Inputs: Registered on the rising clock edge.
4K
CK
Input
Address, data in, and control input register clock. Active high.
4L
CK
Input
Address, data in, and control input register clock. Active low.
4M
SW
Input
Synchronous Write: Registered on the rising clock edge, active low.
Writes all enabled bytes.
5L, 5G, 3G, 3L
(a), (b), (c), (d)
SBx
Input
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
4E
SS
Input
Synchronous Chip Enable: Registered on the rising clock edge, active
low.
4F
G
Input
Output Enable: Asynchronous pin, active low.
2U
TMS
Input
Test Mode Select (JTAG).
3U
TDI
Input
Test Data In (JTAG).
4U
TCK
Input
Test Clock (JTAG).
5U
TDO
Output
4D
ZQ
Input
Programmable Output Impedance: Programming pin.
7T
ZZ
Input
Reserved for future use. Must be grounded.
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P
DQx
I/O
3J, 5J
Vref
Supply
Input Reference: Provides reference voltage for input buffers.
4C, 2J, 4J, 6J, 4R, 3R
VDD
Supply
Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
VDDQ
Supply
Output Power Supply: Provides operating power for output buffers.
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H,
3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 5R
VSS
Supply
Ground.
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C,
4G, 4H, 1R, 7R, 1T, 2T, 6T, 6U
NC
—
MOTOROLA FAST SRAM
Description
Test Data Out (JTAG).
Synchronous Data I/O.
No Connection: There is no connection to the chip.
MCM69L736A•MCM69L818A
3
MCM69L818A PIN DESCRIPTIONS
PBGA Pin Locations
Symbol
Type
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C,
6C, 4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T
SA
Input
Synchronous Address Inputs: Registered on the rising clock edge.
4K
CK
Input
Address, data in, and control input register clock. Active high.
4L
CK
Input
Address, data in, and control input register clock. Active low.
4M
SW
Input
Synchronous Write: Registered on the rising clock edge, active low.
Writes all enabled bytes.
5L, 3G
(a), (b)
SBx
Input
Synchronous Byte Write Enable: Enables writes to byte x in
conjunction with the SW input. Has no effect on read cycles, active
low.
4E
SS
Input
Synchronous Chip Enable: Registered on the rising clock edge, active
low.
2U
TMS
Input
Test Mode Select (JTAG).
3U
TDI
Input
Test Data In (JTAG).
4U
TCK
Input
Test Clock (JTAG).
5U
TDO
Output
4D
ZQ
Input
Programmable Output Impedance: Programming pin.
4F
G
Input
Output Enable: Asynchronous pin, active low.
7T
ZZ
Input
Reserved for future use. Must be grounded.
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P
DQx
I/O
3J, 5J
Vref
Supply
Input Reference: Provides reference voltage for input buffers.
Description
Test Data Out (JTAG).
Synchronous Data I/O.
4C, 2J, 4J, 6J, 4R, 3R
VDD
Supply
Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
VDDQ
Supply
Output Power Supply: Provides operating power for output buffers.
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 5R
VSS
Supply
Ground.
4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C,
2D, 7D, 1E, 6E, 2F, 1G, 4G, 6G,
2H, 4H, 7H, 1K, 6K, 2L, 7L, 6M, 2N,
7N, 1P, 6P, 1R, 7R, 1T, 4T, 6U
NC
—
MCM69L736A•MCM69L818A
4
No Connection: There is no connection to the chip.
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS, See Note 1)
Symbol
Value
Unit
VDD
– 0.5 to + 4.6
V
VDDQ
– 0.5 to VDD + 0.5
V
Voltage On Any Pin
Vin
– 0.5 to VDD + 0.5
V
Input Current (per I/O)
Iin
± 50
mA
Output Current (per I/O)
Iout
± 70
mA
Power Dissipation (See Note 2)
PD
—
W
Operating Temperature
TA
0 to + 70
°C
Temperature Under Bias
Tbias
–10 to + 85
°C
Tstg
– 55 to + 125
°C
Rating
Core Supply Voltage
Output Supply Voltage
Storage Temperature
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. Power dissipation capability will be dependent upon package characteristics and use
environment. See enclosed thermal impedance data.
PBGA PACKAGE THERMAL CHARACTERISTICS
Rating
Junction to Ambient (Still Air)
Symbol
Max
Unit
Notes
RθJA
53
°C/W
1, 2
1, 2
Junction to Ambient (@200 ft/min)
Single Layer Board
RθJA
38
°C/W
Junction to Ambient (@200 ft/min)
Four Layer Board
RθJA
22
°C/W
Junction to Board (Bottom)
RθJB
14
°C/W
3
Junction to Case (Top)
RθJC
5
°C/W
4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC–883
Method 1012.1).
MOTOROLA FAST SRAM
MCM69L736A•MCM69L818A
5
DC OPERATING CONDITIONS AND CHARACTERISTICS
(0_C ≤ TA ≤ 70_C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (See Notes 1 through 4)
Symbol
Min
Typical
–7.5
Typical
–8.5
Typical
–9.5
Typical
–10.5
Max
Unit
Notes
Input Reference DC Voltage
Vref (dc)
0.6
—
—
—
—
1.1
V
11
Core Power Supply Voltage
VDD
3.15
—
—
—
—
3.6
V
VDDQ
1.4
—
—
—
—
1.6
V
IDD1
—
—
300
390
290
380
270
360
260
350
450
560
mA
5
Quiescent Active Power Supply Current)
IDD2
—
190
190
190
190
250
mA
6, 10
Active Standby Power Supply Current
ISB1
—
160
160
160
160
250
mA
7
Quiescent Standby Power Supply Current
ISB2
—
140
140
140
140
230
mA
8, 10
Sleep Mode Power Supply Current
ISB3
—
TBD
TBD
TBD
TBD
TBD
mA
9, 10
Parameter
Output Driver Supply Voltage
Active Power Supply Current
(x18)
(x36)
NOTES:
1. All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS bumps.
2. Supply voltage applied to VDD connections.
3. Supply voltage applied to VDDQ connections.
4. All power supply currents measured with outputs open or deselected.
5. VDD = VDD (max), tKHKH = tKHKH (min), SS registered active, 50% read cycles.
6. VDD = VDD (max), tKHKH = dc, SS registered active.
7. VDD = VDD (max), tKHKH = tKHKH (min), SS registered inactive.
8. VDD = VDD (max), tKHKH = dc, SS registered inactive, ZZ low.
9. VDD = VDD (Max), tKHKH = dc, registered inactive, ZZ high.
10. 200 mV ≥ Vin ≥ VDDQ – 200 mV.
11. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak to peak ac component
superimposed on Vref may not exceed 5% of the dc component of Vref.
DC INPUT CHARACTERISTICS
Parameter
Symbol
Min
Max
Unit
DC Input Logic High
VIH (dc)
Vref + 0.1
VDD + 0.3
V
DC Input Logic Low
VIL (dc)
– 0.3
Vref – 0.1
V
1
Input Reference DC Voltage
Vref (dc)
0.6
1.1
V
2
Ilkg(1)
—
±5
µA
3
Vin
– 0.3
VDD + 0.3
V
Clock Input Differential Voltage
VDIF (dc)
0.1
VDD + 0.6
V
4
Clock Input Common Mode Voltage Range (See Figure 3)
VCM (dc)
0.68
1.1
V
5
VX
0.68
1.1
V
Input Leakage Current
Clock Input Signal Voltage
Clock Input Crossing Point Voltage Range
Notes
NOTES:
1. Inputs may undershoot to – 0.5 V (peak) for up to 20% tKHKH (e.g., 2 ns at a clock cycle time of 10 ns).
2. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak–to–peak ac component
superimposed on Vref may not exceed 5% of the dc component of Vref.
3. 0 V ≤ Vin ≤ VDDQ for all pins.
4. Minimum instantaneous differential input voltage required for differential input clock operation.
5. Maximum rejectable common mode input voltage variation.
MCM69L736A•MCM69L818A
6
MOTOROLA FAST SRAM
DC OUTPUT BUFFER CHARACTERISTICS – PROGRAMMABLE IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE
(0_C ≤ TA ≤ 70_C, Unless Otherwise Noted, See Notes 5 and 6)
Parameter
Symbol
Min
Max
Unit
Notes
Output Logic Low
VOL
VDDQ/2 – 0.025
VDDQ/2 +0.025
V
1
Output Logic High
VOH
VDDQ/2 – 0.025
VDDQ/2 + 0.025
V
2
Light Load Output Logic Low
VOL1
VSS
0.2
V
3
Light Load Output Logic High
VOH1
VDDQ – 0.2
VDDQ
V
4
NOTES:
1. IOL = (VDDQ/2)/(RQ/5) for values of RQ = 175 Ω ≤ RQ ≤ 350 Ω.
2. | IOH | = (VDDQ/2)/(RQ/5) for values of RQ = 175 Ω ≤ RQ ≤ 350 Ω.
3. IOL ≤ 100 µA.
4. | IOH | ≤ 100 µA.
5. The impedance controlled mode is expected to be used in point–to–point applications, driving high impedance inputs.
6. The ZQ pin is connected through RQ to VSS for the controlled impedance mode.
DC OUTPUT BUFFER CHARACTERISTICS — MINIMUM IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE
(0_C ≤ TA ≤ 70_C, ZQ = VDD) (See Notes 1 and 2)
Parameter
Symbol
Min
Max
Unit
Notes
Output Logic Low
VOL2
VSS
0.4
V
3
Output Logic High
VOH2
VDDQ – 0.4
VDDQ
V
4
Light Load Output Logic Low
VOL3
VSS
0.2
V
5
Light Load Output Logic High
VOH3
VDDQ – 0.2
VDDQ
V
6
NOTES:
1. The push–pull output mode is expected to be used in bussed applications and may be series or parallel terminated. Conforms to the JEDEC
Standard JESD8–6 Class I.
2. The ZQ pin is connected to VDD to enable the minimum impedance mode.
3. IOL ≤ 8 mA.
4. IOH ≤ 8 mA.
5. IOL ≤ 100 µA.
6. IOH ≤ 100 µA.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, 0_C ≤ TA ≤ 70_C, Periodically Sampled Rather Than 100% Tested)
Characteristic
Symbol
Typ
Max
Unit
Input Capacitance
Cin
4
5
pF
Input/Output Capacitance
CI/O
7
8
pF
CK, CK Capacitance
CCK
4
5
pF
MOTOROLA FAST SRAM
MCM69L736A•MCM69L818A
7
AC OPERATING CONDITIONS AND CHARACTERISTICS
(0_C ≤ TA ≤ 70_C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.25 to 1.25 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . 0.75 V
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 0.75 V
Clock Input Timing Reference Level . . . . . . Differential Cross–Point
RQ for 50 Ω Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Ω
READ/WRITE CYCLE TIMING (See Note 3)
MCM69L736A–7.5
MCM69L818A–7.5
Parameter
MCM69L736A–8.5
MCM69L818A–8.5
MCM69L736A–9.5
MCM69L818A–9.5
MCM69L736A–10.5
MCM69L818A–10.5
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Cycle Time
tKHKH
7
—
8
—
9
—
10
—
ns
Clock High Pulse Width
tKHKL
2.8
—
3.2
—
3.6
—
4
—
ns
Clock Low Pulse Width
tKLKH
2.8
—
3.2
—
3.6
—
4
—
ns
Clock High to Output
Valid
tKHQV
—
7.5
—
8.5
—
9.5
—
10.5
ns
2
Clock Low to Output
Valid
tKLQV
—
3.5
—
4
—
4
—
4
ns
2
Clock Low to Output
Hold
tKLQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
2
Clock Low to Output
Low–Z
tKLQX1
1
—
1
—
1
—
1
—
ns
3
Clock High to Output
High–Z
tKHQZ
—
3.5
—
4
—
4
—
4
ns
3
Output Enable Low to
Output Low–Z
tGLQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
3
Output Enable Low to
Output Valid
tGLQV
—
3.5
—
4
—
4
—
4
ns
2
Output Enable to Output
Hold
tGHQX
0.5
—
0.5
—
0.5
—
0.5
—
ns
2
Output Enable High to
Output High–Z
tGHQZ
—
3.5
—
4
—
4
—
4
ns
3
Setup Times:
Address
Data In
Chip Select
Write Enable
tAVKH
tDVKH
tSVKH
tWVKH
0.5
—
0.5
—
0.5
—
0.5
—
ns
Hold Times:
Address
Data In
Chip Select
Write Enable
tKHAX
tKHDX
tKHSX
tKHWX
1
—
1
—
1
—
1
—
ns
NOTES:
1. Measured at ± 200 mV from steady state.
2. In no case may control input signals (e.g., SS) be operated with pulse widths less than the minimum clock input pulse width specifications
(e.g., tKHKL) or at frequencies that exceed the applied K clock frequency.
3. Tested per AC Test Load diagram. See Figure 1.
TIMING LIMITS
0.75 V
VDDQ/2
Vref
DEVICE
UNDER
TEST
ZQ
50 Ω
50 Ω
250 Ω
The table of timing values shows either a minimum or a
maximum limit for each parameter. Input requirements are
specified from the external system point of view. Thus, address setup time is shown as a minimum since the system
must supply at least that much time. On the other hand, responses from the memory are specified from the device
point of view. Thus, the access time is shown as a maximum
since the device never provides data later than that time.
Figure 1. AC Test Load
MCM69L736A•MCM69L818A
8
MOTOROLA FAST SRAM
AC INPUT CHARACTERISTICS
Parameter
Symbol
Min
Max
Notes
AC Input Logic High (See Figure 4)
VIH (ac)
Vref + 200 mV
AC Input Logic Low (See Figures 2 and 4)
VIL (ac)
Vref – 200 mV
1
Input Reference Peak to Peak ac Voltage
Vref (ac)
5% Vref (dc)
2
Clock Input Differential Voltage
Vdif (ac)
VDDQ + 600 mV
3
400 mV
NOTES:
1. Inputs may undershoot to – 0.5 V (peak) for up to 20% tKHKH (e.g., 2 ns at a clock cycle time of 10 ns).
2. Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak to peak ac component
superimposed on Vref may not exceed 5% of the dc component of Vref.
3. Minimum instantaneous differential input voltage required for differential input clock operation.
VOH
VSS
50%
100%
20% tKHKH
Figure 2. Undershoot Voltage
VDDQ
VTR
CROSSING POINT
VDIF
VCP
VCM*
VSS
*VCM, the Common Mode Input Voltage, equals VTR – ((VTR – VCP)/2).
Figure 3. Differential Inputs/Common Mode Input Voltage
VIH(ac)
Vref
VIL(ac)
Figure 4. Differential Inputs/Common Mode Input Voltage
MOTOROLA FAST SRAM
MCM69L736A•MCM69L818A
9
REGISTER LATCH READ–WRITE–READ CYCLES
t KHKH
t KHKL
CK
t AVKH
t KLKH
t KHAX
SA
A0
A1
A2
A3
t SVKH
A4
t KHSX
SS
t WVKH
t KHWX
SW
SBx
G
t KLQX
t KHQV
t KLQV
t KLQX1
DQ
t KHQZ
Q0
READ
MCM69L736A•MCM69L818A
10
t KHQZ
t DVKH
t KHDX
Q1
READ
D2
WRITE
t KLQX1
Q3
READ
Q4
DESELECT (HIGH–Z)
READ
MOTOROLA FAST SRAM
REGISTER LATCH READ–WRITE–READ CYCLES
(G Controlled)
CK
SA
A0
A1
A2
A3
A4
SS
SW
SBx
G
t GLQV
t GLQX
t GHQZ
DQ
Q0
READ
MOTOROLA FAST SRAM
Q1
READ
D2
Q3
WRITE
READ
t GHQX
Q4
DESELECT (HIGH–Z)
READ
MCM69L736A•MCM69L818A
11
FUNCTIONAL OPERATION
READ AND WRITE OPERATIONS
All control signals except G are registered on the rising
edge of CK. These signals must meet the setup and hold
times shown in the AC Characteristics table. On the falling
edge of the current cycle, the output latch becomes transparent and data is available. The output data is latched on
the rising edge of the next clock. The output data is available
at the output at t KLQV or t KHQV, whichever is later.
tKHQV is the internal latency of the device. During this same
cycle, a new read address can be applied to the address
pins.
A write cycle can occur on the next cycle as long as
tKLQX and tDVKH are met. Read cycles may follow write
cycles immediately.
G, SS, and SW control output drive. Chip deselect via a
high on SS at the rising edge of CK has its effect on the output drivers immediately. SW low deselects the output drivers
immediately (on the same cycle). Output selecting via a low
on SS and high on SW at a rising CK has its effect on the
output drivers at tKLQX. Output drive is also controlled directly by output enable (G). G is an asynchronous input. No clock
edges are required to enable or disable the output with G.
Output data will be valid at tGLQV, tKHQV, or tKLQV, which is
even later. Outputs will begin driving at tKLQX1. Outputs will
hold previous data until tKLQX or tGHQX.
WRITE AND BYTE WRITE FUNCTIONS
Note that in the following discussion the term “byte” refers
to nine bits of the RAM I/O bus. In all cases, the timing parameters described for synchronous write input (SW) apply
to each of the byte write enable inputs (SBa, SBb, etc.).
Byte write enable inputs have no effect on read cycles.
This allows the system designer not interested in performing
byte writes to connect the byte enable inputs to active low
(VSS). Reads of all bytes proceed normally and write cycles,
activated via a low on SW and the rising edge of CK, write
the entire RAM I/O width. This way the designer is spared
having to drive multiple write input buffer loads.
Byte writes are performed using the byte write enable inputs in conjunction with the synchronous write input (SW). It
is important to note that writing any one byte will inhibit a read
of all bytes at the current address. The RAM cannot simultaneously read one byte and write another at the same address. A write cycle initiated with none of the byte write
MCM69L736A•MCM69L818A
12
enable inputs active is neither a read or a write. No write will
occur, but the outputs will be deselected as in a normal write
cycle.
LATE WRITE
The write address is sampled on the first rising edge of
clock, and write data is sampled on the following rising edge.
The late write feature is implemented with single stage
write buffering. Write buffering is transparent to the user. A
comparator monitors the address bus and, when necessary,
routes buffer contents to the outputs to ensure coherent operation. This occurs in all cases whether there is a byte write
or a full word is written.
PROGRAMMABLE IMPEDANCE OPERATION
The designer can program the RAMs output buffer impedance by terminating the ZQ pin to VSS through a precision
resistor (RQ). The value of RQ is five times the output impedance desired. For example, 250 Ω resistor will give an output
impedance of 50 Ω.
Impedance updates occur continuously and the frequency
of the update is based on the subdivided K clock. Note that if
the K clock stops so does the impedance update.
The actual change in the impedance occurs in small increments and is monotonic. There are no significant disturbances that occur on the output because of this smooth
update method.
The impedance update is not related to any particular type
of cycle because the impedance is updated continuously and
is based on the K clock. Updates occur regardless of whether the the device is performing a read, write or a deselect
cycle and does not depend on the state of G.
At power up, the output impedance defaults to approximately 50 ohms. It will take 4,000 to 16,000 cycles for the impedance to be completely updated if the programmed
impedance is much higher or lower than 50 Ω.
The output buffers can also be programmed in a minimum
impedance configuration by connecting ZQ to VDD.
POWER UP AND INITIALIZATION
Once supplies have reached specification levels, a
minimum dwell of 1.0 µs with CK inputs cycling is required
before beginning normal operations. At power up the output
impedance will be set at approximately 50 Ω , however, in
order to match the programmed impedance the part requires
deselect cycles to occur.
MOTOROLA FAST SRAM
SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION
OVERVIEW
The serial boundary scan test access port (TAP) on this
RAM is designed to operate in a manner consistent with
IEEE 1149.1–1990 (commonly referred to as JTAG), but
does not implement all of the functions required for 1149.1
compliance. Certain functions have been modified or eliminated because their implementation places extra delays in
the RAMs critical speed path. Nevertheless, the RAM supports the standard TAP controller architecture. The TAP controller is the state machine that controls the TAP operation
and can be expected to function in a manner that does not
conflict with the operation of devices with IEEE 1149.1
compliant TAPs. The TAP operates using conventional
JEDEC Standard 8–1B low voltage (3.3 V) TTL/CMOS logic
level signaling.
DISABLING THE TEST ACCESS PORT
It is possible to use this device without utilizing the TAP. To
disable the TAP controller without interfering with normal
operation of the device, TCK must be tied to VSS to preclude
mid–level inputs. TDI and TMS are designed so an undriven
input will produce a response identical to the application of a
logic one, and may be left unconnected. But they may also
be tied to VDD through a 1 k resistor. TDO should be left
unconnected.
TAP DC OPERATING CHARACTERISTICS
(0_C ≤ TA ≤ 70_C, Unless Otherwise Noted)
Parameter
Symbol
Min
Max
Unit
Logic Input Logic High
VIH1
2.0
VDD + 0.3
V
Logic Input Logic Low
VIL1
– 0.3
0.8
V
Notes
Ilkg
—
±5
µA
1
CMOS Output Logic Low
VOL1
—
0.2
V
2
CMOS Output Logic High
VOH1
VDD – 0.2
—
V
3
TTL Output Logic Low
VOL2
—
0.4
V
4
TTL Output Logic High
VOH2
2.4
—
V
5
Logic Input Leakage Current
NOTES:
1. 0 V ± Vin ± VDDQ for all logic input pins.
2. IOL1 ≤ 100 µA @ VOL = 0.2 V. Sampled, not 100% tested.
3. IOH1 ≤ 100 µA @ VDDQ – 0.2 V. Sampled, not 100% tested.
4. IOL2 ≤ 8 mA @ VOL = 0.4 V.
5. IOH2 ≤ 8 mA @ VOH = 2.4 V.
MOTOROLA FAST SRAM
MCM69L736A•MCM69L818A
13
TAP AC OPERATING CONDITIONS AND CHARACTERISTICS
(0_C ≤ TA ≤ 70_C, Unless Otherwise Noted)
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1 V/ns (20% to 80%)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Test Load . . . . . . 50 Ω Parallel Terminated T–line with 20 pF
Receiver Input Capacitance
Test Load Termination Supply Voltage (VT) . . . . . . . . . . . . . . . 1.5 V
TAP CONTROLLER TIMING
Symbol
Min
Max
Unit
Cycle Time
Parameter
tTHTH
100
—
ns
Notes
Clock High Time
tTHTL
40
—
ns
Clock Low Time
tTLTH
40
—
ns
TMS Setup
tMVTH
10
—
ns
TMS Hold
tTHMX
10
—
ns
TDI Valid to TCK High
tDVTH
10
—
ns
TCK High to TDI Don’t Care
tTHDX
10
—
ns
Capture Setup
tCS
10
—
ns
1
Capture Hold
tCH
10
—
ns
1
TCK Low to TDO Unknown
tTLQX
0
—
ns
TCK Low to TDO Valid
tTLOV
—
20
ns
NOTE:
1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to ensure accurate pad data capture.
AC TEST LOAD
1.5 V
DEVICE
UNDER
TEST
50 Ω
50 Ω
TAP CONTROLLER TIMING DIAGRAM
tTHTH
tTLTH
TEST CLOCK
(TCK)
tTHTL
tTHMX
tMVTH
TEST MODE SELECT
(TMS)
tTHDX
tDVTH
TEST DATA IN
(TDI)
tTLQV
tTLQX
TEST DATA OUT
(TDO)
MCM69L736A•MCM69L818A
14
MOTOROLA FAST SRAM
TEST ACCESS PORT PINS
TCK — TEST CLOCK (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
TMS — TEST MODE SELECT (INPUT)
The TMS input is sampled on the rising edge of TCK. This
is the command input for the TAP controller state machine.
An undriven TMS input will produce the same result as a logic one input level.
TDI — TEST DATA IN (INPUT)
The TDI input is sampled on the rising edge of TCK. This is
the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and
the instruction that is currently loaded in the TAP instruction
register (see Figure 6). An undriven TDI pin will produce the
same result as a logic one input level.
TDO — TEST DATA OUT (OUTPUT)
Output that is active depending on the state of the TAP
state machine (see Figure 6). Output changes in response to
the falling edge of TCK. This is the output side of the serial
registers placed between TDI and TDO.
TRST — TAP RESET
This device does not have a TRST pin. TRST is optional in
IEEE 1149.1. The test–logic reset state is entered while TMS
is held high for five rising edges of TCK. Power on reset circuitry is included internally. This type of reset does not affect
the operation of the system logic. The reset affects test logic
only.
TEST ACCESS PORT REGISTERS
OVERVIEW
The various TAP registers are selected (one at a time) via
the sequences of ones and zeros input to the TMS pin as the
TCK is strobed. Each of the TAP registers are serial shift registers that capture serial input data on the rising edge of TCK
and push serial data out on the subsequent falling edge of
TCK. When a register is selected it is “placed” between the
TDI and TDO pins.
INSTRUCTION REGISTER
The instruction register holds the instructions that are
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are three bits long. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction register is automatically preloaded with the IDCODE instruction at
power–up or whenever the controller is placed in test–logic–
reset state.
BYPASS REGISTER
The bypass register is a single bit register that can be
placed between TDI and TDO. It allows serial test data to be
passed through the RAMs TAP to another device in the scan
chain with as little delay as possible.
MOTOROLA FAST SRAM
BOUNDARY SCAN REGISTER
The boundary scan register is identical in length to the
number of active input and I/O connections on the RAM (not
counting the TAP pins). This also includes a number of place
holder locations (always set to a logic one) reserved for density upgrade address pins. There are a total of 70 bits in the
case of the x36 device and 51 bits in the case of the x18 device. The boundary scan register, under the control of the
TAP controller, is loaded with the contents of the RAM I/O
ring when the controller is in capture–DR state and then is
placed between the TDI and TDO pins when the controller is
moved to shift–DR state. Several TAP instructions can be
used to activate the boundary scan register.
The Bump/Bit Scan Order tables describe which device
bump connects to each boundary scan register location. The
first column defines the bit’s position in the boundary scan
register. The shift register bit nearest TDO (i.e., first to be
shifted out) is defined as bit 1. The second column is the
name of the input or I/O at the bump and the third column is
the bump number.
IDENTIFICATION (ID) REGISTER
The ID register is a 32–bit register that is loaded with a device and vendor specific 32–bit code when the controller is
put in capture–DR state with the IDCODE command loaded
in the instruction register. The code is loaded from a 32–bit
on–chip ROM. It describes various attributes of the RAM as
indicated below. The register is then placed between the TDI
and TDO pins when the controller is moved into shift–DR
state. Bit 0 in the register is the LSB and the first to reach
TDO when shifting begins.
ID Register Presence Indicator
Bit No.
0
Value
1
Motorola JEDEC ID Code (Compressed Format, per
IEEE Standard 1149.1 – 1990)
Bit No.
11
10
9
8
7
6
5
4
3
2
1
Value
0
0
0
0
0
0
0
1
1
1
0
Reserved For Future Use
Bit No.
17
16
15
14
13
12
Value
x
x
x
x
x
x
Configuration
Bit No.
22
21
20
19
18
128K x 36
Value
0
0
1
0
0
256K x 18
Value
0
0
0
1
1
Configuration
Bit No.
27
26
25
24
23
128K x 36
Value
0
0
1
0
1
256K x 18
Value
0
0
1
1
0
Device Width
Device Depth
Revision Number
Bit No.
31
30
29
28
Value
x
x
x
x
Figure 5. ID Register Bit Meanings
MCM69L736A•MCM69L818A
15
MCM69L736A Bump/Bit Scan Order
MCM69L818A Bump/Bit Scan Order
Bit
No.
Signal
Name
Bump
ID
Bit
No.
Signal
Name
Bump
ID
Bit
No.
Signal
Name
Bump
ID
Bit
No.
Signal
Name
Bump
ID
1
M2
5R
36
SA
3B
1
M2
5R
36
SBb
3G
2
SA
4P
37
NC
2B
2
SA
6T
37
ZQ
4D
3
SA
4T
38
SA
3A
3
SA
4P
38
SS
4E
4
SA
6R
39
SA
3C
4
SA
6R
39
NC
4G
5
SA
5T
40
SA
2C
5
SA
5T
40
NC
4H
6
ZZ
7T
41
SA
2A
6
ZZ
7T
41
SW
4M
7
DQa
6P
42
DQc
2D
7
DQa
7P
42
DQb
2K
8
DQa
7P
43
DQc
1D
8
DQa
6N
43
DQb
1L
9
DQa
6N
44
DQc
2E
9
DQa
6L
44
DQb
2M
10
DQa
7N
45
DQc
1E
10
DQa
7K
45
DQb
1N
11
DQa
6M
46
DQc
2F
11
SBa
5L
46
DQb
2P
12
DQa
6L
47
DQc
2G
12
CK
4L
47
SA
3T
13
DQa
7L
48
DQc
1G
13
CK
4K
48
SA
2R
14
DQa
6K
49
DQc
2H
14
G
4F
49
SA
4N
15
DQa
7K
50
DQc
1H
15
DQa
6H
50
SA
2T
16
SBa
5L
51
SBc
3G
16
DQa
7G
51
M1
3R
17
CK
4L
52
ZQ
4D
17
DQa
6F
18
CK
4K
53
SS
4E
18
DQa
7E
19
G
4F
54
NC
4G
19
DQa
6D
20
SBb
5G
55
NC
4H
20
SA
6A
21
DQb
7H
56
SW
4M
21
SA
6C
22
DQb
6H
57
SBd
3L
22
SA
5C
23
DQb
7G
58
DQd
1K
23
SA
5A
24
DQb
6G
59
DQd
2K
24
NC
6B
25
DQb
6F
60
DQd
1L
25
SA
5B
26
DQb
7E
61
DQd
2L
26
SA
3B
27
DQb
6E
62
DQd
2M
27
NC
2B
28
DQb
7D
63
DQd
1N
28
SA
3A
29
DQb
6D
64
DQd
2N
29
SA
3C
30
SA
6A
65
DQd
1P
30
SA
2C
31
SA
6C
66
DQd
2P
31
SA
2A
32
SA
5C
67
SA
3T
32
DQb
1D
33
SA
5A
68
SA
2R
33
DQb
2E
34
NC
6B
69
SA
4N
34
DQb
2G
35
SA
5B
70
M1
3R
35
DQb
1H
NOTES:
1. The NC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a “place holder” bit that is forced
to logic one. These pads are reserved for use as address inputs on higher density RAMs that follow this pad out and scan order standard.
2. CK and CK, are sampled individually. CK is not simply a forced complement of the CK input. In scan mode these differential inputs are referenced to Vref, not each other.
3. ZQ, M1, and M2 are not ordinary inputs and may not respond to standard I/O logic levels. ZQ, M1, and M2 must be driven to within 100 mV
of a VDD or VSS supply rail to ensure consistent results.
4. ZZ must remain at VIL during boundary scan to ensure consistent results.
MCM69L736A•MCM69L818A
16
MOTOROLA FAST SRAM
TAP CONTROLLER INSTRUCTION SET
OVERVIEW
There are two classes of instructions defined in IEEE Standard 1149.1–1990, the standard (public) instructions and device specific (private) instructions. Some public instructions
are mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1194.1 compliant because
some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all
input and I/O pads, but cannot be used to load address, data,
or control signals into the RAM or to preload the I/O buffers.
In other words, the device will not perform IEEE 1149.1
EXTEST, INTEST, or the preload portion of the SAMPLE/
PRELOAD command.
When the TAP controller is placed in capture–IR state, the
two least significant bits of the instruction register are loaded
with 01. When the controller is moved to the shift–IR state,
the instruction register is placed between TDI and TDO. In
this state, the desired instruction is serially loaded through
the TDI input (while the previous contents are shifted out at
TDO). For all instructions, the TAP executes newly loaded
instructions only when the controller is moved to update–IR
state. The TAP instruction sets for this device are listed in the
following tables.
STANDARD (PUBLIC) INSTRUCTIONS
BYPASS
The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and
TDO. This occurs when the TAP controller is moved to the
shift–DR state. This allows the board level scan path to be
shortened to facilitate testing of other devices in the scan
path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory public
instruction. When the SAMPLE/PRELOAD instruction is
loaded in the instruction register, moving the TAP controller
into the capture–DR state loads the data in the RAM’s input
and I/O buffers into the boundary scan register. Because the
RAM clock(s) are independent from the TAP clock (TCK) it is
possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable
inputs will not harm the device, repeatable results cannot be
MOTOROLA FAST SRAM
expected. RAM input signals must be stabilized for long
enough to meet the TAP’s input data capture set–up plus
hold time (tCS plus tCH). The RAM’s clock inputs need not be
paused for any other TAP operation except capturing the I/O
ring contents into the boundary scan register.
Moving the controller to shift–DR state then places the
boundary scan register between the TDI and TDO pins.
Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the
update–DR state with the SAMPLE/PRELOAD instruction
loaded in the instruction register has the same effect as the
pause–DR command. This functionality is not IEEE 1149.1
compliant.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It
is to be executed whenever the instruction register, whatever
length it may be in the device, is loaded with all logic zeros.
EXTEST is not implemented in this device. Therefore, this
device is not IEEE 1149.1 compliant. Nevertheless, this RAM
TAP does respond to an all zeros instruction, as follows. With
the EXTEST (000) instruction loaded in the instruction
register, the RAM responds just as it does in response to the
SAMPLE/PRELOAD instruction described above, except the
RAM outputs are forced to High–Z any time the instruction is
loaded.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded
into the ID register when the controller is in capture–DR
mode and places the ID register between the TDI and TDO
pins in shift–DR mode. The IDCODE instruction is the default
instruction loaded in at power up and any time the controller
is placed in the test–logic–reset state.
DEVICE SPECIFIC (PUBLIC) INSTRUCTION
SAMPLE–Z
If the SAMPLE–Z instruction is loaded in the instruction
register, all RAM outputs are forced to an inactive drive state
(High–Z) and the boundary scan register is connected between TDI and TDO when the TAP controller is moved to the
shift–DR state.
DEVICE SPECIFIC (PRIVATE) INSTRUCTION
NO OP
Do not use these instructions; they are reserved for future
use.
MCM69L736A•MCM69L818A
17
STANDARD (PUBLIC) INSTRUCTION CODES
Instruction
Code*
EXTEST
000
IDCODE
001**
Description
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
RAM outputs to High–Z state. NOT IEEE 1149.1 COMPLIANT.
Preloads ID register and places it between TDI and TDO. Does not affect RAM operation.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not
affect RAM operation. Does not implement IEEE 1149.1 PRELOAD function. NOT IEEE 1149.1
COMPLIANT.
BYPASS
111
Places bypass register between TDI and TDO. Does not affect RAM operation.
SAMPLE–Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
RAM output drivers to High–Z state.
* Instruction codes expressed in binary; MSB on left, LSB on right.
** Default instruction automatically loaded at power–up and in test–logic–reset state.
STANDARD (PRIVATE) INSTRUCTION CODES
Instruction
Code*
Description
NO OP
011
Do not use these instructions; they are reserved for future use.
NO OP
101
Do not use these instructions; they are reserved for future use.
NO OP
110
Do not use these instructions; they are reserved for future use.
* Instruction codes expressed in binary; MSB on left, LSB on right.
1
TEST–LOGIC
RESET
0
0
RUN–TEST/
IDLE
1
SELECT
DR–SCAN
SELECT
IR–SCAN
1
0
1
1
0
1
CAPTURE–DR
CAPTURE–IR
0
0
SHIFT–DR
SHIFT–IR
0
0
1
1
1
1
EXIT1–DR
EXIT1–IR
0
0
PAUSE–DR
PAUSE–IR
0
1
0
1
EXIT2–DR
0
EXIT2–IR
1
1
UPDATE–DR
1
0
0
UPDATE–IR
1
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 6. TAP Controller State Diagram
MCM69L736A•MCM69L818A
18
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number)
MCM
69L736A
69L818A XX
X
X
Motorola Memory Prefix
R = Tape and Reel, Blank = Tray
Part Number
Speed (7.5 = 7.5 ns, 8.5 = 8.5 ns,
9.5 = 9.5 ns, 10.5 = 10.5 ns)
Package (ZP = PBGA)
Full Part Numbers — MCM69L736AZP7.5
MCM69L818AZP7.5
MCM69L736AZP7.5R
MCM69L818AZP7.5R
MOTOROLA FAST SRAM
MCM69L736AZP8.5
MCM69L818AZP8.5
MCM69L736AZP8.5R
MCM69L818AZP8.5R
MCM69L736AZP9.5
MCM69L818AZP9.5
MCM69L736AZP9.5R
MCM69L818AZP9.5R
MCM69L736AZP10.5
MCM69L818AZP10.5
MCM69L736AZP10.5R
MCM69L818AZP10.5R
MCM69L736A•MCM69L818A
19
PACKAGE DIMENSIONS
ZP PACKAGE
7 X 17 BUMP PBGA
CASE 999–01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.20 (0.008)
4X
A
–W–
PIN 1A
IDENTIFIER
7 6 5 4 3 2 1
B
–L–
P
S
16X
N
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
G
6X
DIM
A
B
C
D
E
F
G
K
N
P
R
S
119X
G
INCHES
MIN
MAX
0.551 BSC
0.866 BSC
–––
0.094
0.024
0.035
0.020
0.028
0.051
0.067
0.050 BSC
0.031
0.039
0.469
0.476
0.764
0.772
0.300 BSC
0.800 BSC
D
R
0.30 (0.012)
S
T W
BOTTOM VIEW
0.10 (0.004)
S
T
TOP VIEW
MILLIMETERS
MIN
MAX
14.00 BSC
22.00 BSC
–––
2.40
0.60
0.90
0.50
0.70
1.30
1.70
1.27 BSC
0.80
1.00
11.90
12.10
19.40
19.60
7.62 BSC
20.32 BSC
S
L
S
0.25 (0.010) T
F
0.35 (0.014) T
0.15 (0.006) T
C
–T–
K
E
SIDE VIEW
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
Mfax is a trademark of Motorola, Inc.
How to reach us:
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MCM69L736A•MCM69L818A ◊
20
MOTOROLAMCM69L736A/D
FAST SRAM
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