ON MC14077BDG Cmos ssi quad exclusive â orâ and â norâ gate Datasheet

MC14070B, MC14077B
CMOS SSI
Quad Exclusive “OR” and “NOR” Gates
The MC14070B quad exclusive OR gate and the MC14077B quad
exclusive NOR gate are constructed with MOS P−channel and
N−channel enhancement mode devices in a single monolithic
structure. These complementary MOS logic gates find primary use
where low power dissipation and/or high noise immunity is desired.
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MARKING
DIAGRAMS
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
•
•
•
•
14
PDIP−14
P SUFFIX
CASE 646
Schottky TTL Load Over the Rated Temperature Range
Double Diode Protection on All Inputs
MC14070B − Replacement for CD4030B and CD4070B Types
MC14077B − Replacement for CD4077B Type
These Devices are Pb−Free and are RoHS Compliant
MC140xxBCP
AWLYYWWG
1
14
SOIC−14
D SUFFIX
CASE 751A
140xxBG
AWLYWW
1
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Value
Unit
−0.5 to +18.0
V
−0.5 to VDD + 0.5
V
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
Symbol
VDD
Vin, Vout
Iin, Iout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
14
SOEIAJ−14
F SUFFIX
CASE 965
MC140xxB
ALYWG
1
xx
A
WL, L
YY, Y
WW, W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 8
1
Publication Order Number:
MC14070B/D
MC14070B, MC14077B
PIN ASSIGNMENT
IN 1A
1
14
VDD
IN 2A
2
13
IN 2D
OUTA
3
12
IN 1D
OUTB
4
11
OUTD
IN 1B
5
10
OUTC
IN 2B
6
9
IN 2C
VSS
7
8
IN 1C
MC14070B
QUAD Exclusive OR
Gate
MC14077B
QUAD Exclusive NOR
Gate
1
1
3
3
2
5
2
5
4
4
6
8
6
8
10
9
12
10
9
12
11
11
13
13
VDD = PIN 14
VSS = PIN 7
(BOTH DEVICES)
20 ns
VDD
Vin
VDD
90%
50%
10%
Vin
IDD
20 ns
VSS
1/f
50% DUTY CYCLE
*
CL
*Inverted output on MC14077B only.
Figure 1. Power Dissipation Test Circuit and Waveform
PULSE
GENERATOR
INPUT
*
#
VSS
20 ns
20 ns
VDD
tPHL
CL
OUTPUT
tPLH
90%
50%
10%
tTHL
*Inverted output on MC14077B only.
#Connect unused input to VDD for MC14070B, to VSS for MC14077B.
Figure 2. Switching Time Test Circuit and Waveforms
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2
VDD
90%
50%
10%
tTLH
VSS
VOH
VOL
MC14070B, MC14077B
ORDERING INFORMATION
Package
Shipping†
MC14070BCPG
PDIP−14
(Pb−Free)
500 Units / Rail
MC14070BDG
SOIC−14
(Pb−Free)
55 Units / Rail
MC14070BDR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
SOEIAJ−14
(Pb−Free)
2000 / Tape & Reel
PDIP−14
(Pb−Free)
500 Units / Rail
SOIC−14
(Pb−Free)
55 Units / Rail
SOIC−14
(Pb−Free)
2500 / Tape & Reel
SOEIAJ−14
(Pb−Free)
2000 / Tape & Reel
Device
MC14070BFELG
MC14077BCPG
MC14077BDG
MC14077BDR2G
MC14077BFELG
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
MC14070B, MC14077B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
− 55_C
Characteristic
“0” Level
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ
(Note 2)
Max
Min
Max
Unit
VOL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
“0” Level
VIL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
−
−
−
−
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
– 1.7
– 0.36
– 0.9
– 2.4
−
−
−
−
IOL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current
Iin
15
−
±0.1
−
± 0.00001
±0.1
−
±1.0
mAdc
Input Capacitance
(Vin = 0)
Cin
−
−
—
−
5.0
7.5
−
−
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
−
−
−
0.25
0.5
1.0
−
−
−
0.0005
0.0010
0.0015
0.25
0.5
1.0
−
−
−
7.5
15
30
mAdc
IT
5.0
10
15
Output Voltage
Vin = VDD or 0
Symbol
Vin = 0 or VDD
Input Voltage
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
Source
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Sink
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
VIH
IOH
Output Rise and Fall Times (Note 3)
(CL = 50 pF)
tTLH, tTHL = (1.35 ns/pF) CL + 33 ns
tTLH, tTHL = (0.60 ns/pF) CL + 20 ns
tTLH, tTHL = (0.40 ns/pF) CL + 20 ns
tTLH,
tTHL
Propagation Delay Times (Note 3)
(CL = 50 pF)
tPLH, tPHL = (0.90 ns/pF) CL + 130 ns
tPLH, tPHL = (0.36 ns/pF) CL + 57 ns
tPLH, tPHL = (0.26 ns/pF) CL + 37 ns
tPLH,
tPHL
Vdc
Vdc
mAdc
IT = (0.3 mA/kHz) f + IDD
IT = (0.6 mA/kHz) f + IDD
IT = (0.9 mA/kHz) f + IDD
mAdc
ns
5.0
10
15
−
−
−
−
−
−
−
−
−
100
50
40
200
100
80
−
−
−
−
−
−
ns
5.0
10
15
−
−
−
−
−
−
−
−
−
175
75
55
350
150
110
−
−
−
−
−
−
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in mH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
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4
MC14070B, MC14077B
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
A
F
L
N
C
−T−
SEATING
PLANE
H
G
D 14 PL
J
K
0.13 (0.005)
M
M
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5
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
−−−
10 _
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
−−−
10 _
0.38
1.01
MC14070B, MC14077B
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
D
A
B
14
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
b
0.25
M
C A
S
B
S
e
DETAIL A
h
A
X 45 _
M
A1
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
MC14070B, MC14077B
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
8
Q1
E HE
M_
L
7
1
DETAIL P
Z
D
VIEW P
A
e
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--1.42
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.004
0.008
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.056
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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7
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MC14070B/D
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