ON NB100LVEP224 2.5v/3.3v 1:24 differential ecl/pecl clock driver with clock select and output enable Datasheet

NB100LVEP224
2.5V/3.3V 1:24 Differential
ECL/PECL Clock Driver with
Clock Select and Output
Enable
The NB100LVEP224 is a low skew 1-to-24 differential clock
driver, designed with clock distribution in mind, accepting two clock
sources into an input multiplexer. The part is designed for use in low
voltage applications which require a large number of outputs to drive
precisely aligned low skew signals to their destination. The two clock
inputs are differential ECL/PECL and they are selected by the
CLK_SEL pin. To avoid generation of a runt clock pulse when the
device is enabled/disabled, the Output Enable (OE) is synchronous
ensuring the outputs will only be enabled/disabled when they are
already in LOW state (See Figure 4).
The NB100LVEP224 guarantees low output-to-output skew. The
optimal design, layout, and processing minimize skew within a device
and from lot to lot. In any differential output, the same bias and
termination scheme is required. Unused output pairs should be left
unterminated (open) to “reduce power and switching noise as much as
possible.” Any unused single line of a differential pair should be
terminated the same as the used line to maintain balanced loads on the
differential driver outputs. The wide VIHCMR specification allows
both pair of CLOCK inputs to accept LVDS levels.
The NB100LVEP224, as with most other ECL devices, can be
operated from a positive VCC supply in LVPECL mode. This allows
the LVEP224 to be used for high performance clock distribution in
+3.3 V or +2.5 V systems. Single-ended CLK input operation is
limited to a VCC ≥ 3.0 V in LVPECL mode, or VEE ≤ -3.0 V in NECL
mode. In a PECL environment, series or Thevenin line terminations
are typically used as they require no additional power supplies. For
more information on PECL terminations, designers should refer to
Application Note AND8020/D.
•
•
•
•
•
•
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MARKING
DIAGRAM*
64
NB100
LVEP224
AWLYYWW
1
64-LEAD LQFP
CASE 848G
THERMALLY ENHANCED
FA SUFFIX
A
WL
YY
WW
64
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
Device
NB100LVEP224FA
Package
Shipping
LQFP-64
160 Units/Tray
NB100LVEP224FAR2 LQFP-64 1500/Tape & Reel
20 ps Typical Output-to-Output Skew
75 ps Typical Device-to- Device Skew
Maximum Frequency > 1 GHz
650 ps Typical Propagation Delay
LVPECL Mode Operating Range:
VCC = 2.375 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = -2.375 V to -3.8 V
Internal Input Pulldown Resistors
•
• Q Output will Default Low with Inputs Open or at VEE
• Thermally Enhanced 64-Lead LQFP
• CLOCK Inputs are LVDS-Compatible; Requires External 100 LVDS Termination Resistor
 Semiconductor Components Industries, LLC, 2003
June, 2003 - Rev. 4
1
Publication Order Number:
NB100LVEP224/D
Q8
Q8
Q9
Q9
Q10
Q10
Q11
Q11
Q12
Q12
Q13
Q13
Q14
Q14
VEE
VCCO
VEE
NB100LVEP224
48
49
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
VCCO
Q7
50
31
Q15
Q7
51
30
Q15
Q6
52
29
Q16
Q6
53
28
Q16
Q5
54
27
Q17
Q5
55
26
Q17
Q4
56
25
Q18
Q4
57
24
Q18
Q3
58
23
Q19
Q3
59
22
Q19
Q2
60
21
Q20
Q2
61
20
Q20
Q1
62
19
Q21
Q1
63
18
Q21
VCCO
64
17
VCCO
10
11
12
13
14
15
16
Q23
Q22
Q22
VCCO
9
Q23
8
OE
VCC
7
VEE
Q0
6
CLK1
Q0
5
CLK1
4
CLK_SEL
3
CLK0
2
CLK0
1
VCCO
NB100LVEP224
All VCC, VCCO, and VEE pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally
conductive exposed pad on package bottom (see package case drawing) must be attached to a heat-sinking conduit, capable of transferring 1.2 Watts. This exposed pad is electrically connected to VEE internally.
Figure 1. 64-Lead LQFP Pinout (Top View)
PIN DESCRIPTION
PIN
FUNCTION
CLK0*, CLK0**
CLK1*, CLK1**
CLK_SEL*
OE*
Q0-Q23, Q0-Q23
VCC, VCCO
VEE***
ECL Differential Input Clock
ECL Differential Input Clock
ECL Input CLK Select
ECL Output Enable
ECL Differential Outputs
Positive Supply
Negative Supply
FUNCTION TABLE
OE (1)
CLK_SEL
Q0-Q23
Q0-Q23
L
L
H
H
L
H
L
H
CLK0
CLK1
L
L
CLK0
CLK1
H
H
1. The OE (Output Enable) signal is synchronized with the
falling edge of the LVPECL_CLK signal.
* Pins will default LOW when left open.
** Pins will default HIGH when left open.
*** The thermally conductive exposed pad on the bottom of the
package is electrically connected to VEE internally.
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2
NB100LVEP224
CLK_SEL
CLK0
0
24
CLK0
24
CLK1
Q0-Q23
Q0-Q23
1
CLK1
VCC
VEE
Q
D
OE
Figure 2. Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
37.5 k
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 150 V
> 2 kV
Moisture Sensitivity (Note 1)
Flammability Rating
Level 3
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
654 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
-6
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6 to 0
-6 to 0
V
TA
Operating Temperature Range
0 to +85
°C
Tstg
Storage Temperature Range
-65 to +150
°C
JA
Thermal Resistance (Junction-to-Ambient)
(See Application Information)
0 LFPM
500 LFPM
64 LQFP
64 LQFP
35.6
30
°C/W
°C/W
JC
Thermal Resistance (Junction-to-Case)
(See Application Information)
0 LFPM
500 LFPM
64 LQFP
64 LQFP
3.2
6.4
°C/W
°C/W
Tsol
Wave Solder
265
°C
< 2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
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3
VI ≤ VCC
VI ≥ VEE
NB100LVEP224
LVPECL DC CHARACTERISTICS VCC = 2.5 V; VEE = 0 V (Note 3)
-40 °C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
130
160
195
135
165
200
140
165
205
mA
VOH
Output HIGH Voltage (Note 8)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VOL
Output LOW Voltage (Note 8)
555
680
900
555
680
900
555
680
900
mV
VIH
Input HIGH Voltage (Single-Ended)
(Note 9)
1335
1620
1335
1620
1275
1620
mV
VIL
Input LOW Voltage (Single-Ended)
(Note 9)
555
900
555
900
555
900
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 10)
CLK/CLK
1.2
2.5
1.2
2.5
1.2
2.5
V
150
A
IIH
Input HIGH Current
IIL
Input LOW Current
150
CLK
CLK
0.5
-150
150
0.5
-150
A
0.5
-150
NOTE:
3.
4.
5.
6.
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is
maintained.
Input and output parameters vary 1:1 with VCC. VEE can vary + 0.125 V to -1.3 V.
All outputs loaded with 50 to VCC - 2.0 V.
Do not use VBB at VCC < 3.0 V.
VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0 V (Note 7)
-40 °C
Symbol
Min
Characteristic
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
140
165
195
145
175
205
145
175
210
mA
VOH
Output HIGH Voltage (Note 8)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 8)
1355
1480
1700
1355
1480
1700
1355
1480
1700
mV
VIH
Input HIGH Voltage (Single-Ended)
(Note 9)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single-Ended)
(Note 9)
1355
1700
1355
1700
1355
1700
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 10) (Figure
5)
1.2
3.3
1.2
3.3
1.2
3.3
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
150
CLK
CLK
0.5
-150
150
0.5
-150
NOTE:
0.5
-150
A
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to -0.5 V.
8. All outputs loaded with 50 to VCC - 2.0 V.
9. Single ended input operation is limited VCC ≥ 3.0 V in LVPECL mode.
10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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NB100LVEP224
NECL DC CHARACTERISTICS VCC = 0 V, VEE = -2.375 V to -3.8 V (Note 11)
-40 °C
Symbol
Characteristic
VEE = -2.5 V
VEE = -3.3 V
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
130
140
160
165
195
195
135
145
165
175
200
205
140
145
165
175
205
210
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 12)
-1 145
-1020
-895
-1 145
-1020
-895
-1 145
-1020
-895
mV
VOL
Output LOW Voltage (Note 12)
-1945
-1820
-1600
-1945
-1820
-1600
-1945
-1820
-1600
mV
VIH
Input HIGH Voltage (Single-Ended)
(Note 13)
-1 165
-880
-1 165
-880
-1 165
-880
mV
VIL
Input LOW Voltage (Single-Ended)
(Note 13)
-1945
-1600
-1945
-1600
-1945
-1600
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
(Figure 5)
0.0
V
IIH
Input HIGH Current
150
A
IIL
Input LOW Current
VEE + 1.2
0.0
VEE + 1.2
0.0
150
CLK
CLK
VEE + 1.2
150
0.5
-150
0.5
-150
A
0.5
-150
NOTE:
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
11. Input and output parameters vary 1:1 with VCC.
12. All outputs loaded with 50 to VCC - 2.0 V.
13. Single ended input operation is limited VEE ≤ -3.0 V in NECL mode.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VCC = 2.375 V to 3.8 V; VEE = 0 V (Note 15)
-40 C
Symbol
VOpp
Characteristic
Differential Output Voltage
(Figure 3)
fout < 50 MHz
fout < 0.8 GHz
fout < 1.0 GHz
25C
Min
Typ
Max
600
600
600
750
750
700
500
600
600
700
700
800
85C
Min
Typ
Max
600
600
525
725
725
650
550
650
650
800
750
900
Min
Typ
Max
575
550
400
700
650
525
650
750
750
850
1000
1150
ps
ps
Unit
mV
mV
mV
tPLH
tPHL
Propagation Delay (Differential)
tskew
Within-Device Skew (Note 16)
Device-to-Device Skew (Note 17)
20
50
40
300
20
50
40
300
35
100
60
300
ps
ps
tJITTER
Random Clock Jitter (Figure 3) (RMS)
1
5
1
5
1
5
ps
VPP
Input Swing (Differential) (Note 19) (Figure 5)
200
800
1200
800
1200
800
1200
mV
tS
OE Set Up Time (Note 18)
200
200
200
ps
tH
OE Hold Time
200
200
200
ps
tr/tf
Output Rise/Fall Time
(20%-80%)
100
CLKx-Qx
CLK_SELx-Qx
200
300
200
100
200
300
200
150
250
350
ps
15. Measured with PECL 750 mV source, 50% duty cycle clock source. All outputs loaded with 50 to VCC - 2 V.
16. Skew is measured between outputs under identical transitions and conditions on any one device.
17. Device-to-Device skew for identical transitions at identical VCC levels.
18. OE Set Up Time is defined with respect to the falling edge of the clock. OE High-to-Low transition ensures outputs remain disabled during
the next clock cycle. OE Low-to-High transition enables normal operation of the next input clock.
19. VPP is the differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew.
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5
NB100LVEP224
10
9.0
800
8.0
700
Q AMP (mV)
7.0
6.0
600
500
5.0
2.5 V
3.3 V
4.0
3.0
400
2.0
RMS JITTER (ps)
300
RMS JITTER (ps)
OUTPUT AMPLITUDE (mV)
900
1.0
0
200
0.5 0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4 1.5
INPUT FREQUENCY (GHz)
Figure 3. Output Amplitude (VOPP) versus Input Frequency and Random Clock Jitter (tJITTER)
CLK
CLK
OE
Q
Q
Figure 4. Output Enable (OE) Timing Diagram
VCC(LVPECL)
VIH(DIFF)
VPP
VIHCMR
VIL(DIFF)
VEE
Figure 5. LVPECL Differential Input Levels
Resource Reference of Application Notes
AN1405
-
ECL Clock Distribution Techniques
AND8002
-
Marking and Date Codes
AND8009
-
ECLinPS Plus Spice I/O Model Kit
AND8020
-
Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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NB100LVEP224
APPLICATIONS INFORMATION
Using the thermally enhanced package of the
NB100LVEP224
The NB100LVEP224 uses a thermally enhanced 64-lead
LQFP package. The package is molded so that a portion of
the leadframe is exposed at the surface of the package
bottom side. This exposed metal pad will provide the low
thermal impedance that supports the power consumption of
the NB100LVEP224 high-speed bipolar integrated circuit
and will ease the power management task for the system
design. In multilayer board designs, a thermal land pattern
on the printed circuit board and thermal vias are
recommended to maximize both the removal of heat from
the package and electrical performance of the
NB100LVEP224. The size of the land pattern can be larger,
smaller, or even take on a different shape than the exposed
pad on the package. However, the solderable area should be
at least the same size and shape as the exposed pad on the
package. Direct soldering of the exposed pad to the thermal
land will provide an efficient thermal conduit. The thermal
vias will connect the exposed pad of the package to internal
copper planes of the board. The number of vias, spacing, via
diameters and land pattern design depend on the application
and the amount of heat to be removed from the package.
Maximum thermal and electrical performance is achieved
when an array of vias is incorporated in the land pattern.
The recommended thermal land design for
NB100LVEP224 applications on multi-layer boards
comprises a 4 X 4 thermal via array using a 1.2 mm pitch as
shown in Figure 6 providing an efficient heat removal path.
supply enough solder paste to fill those vias and not starve
the solder joints. The attachment process for the exposed pad
package is equivalent to standard surface mount packages.
Figure 7, “Recommended solder mask openings”, shows a
recommended solder mask opening with respect to a 4 X 4
thermal via array. Because a large solder mask opening may
result in a poor rework release, the opening should be
subdivided as shown in Figure 7. For the nominal package
standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should
be considered.
All Units mm
0.2
1.0
1.0
4.6
0.2
4.6
Thermal Via Array (4 X 4)
1.2 mm Pitch
0.3 mm Diameter
Exposed Pad
Land Pattern
Figure 7. Recommended Solder Mask Openings
All Units mm
Proper thermal management is critical for reliable system
operation. This is especially true for high-fanout and high
output drive capability products.
For thermal system analysis and junction temperature
calculation the thermal resistance parameters of the package
is provided:
4.6
Table 1. Thermal Resistance *
4.6
Thermal Via Array (4 X 4)
1.2 mm Pitch
0.3 mm Diameter
LFPM
JA C/W
JC C/W
0
35.6
3.2
100
32.8
4.9
500
30.0
6.4
* Junction to ambient and Junction to board, four-conductor
layer test board (2S2P) per JESD 51-8
These recommendations are to be used as a guideline,
only. It is therefore recommended that users employ
sufficient thermal modeling analysis to assist in applying the
general recommendations to their particular application to
assure adequate thermal performance. The exposed pad of
the NB100LVEP224 package is electrically shorted to the
substrate of the integrated circuit and VEE. The thermal land
should be electrically connected to VEE.
Exposed Pad
Land Pattern
Figure 6. Recommended Thermal Land Pattern
The via diameter should be approximately 0.3 mm with
1 oz. copper via barrel plating. Solder wicking inside the via
may result in voiding during the solder process and must be
avoided. If the copper plating does not plug the vias, stencil
print solder paste onto the printed circuit pad. This will
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NB100LVEP224
PACKAGE DIMENSIONS
LQFP
FA SUFFIX
64-LEAD PACKAGE
CASE 848G-02
ISSUE A
4 PL
M
M/2
-Z-
0.20 (0.008) T X−Y Z
AJ AJ
64
49
48
1
ÉÉÉÉ
ÇÇÇÇ
ÉÉÉÉ
ÇÇÇÇ
ÉÉÉÉ
PLATING
-X-
AA
-Y-
L
B
J
AB
B/2
L/2
D
REF
16
33
0.08 (0.003)
M
Y T−U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MM.
3. DATUM PLANE E" IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING PLANE.
4. DATUM X", Y" AND Z" TO BE DETERMINED AT
DATUM PLANE DATUM E".
5. DIMENSIONS M AND L TO BE DETERMINED AT
SEATING PLANE DATUM T".
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
BASE
DETERMINED AT DATUM PLAND E".
METAL 7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED THE MAXIMUM D DIMENSION
BY MORE THAN 0.08 (0.003). DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR THE
FOOT. MINIMUM SPACE BETWEEN PROTRUSION
AND ADJACENT LEAD OR PROTRUSION 0.07
(0.003).
8. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
Z
DIM
A
B
C
D
F
G
H
J
K
L
M
N
P
R
S
V
W
AA
AB
AC
AD
AE
AF
32
17
DETAIL AJ-AJ
A/2
0.20 (0.008) E X−Y Z
A
DETAIL AH
-E-T-
AG
AG
G/2
SEATING
PLANE
G
0.08 (0.003) T
4 PL
60 PL
D
64 PL
0.08 (0.003)
M
T X−Y
V
Z
0.05 (0.002)
R
S
AC
AE
EXPOSED PAD
17
AD
32
S
C
33
16
W
N
K
P
F
AF
H
DETAIL AH
1
48
64
49
VIEW AG-AG
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8
0.25
GAGE
PLANE
MILLIMETERS
MIN
MAX
10.00 BSC
10.00 BSC
1.35
1.45
0.17
0.27
0.45
0.75
0.50 BSC
1.00 REF
0.09
0.20
0.05
0.15
12.00 BSC
12.00 BSC
0.20
−−−
0
7
0
−−−
−−−
1.60
11 13 11 13 0.17
0.23
0.09
0.16
0.08
−−−
0.08
−−−
4.50
4.78
4.50
4.78
INCHES
MIN
MAX
0.394 BSC
0.394 BSC
0.053
0.057
0.007
0.011
0.018
0.030
0.020 BSC
0.039 BSC
0.004
0.008
0.002
0.006
0.472 BSC
0.472 BSC
0.008
−−−
0
7
0
−−−
−−−
0.063
11 13 11 13 0.007
0.009
0.004
0.006
0.003
−−−
0.003
−−−
0.180
0.188
0.180
0.188
NB100LVEP224
Notes
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NB100LVEP224
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: [email protected]
JAPAN: ON Semiconductor, Japan Customer Focus Center
2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051
Phone: 81-3-5773-3850
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
N. American Technical Support: 800-282-9855 Toll Free USA/Canada
http://onsemi.com
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