Renesas ISL5761/2IAZ 10-bit, 3.3v, 130/210msps, high speed d/a converter Datasheet

DATASHEET
ISL5761
FN6009
Rev 4.00
Sep 15, 2015
10-bit, +3.3V, 130/210+MSPS, High Speed D/A Converter
The ISL5761 is a 10-bit, 130/210+MSPS (Mega Samples
Per Second), CMOS, high speed, low power, D/A (digital to
analog) converter, designed specifically for use in high
performance communication systems such as base
transceiver stations utilizing 2.5G or 3G cellular protocols.
This device complements the ISL5x61 family of high speed
converters, which include 10, 12, and 14-bit devices.
Ordering Information
Features
• Speed Grades . . . . . . . . . . . . . . . . 130M and 210+MSPS
• Low Power . . . . . 103mW with 20mA Output at 130MSPS
• Adjustable Full Scale Output Current . . . . . 2mA to 20mA
• +3.3V Power Supply
• 3V LVCMOS Compatible Inputs
• Excellent Spurious Free Dynamic Range
(71dBc to Nyquist, f S = 130MSPS, fOUT = 10MHz)
PART
NUMBER
(See Note)
TEMP.
RANGE
(oC)
ISL5761IBZ
(No longer
available,
recommended
replacement:
ISL5761IAZ)
-40 to 85
ISL5761IAZ
-40 to 85
28 Ld TSSOP M28.173 130MHz
Applications
ISL5761/2IBZ
(No longer
available,
recommended
replacement:
ISL5761/2IAZ)
-40 to 85
28 Ld SOIC
• Cellular Infrastructure - Single or Multi-Carrier: IS-136, IS95, GSM, EDGE, CDMA2000, WCDMA, TDS-CDMA
ISL5761/2IAZ
-40 to 85
28 Ld TSSOP M28.173 210MHz
• Wireless Communication Systems
ISL5761EVAL1
25
SOIC Evaluation Platform 210MHz
• High Resolution Imaging Systems
PACKAGE
(RoHS
Compliant)
28 Ld SOIC
PKG.
DWG. #
M28.3
CLOCK
SPEED
130MHz
• UMTS Adjacent Channel Power = 65dB at 19.2MHz
• EDGE/GSM SFDR = 83dBc at 11MHz in 20MHz Window
• Pin compatible, 3.3V, Lower Power Replacement For The
AD9750 and HI5760
• Pb-free available
M28.3
210MHz
• BWA Infrastructure
• Medical/Test Instrumentation
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
• Arbitrary Waveform Generators
Pinout
ISL5761
TOP VIEW
D9 (MSB) 1
27 DVDD
D7 3
26 DCOM
D6 4
25 NC
D5 5
24 AVDD
D4 6
23 COMP
D3 7
22 IOUTA
D2 8
21 IOUTB
D1 9
20 ACOM
D0 (LSB) 10
FN6009 Rev 4.00
Sep 15, 2015
28 CLK
D8 2
19 NC
DCOM 11
18 FSADJ
DCOM 12
17 REFIO
DCOM 13
16 REFLO
DCOM 14
15 SLEEP
Page 1 of 14
ISL5761
Typical Applications Circuit
ISL5761
ONE CONNECTION
(25, 19) NC
(15) SLEEP
(16) REFLO
DCOM
ACOM
(17) REFIO
D9
D9 (1)
D8
D8 (2)
D7
D7 (3)
D6
D6 (4)
D5
D5 (5)
D4
D4 (6)
D3
D3 (7)
D2
D2 (8)
D1
D1 (9)
D0
D0 (LSB) (10)
0.1F
(18) FSADJ
RSET
1:1, Z1:Z2
(22) IOUTA
(21) IOUTB
(50)
50
REPRESENTS
ANY 50 LOAD
(23) COMP
CLK (28)
DCOM (26, 11-14)
50
0.1F
(20) ACOM
BEAD
+
10F
10H
1.91k
FERRITE
BEAD
(24) AVDD
DVDD (27)
+
10H
0.1F
0.1F
10F
+3.3V (VDD)
Functional Block Diagram
IOUTA
IOUTB
CASCODE
(LSB) D0
CURRENT
SOURCE
INPUT
LATCH
D1
36
D2
SWITCH
MATRIX
D3
36
5 LSBs
+
31 MSB
SEGMENTS
D4
D5
D6
D7
D8
UPPER
5-BIT
DECODER
(MSB) D9
COMP
CLK
INT/EXT
VOLTAGE
BIAS
GENERATION
REFERENCE
REFLO REFIO
FN6009 Rev 4.00
Sep 15, 2015
FSADJ
SLEEP
Page 2 of 14
ISL5761
Pin Descriptions
PIN NO.
PIN NAME
1-10
D9 (MSB) Through
D0 (LSB)
15
SLEEP
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin
has internal 20A active pulldown current.
16
REFLO
Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference.
17
REFIO
Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is
enabled. Use 0.F cap to ground when internal reference is enabled.
18
FSADJ
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current
= 32 x VFSADJ/RSET.
19, 25
NC
21
IOUTB
The complementary current output of the device. Full scale output current is achieved when all input bits are
set to binary 0.
22
IOUTA
Current output of the device. Full scale output current is achieved when all input bits are set to binary 1.
23
COMP
Connect 0.1F capacitor to ACOM.
24
AVDD
Analog Supply (+3.0V to +3.6V).
20
ACOM
Connect to Analog Ground.
26, 11-14
DCOM
Connect to Digital Ground.
27
DVDD
Digital Supply (+3.0V to +3.6V).
28
CLK
FN6009 Rev 4.00
Sep 15, 2015
DESCRIPTION
Digital Data Bit 9, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).
No Connect. These should be grounded, but can be left disconnected.
Clock Input.
Page 3 of 14
ISL5761
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +3.6V
Analog Supply Voltage AVDD to ACOM. . . . . . . . . . . . . . . . . . +3.6V
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . DVDD + 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Thermal Resistance (Typical, Note 1)
Operating Conditions
JA(oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values
TA = -40oC TO 85oC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM PERFORMANCE
Resolution
10
-
-
Bits
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 7)
-0.5
0.1
+0.5
LSB
Differential Linearity Error, DNL
(Note 7)
-0.5
0.1
+0.5
LSB
Offset Error, IOS
IOUTA (Note 7)
+0.006
% FSR
Offset Drift Coefficient
(Note 7)
-
0.1
-
ppm
FSR/oC
Full Scale Gain Error, FSE
With External Reference (Notes 2, 7)
-3
0.5
+3
% FSR
With Internal Reference (Notes 2, 7)
-3
0.5
+3
% FSR
With External Reference (Note 7)
-
50
-
ppm
FSR/oC
With Internal Reference (Note 7)
-
100
-
ppm
FSR/oC
2
-
20
mA
-1.0
-
1.25
V
Full Scale Gain Drift
-0.006
Full Scale Output Current, IFS
Output Voltage Compliance Range
(Note 3)
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, fCLK
ISL5761/2IA, ISL5761/2IB
210
250
-
MHz
Maximum Clock Rate, fCLK
ISL5761IA, ISL5761IB
130
150
-
MHz
Output Rise Time
Full Scale Step
-
1.5
-
ns
Output Fall Time
Full Scale Step
-
1.5
-
ns
-
10
-
pF
IOUTFS = 20mA
-
50
-
pA/Hz
IOUTFS = 2mA
-
30
-
pA/Hz
fCLK = 210MSPS, fOUT = 80.8MHz, 30MHz Span (Notes 4, 7)
-
72
-
dBc
fCLK = 210MSPS, fOUT = 40.4MHz, 30MHz Span (Notes 4, 7)
-
75
-
dBc
fCLK = 130MSPS, fOUT = 20.2MHz, 20MHz Span (Notes 4, 7)
-
77
-
dBc
Output Capacitance
Output Noise
AC CHARACTERISTICS (Using Figure 13 with RDIFF = 50 and RLOAD= 50, Full Scale Output = -2.5dBm
Spurious Free Dynamic Range,
SFDR Within a Window
FN6009 Rev 4.00
Sep 15, 2015
Page 4 of 14
ISL5761
Electrical Specifications
AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued)
TA = -40oC TO 85oC
PARAMETER
Spurious Free Dynamic Range,
SFDR to Nyquist (fCLK/2)
TEST CONDITIONS
fCLK = 210MSPS, fOUT = 80.8MHz (Notes 4, 7)
fCLK = 210MSPS, fOUT = 40.4MHz (Notes 4, 7, 9)
MIN
TYP
MAX
UNITS
-
50
-
dBc
-
58
-
dBc
fCLK = 200MSPS, fOUT = 20.2MHz, T = 25oC (Notes 4, 7)
58
60
-
dBc
fCLK = 200MSPS, fOUT = 20.2MHz, T = -40oC to 85oC (Notes 4, 7)
56
-
-
dBc
fCLK = 130MSPS, fOUT = 50.5MHz (Notes 4, 7)
-
55
-
dBc
fCLK = 130MSPS, fOUT = 40.4MHz (Notes 4, 7)
-
60
-
dBc
fCLK = 130MSPS, fOUT = 20.2MHz (Notes 4, 7)
-
68
-
dBc
fCLK = 130MSPS, fOUT = 10.1MHz (Notes 4, 7)
-
70
-
dBc
fCLK = 130MSPS, fOUT
= 5.05MHz, T = 25oC (Notes 4, 7)
68
75
-
dBc
fCLK = 130MSPS, fOUT
= 5.05MHz, T = -40oC to 85oC (Notes 4, 7)
66
-
-
dBc
fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 7)
-
58
-
dBc
fCLK = 80MSPS, fOUT = 30.3MHz (Notes 4, 7)
-
61
-
dBc
fCLK = 80MSPS, fOUT = 20.2MHz (Notes 4, 7)
-
67
-
dBc
fCLK = 80MSPS, fOUT = 10.1MHz (Notes 4, 7, 9)
-
69
-
dBc
fCLK = 80MSPS, fOUT = 5.05MHz (Notes 4, 7)
-
74
-
dBc
fCLK = 50MSPS, fOUT = 20.2MHz (Notes 4, 7)
-
66
-
dBc
fCLK = 50MSPS, fOUT = 10.1MHz (Notes 4, 7)
-
72
-
dBc
fCLK = 50MSPS, fOUT = 5.05MHz (Notes 4, 7)
-
75
-
dBc
fCLK = 210MSPS, fOUT = 28.3MHz to 45.2MHz, 2.1MHz Spacing,
50MHz Span (Notes 4, 7, 9)
-
63
-
dBc
fCLK = 130MSPS, fOUT =17.5MHz to 27.9MHz, 1.3MHz Spacing,
35MHz Span (Notes 4, 7)
-
66
-
dBc
fCLK = 80MSPS, fOUT = 10.8MHz to 17.2MHz, 811kHz Spacing,
15MHz Span (Notes 4, 7)
-
73
-
dBc
fCLK = 50MSPS, fOUT = 6.7MHz to 10.8MHz, 490kHz Spacing,
10MHz Span (Notes 4, 7)
-
75
-
dBc
-
83
-
dBc
-
65
-
dB
1.2
1.23
1.3
V
-
40
-
ppm/oC
-
0
-
A
Reference Input Impedance
-
1
-
M
Reference Input Multiplying Bandwidth (Note 7)
-
1.0
-
MHz
Spurious Free Dynamic Range,
SFDR in a Window with Eight Tones
Spurious Free Dynamic Range,
fCLK = 78MSPS, fOUT = 11MHz, in a 20MHz Window, RBW=30kHz
SFDR in a Window with EDGE or GSM (Notes 4, 7, 9)
Adjacent Channel Power Ratio,
ACPR with UMTS
fCLK = 76.8MSPS, fOUT = 19.2MHz, RBW=30kHz (Notes 4, 7, 9)
VOLTAGE REFERENCE
Internal Reference Voltage, VFSADJ
Pin 18 Voltage with Internal Reference
Internal Reference Voltage Drift
Internal Reference Output Current
Sink/Source Capability
DIGITAL INPUTS
Reference is not intended to be externally loaded (REFIO pin)
D9-D0, CLK
Input Logic High Voltage with
3.3V Supply, VIH
(Note 3)
2.3
3.3
-
V
Input Logic Low Voltage with
3.3V Supply, VIL
(Note 3)
-
0
1.0
V
-25
-
+25
A
Sleep Input Current, IIH
FN6009 Rev 4.00
Sep 15, 2015
Page 5 of 14
ISL5761
Electrical Specifications
AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued)
TA = -40oC TO 85oC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Logic Current, IIH, IL
-20
-
+20
A
Clock Input Current, IIH, IL
-10
-
+10
A
-
5
-
pF
Digital Input Capacitance, CIN
TIMING CHARACTERISTICS
Data Setup Time, tSU
See Figure 15
-
1.5
-
ns
Data Hold Time, tHLD
See Figure 15
-
1.5
-
ns
Propagation Delay Time, tPD
See Figure 15
-
1
-
Clock
Cycles
CLK Pulse Width, tPW1 , tPW2
See Figure 15 (Note 3)
2
-
-
ns
POWER SUPPLY CHARACTERISTICS
AVDD Power Supply
(Note 8)
2.7
3.3
3.6
V
DVDD Power Supply
(Note 8)
2.7
3.3
3.6
V
Analog Supply Current (IAVDD)
3.3V, IOUTFS = 20mA
-
27.5
28.5
mA
3.3V, IOUTFS = 2mA
-
10
-
mA
3.3V (Note 5)
-
3.7
5
mA
3.3V (Note 6)
-
6.5
8
mA
Supply Current (IAVDD) Sleep Mode
3.3V, IOUTFS = Don’t Care
-
1.5
-
mA
Power Dissipation
3.3V, IOUTFS = 20mA (Note 5)
-
103
111
mW
3.3V, IOUTFS = 20mA (Note 6)
-
110
120
mW
3.3V, IOUTFS = 2mA (Note 5)
-
45
-
mW
-0.125
-
+0.125
%FSR/V
Digital Supply Current (IDVDD)
Power Supply Rejection
Single Supply (Note 7)
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625A). Ideally the
ratio should be 32.
3. Parameter guaranteed by design or characterization and not production tested.
4. Spectral measurements made with differential transformer coupled output and no external filtering. For multitone testing, the same pattern was
used at different clock rates, producing different output frequencies but at the same ratio to the clock rate.
5. Measured with the clock at 130MSPS and the output frequency at 5MHz.
6. Measured with the clock at 200MSPS and the output frequency at 20MHz.
7. See “Definition of Specifications”.
8. Recommended operation is from 3.0V to 3.6V. Operation below 3.0V is possible with some degradation in spectral performance. Reduction in
analog output current may be necessary to maintain spectral performance.
9. See Typical Performance Plots.
FN6009 Rev 4.00
Sep 15, 2015
Page 6 of 14
ISL5761
Typical Performance (+3.3V Supply, Using Figure 13 with RDIFF = 100 and RLOAD= 50)
SPECTRAL MASK FOR
GSM900/DCS1800/PCS1900
P>43dBm NORMAL BTS
WITH 30kHz RBW
FIGURE 1. EDGE AT 11MHz, 78MSPS CLOCK
(83+dBc @ f = +6MHz)
FIGURE 2. EDGE AT 11MHz, 78MSPS CLOCK (75dBc NYQUIST, 6dB PAD)
SPECTRAL MASK FOR
GSM900/DCS1800/PCS1900
P>43dBm NORMAL BTS
WITH 30kHz RBW
FIGURE 3. GSM AT 11MHz, 78MSPS CLOCK
(86+dBc @ f = +6MHz, 3dB PAD)
FIGURE 4. GSM AT 11MHz, 78MSPS CLOCK (78dBc NYQUIST, 9dB PAD)
FIGURE 5. FOUR EDGE CARRIERS AT 12.4-15.6MHz, 800kHz
SPACING, 78MSPS (67dBc - 20MHz WINDOW)
FIGURE 6. FOUR GSM CARRIERS AT 12.4-15.6MHz, 78MSPS
(71dBc - 20MHz WINDOW, 6dB PAD)
FN6009 Rev 4.00
Sep 15, 2015
Page 7 of 14
ISL5761
Typical Performance (+3.3V Supply, Using Figure 13 with RDIFF = 100 and RLOAD= 50)
(Continued)
SPECTRAL MASK
UMTS TDD
P>43dBm BTS
FIGURE 7. UMTS AT 19.2MHz, 76.8MSPS (65dB 1stACPR,
64dB 2ndACPR)
FIGURE 9. ONE TONE AT 40.4MHz, 210MSPS CLOCK (61dBc
- NYQUIST, 6dB PAD)
FIGURE 11. TWO TONES (CF=6) AT 8.5MHz, 50MSPS CLOCK,
500kHz SPACING (80dBc - 10MHz WINDOW,
6dB PAD)
FN6009 Rev 4.00
Sep 15, 2015
FIGURE 8. ONE TONE AT 10.1MHz, 80MSPS CLOCK (71dBc NYQUIST, 6dB PAD)
FIGURE 10. EIGHT TONES (CREST FACTOR=8.9) AT 37MHz,
210MSPS CLOCK, 2.1MHz SPACING
(64dBc - NYQUIST)
FIGURE 12. FOUR TONES (CF=8.1) AT 14MHz, 80MSPS
CLOCK, 800kHz SPACING (70dBc - NYQUIST,
6dB PAD)
Page 8 of 14
ISL5761
Definition of Specifications
Adjacent Channel Power Ratio, ACPR, is the ratio of the
average power in the adjacent frequency channel (or offset) to
the average power in the transmitted frequency channel.
Differential Linearity Error, DNL, is the measure of the step
size output deviation from code to code. Ideally the step size
should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
EDGE, Enhanced Data for Global Evolution, a TDMA
standard for cellular applications which uses 200kHz BW, 8PSK modulated carriers.
Full Scale Gain Drift, is measured by setting the data inputs to
be all logic high (all 1s) and measuring the output voltage
through a known resistance as the temperature is varied from
TMIN to TMAX . It is defined as the maximum deviation from the
value measured at room temperature to the value measured at
either TMIN or TMAX . The units are ppm of FSR (full scale
range) per oC.
Full Scale Gain Error, is the error from an ideal ratio of 32
between the output current and the full scale adjust current
(through RSET).
GSM, Global System for Mobile Communication, a TDMA
standard for cellular applications which uses 200kHz BW,
GMSK modulated carriers.
Integral Linearity Error, INL, is the measure of the worst case
point that deviates from a best fit straight line of data values
along the transfer curve.
Internal Reference Voltage Drift, is defined as the maximum
deviation from the value measured at room temperature to the
value measured at either TMIN or TMAX . The units are ppm per
oC.
Offset Drift, is measured by setting the data inputs to all logic
low (all 0s) and measuring the output voltage at IOUTA through
a known resistance as the temperature is varied from TMIN to
TMAX . It is defined as the maximum deviation from the value
measured at room temperature to the value measured at either
TMIN or TMAX . The units are ppm of FSR (full scale range) per
degree oC.
Offset Error, is measured by setting the data inputs to all logic
low (all 0s) and measuring the output voltage of IOUTA through
a known resistance. Offset error is defined as the maximum
deviation of the IOUTA output current from a value of 0mA.
Output Voltage Compliance Range, is the voltage limit
imposed on the output. The output impedance should be
chosen such that the voltage developed does not violate the
compliance range.
Power Supply Rejection, is measured using a single power
supply. The nominal supply voltage is varied 10% and the
change in the DAC full scale output is noted.
FN6009 Rev 4.00
Sep 15, 2015
Reference Input Multiplying Bandwidth, is defined as the
3dB bandwidth of the voltage reference input. It is measured
by using a sinusoidal waveform as the external reference with
the digital inputs set to all 1s. The frequency is increased until
the amplitude of the output waveform is 0.707 (-3dB) of its
original value.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from the fundamental signal to the largest
harmonically or non-harmonically related spur within the
specified frequency window.
Total Harmonic Distortion, THD, is the ratio of the RMS value
of the fundamental output signal to the RMS sum of the first
five harmonic components.
UMTS, Universal Mobile Telecommunications System, a
W-CDMA standard for cellular applications which uses
3.84MHz modulated carriers.
Detailed Description
The ISL5761 is a 10-bit, current out, CMOS, digital to analog
converter. The maximum update rate is at least 210+MSPS
and can be powered by a single power supply in the
recommended range of +3.0V to +3.6V. Operation with clock
rates higher than 210MSPS is possible; please contact the
factory for more information. It consumes less than 120mW of
power when using a +3.3V supply, the maximum 20mA of
output current, and the data switching at 210MSPS. The
architecture is based on a segmented current source
arrangement that reduces glitch by reducing the amount of
current switching at any one time. In previous architectures
that contained all binary weighted current sources or a binary
weighted resistor ladder, the converter might have a
substantially larger amount of current turning on and off at
certain, worst-case transition points such as midscale and
quarter scale transitions. By greatly reducing the amount of
current switching at these major transitions, the overall glitch of
the converter is dramatically reduced, improving settling time,
transient problems, and accuracy.
Digital Inputs and Termination
The ISL5761 digital inputs are guaranteed to 3V LVCMOS
levels. The internal register is updated on the rising edge of the
clock. To minimize reflections, proper termination should be
implemented. If the lines driving the clock and the digital inputs
are long 50 lines, then 50 termination resistors should be
placed as close to the converter inputs as possible connected
to the digital ground plane (if separate grounds are used).
These termination resistors are not likely needed as long as
the digital waveform source is within a few inches of the DAC.
For pattern drivers with very high speed edge rates, it is
recommended that the user consider series termination (50200prior to the DAC’s inputs in order to reduce the amount
of noise.
Page 9 of 14
ISL5761
Power Supply
Separate digital and analog power supplies are recommended.
The allowable supply range is +2.7V to +3.6V. The
recommended supply range is +3.0 to 3.6V (nominally +3.3V)
to maintain optimum SFDR. However, operation down to +2.7V
is possible with some degradation in SFDR. Reducing the
analog output current can help the SFDR at +2.7V. The SFDR
values stated in the table of specifications were obtained with a
+3.3V supply.
Ground Planes
Separate digital and analog ground planes should be used. All
of the digital functions of the device and their corresponding
components should be located over the digital ground plane
and terminated to the digital ground plane. The same is true for
the analog components and the analog ground plane.
Noise Reduction
To minimize power supply noise, 0.1F capacitors should be
placed as close as possible to the converter’s power supply
pins, AVDD and DVDD . Also, the layout should be designed
using separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for DVDD
and to the analog ground for AVDD . Additional filtering of the
power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal value
of +1.23V with a 40ppm/ oC drift coefficient over the full
temperature range of the converter. It is recommended that a
0.1F capacitor be placed as close as possible to the REFIO
pin, connected to the analog ground. The REFLO pin (16)
selects the reference. The internal reference can be selected if
pin 16 is tied low (ground). If an external reference is desired,
then pin 16 should be tied high (the analog supply voltage) and
the external reference driven into REFIO, pin 17. The full scale
output current of the converter is a function of the voltage
reference used and the value of RSET. IOUT should be within
the 2mA to 20mA range, though operation below 2mA is
possible, with performance degradation.
If the internal reference is used, VFSADJ will equal
approximately 1.2V (pin 18). If an external reference is used,
VFSADJ will equal the external reference. The calculation for
IOUT (Full Scale) is:
IOUT(Full Scale) = (VFSADJ/RSET) X 32.
If the full scale output current is set to 20mA by using the
internal voltage reference (1.2V) and a 1.91k RSET resistor,
then the input coding to output current will resemble the
following:
FN6009 Rev 4.00
Sep 15, 2015
TABLE 1. INPUT CODING vs OUTPUT CURRENT WITH INTERNAL
REFERENCE AND RSET=1.91K
INPUT CODE (D9-D0)
IOUTA (mA)
IOUTB (mA)
11111 11111
20
0
10000 00000
10
10
00000 00000
0
20
Analog Output
IOUTA and IOUTB are complementary current outputs. The
sum of the two currents is always equal to the full scale output
current minus one LSB. If single ended use is desired, a load
resistor can be used to convert the output current to a voltage.
It is recommended that the unused output be either grounded
or equally terminated. The voltage developed at the output
must not violate the output voltage compliance range of -1.0V
to 1.25V. ROUT (the impedance loading each current output)
should be chosen so that the desired output voltage is
produced in conjunction with the output full scale current. If a
known line impedance is to be driven, then the output load
resistor should be chosen to match this impedance. The output
voltage equation is:
VOUT = IOUT X ROUT.
The most effective method for reducing the power
consumption is to reduce the analog output current, which
dominates the supply current. The maximum recommended
output current is 20mA.
Differential Output
IOUTA and IOUTB can be used in a differential-to-singleended arrangement to achieve better harmonic rejection. With
RDIFF= 50and RLOAD=50, the circuit in Figure 13 will
provide a 500mV (-2.5dBm) signal at the output of the
transformer if the full scale output current of the DAC is set to
20mA (used for the electrical specifications table). Values of
RDIFF= 100and RLOAD=50 were used for the typical
performance curves. The center tap in Figure 13 must be
grounded.
In the circuit in Figure 14, the user is left with the option to
ground or float the center tap. The DC voltage that will exist at
either IOUTA or IOUTB if the center tap is floating is IOUTDC x
(RA//RB) V because RDIFF is DC shorted by the transformer. If
the center tap is grounded, the DC voltage is 0V.
Recommended values for the circuit in Figure 14 are
RA=RB=50, RDIFF=100, assuming RLOAD=50. The
performance of Figure 13 and Figure 14 is basically the same,
however leaving the center tap of Figure 14 floating allows the
circuit to find a more balanced virtual ground, theoretically
improving the even order harmonic rejection, but likely
reducing the signal swing available due to the output voltage
compliance range limitations.
Page 10 of 14
ISL5761
Propagation Delay
REQ = 0.5 x (RLOAD // RDIFF)
AT EACH OUTPUT
PIN 21
PIN 22
ISL5761
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous data.
The propagation delay is therefore 1/CLK, plus <2ns of
processing. See Figure 15.
VOUT = (2 x IOUTA x REQ)V
1:1
IOUTB
RDIFF
RLOAD
IOUTA
Test Service
Intersil offers customer-specific testing of converters with a
service called Testdrive. To submit a request, fill out the
Testdrive form. The form can be found by doing an ‘entire site
search’ at www.intersil.com on the words ‘DAC Testdrive’. Or,
send a request to the technical support center.
RLOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 13. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
REQ = 0.5 x (RLOAD // RDIFF// RA), WHERE RA=RB
AT EACH OUTPUT
RA
PIN 21
PIN 22
ISL5761
IOUTB
VOUT = (2 x IOUTA x REQ)V
RDIFF
IOUTA
RLOAD
RB
RLOAD REPRESENTS THE
LOAD SEEN BY THE TRANSFORMER
FIGURE 14. ALTERNATIVE OUTPUT LOADING
Timing Diagram
tPW2
tPW1
50%
CLK
tSU
tSU
tHLD
D9-D0
W0
tSU
tHLD
tHLD
W1
W2
W3
tPD
tPD
OUTPUT=W0
IOUT
OUTPUT=W-1
OUTPUT=W1
FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
FN6009 Rev 4.00
Sep 15, 2015
Page 11 of 14
ISL5761
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
September 15, 2015
FN6009.4
CHANGE
Updated the Ordering Information table on page 1.
Added Revision History and About Intersil sections.
Updated Package Outline Drawing M28.173 to the latest revision. Changes are as follows:
-Convert to new POD format by moving dimensions from table onto drawing and adding land pattern. No
dimension changes.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2001-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6009 Rev 4.00
Sep 15, 2015
Page 12 of 14
ISL5761
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010) M
H
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
MAX
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
e
µ
MIN
0.05 BSC
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o

10.00
28
0o
10.65
-
0.394
N
0.419
1.27 BSC
H
28
-
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
FN6009 Rev 4.00
Sep 15, 2015
Page 13 of 14
ISL5761
Package Outline Drawing
M28.173
28 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 1, 5/10
A
9.70± 0.10
1
3
SEE DETAIL "X"
15
28
6.40
PIN #1
I.D. MARK
4.40 ± 0.10
2
3
0.20 C B A
1
14
0.15 +0.05
-0.06
B
0.65
TOP VIEW
END VIEW
1.00 REF
H
- 0.05
0.90 +0.15
-0.10
C
GAUGE
PLANE
1.20 MAX
SEATING PLANE
+0.05
0.25
5
-0.06
0.10 M C B A
0.10 C
0.25
0°-8°
0.05 MIN
0.15 MAX
0.60 ±0.15
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
(5.65)
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
(0.65 TYP)
TYPICAL RECOMMENDED LAND PATTERN
(0.35 TYP)
is 0.07mm.
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153.
FN6009 Rev 4.00
Sep 15, 2015
Page 14 of 14
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