TI1 LM5101AM Lm5100a/b/c lm5101a/b/c 3a, 2a and 1a high voltage high-side and low-side gate driver Datasheet

LM5100A,LM5100B,LM5100C,LM5101A,LM5101B,
LM5101C
LM5100A/B/C LM5101A/B/C 3A, 2A and 1A High Voltage High-Side and Low-Side
Gate Drivers
Literature Number: SNOSAW2M
August 20, 2011
3A, 2A and 1A High Voltage High-Side and Low-Side Gate
Drivers
General Description
The LM5100A/B/C and LM5101A/B/C High Voltage Gate
Drivers are designed to drive both the high-side and the lowside N-Channel MOSFETs in a synchronous buck or a halfbridge configuration. The floating high-side driver is capable
of operating with supply voltages up to 100V. The “A” versions
provide a full 3A of gate drive while the “B” and “C” versions
provide 2A and 1A respectively. The outputs are independently controlled with CMOS input thresholds (LM5100A/B/C)
or TTL input thresholds (LM5101A/B/C). An integrated high
voltage diode is provided to charge the high-side gate drive
bootstrap capacitor. A robust level shifter operates at high
speed while consuming low power and providing clean level
transitions from the control logic to the high-side gate driver.
Under-voltage lockout is provided on both the low-side and
the high-side power rails. These devices are available in the
standard SOIC-8 pin, PSOP-8 pin and the LLP-10 pin packages. The LM5100C and LM5101C are also available in
eMSOP-8 package. The LM5101A is also available in LLP-8
pin package.
Features
■ Drives both a high-side and low-side N-Channel
MOSFETs
■ Independent high and low driver logic inputs
■
■
■
■
■
■
■
Bootstrap supply voltage up to 118V DC
Fast propagation times (25 ns typical)
Drives 1000 pF load with 8 ns rise and fall times
Excellent propagation delay matching (3 ns typical)
Supply rail under-voltage lockout
Low power consumption
Pin compatible with HIP2100/HIP2101
Typical Applications
■
■
■
■
■
Current Fed push-pull converters
Half and Full Bridge power converters
Synchronous buck converters
Two switch forward power converters
Forward with Active Clamp converters
Package
■
■
■
■
■
SOIC-8
PSOP-8
LLP-8 (4 mm x 4 mm)
LLP-10 (4 mm x 4 mm)
eMSOP-8
Simplified Block Diagram
20203103
FIGURE 1.
© 2011 National Semiconductor Corporation
202031
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LM5100A/B/C, LM5101A/B/C 3A, 2A and 1A High Voltage High-Side and Low-Side Gate Drivers
LM5100A/B/C
LM5101A/B/C
LM5100A/B/C, LM5101A/B/C
Input/Output Options
Part Number
Input Thresholds
Peak Output Current
LM5100A
CMOS
3A
LM5101A
TTL
3A
LM5100B
CMOS
2A
LM5101B
TTL
2A
LM5100C
CMOS
1A
LM5101C
TTL
1A
Connection Diagrams
20203101
20203137
20203102
20203135
20203136
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2
Ordering Number
Package Type
NSC Package Drawing
Supplied As
LM5100A/LM5101AM
SOIC 8
M08A
95 units shipped in anti static rails
LM5100A/LM5101AMX
SOIC 8
M08A
2500 shipped in Tape & Reel
LM5100A/LM5101AMR
PSOP 8
MRA08A
95 units shipped in anti static rails
LM5100A/LM5101AMRX
PSOP 8
MRA08A
2500 shipped in Tape & Reel
1000 shipped in Tape & Reel
LM5100A /LM5101ASD
LLP 10
SDC10A
LM5100A/LM5101ASDX
LLP 10
SDC10A
4500 shipped in Tape & Reel
LM5100B/LM5101BMA
SOIC 8
M08A
95 units shipped in anti static rails
LM5100B/LM5101BMAX
SOIC 8
M08A
2500 shipped in Tape & Reel
LM5100B/LM5101BSD
LLP 10
SDC10A
1000 shipped in Tape & Reel
LM5100B/LM5101BSDX
LLP 10
SDC10A
4500 shipped in Tape & Reel
LM5100C/LM5101CMA
SOIC 8
M08A
95 units shipped in anti static rails
LM5100C/LM5101CMAX
SOIC 8
M08A
2500 shipped in Tape & Reel
LM5100C /LM5101CSD
LLP 10
SDC10A
1000 shipped in Tape & Reel
LM5100C/LM5101CSDX
LLP 10
SDC10A
4500 shipped in Tape & Reel
LM5100C/LM5101CMYE
eMSOP-8
MUY08A
250 shipped in Tape & Reel
LM5100C/LM5101CMY
eMSOP-8
MUY08A
1000 shipped in Tape & Reel
LM5100C/LM5101CMYX
eMSOP-8
MUY08A
3500 shipped in Tape & Reel
LM5101ASD-1
LLP 8
SDC08A
1000 shipped in Tape & Reel
LM5101ASDX-1
LLP 8
SDC08A
4500 shipped in Tape & Reel
3
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LM5100A/B/C, LM5101A/B/C
Ordering Information
LM5100A/B/C, LM5101A/B/C
Pin Descriptions
Pin #
Name
SOIC-8
PSOP-8
LLP-8
LLP-10
eMSOP-8
1
1
1
1
1
VDD
2
2
2
2
2
3
3
3
3
4
4
4
5
5
6
Description
Application Information
Positive gate drive
supply
Locally decouple to VSS using low
ESR/ESL capacitor located as close
to the IC as possible.
HB
High-side gate driver
bootstrap rail
Connect the positive terminal of the
bootstrap capacitor to HB and the
negative terminal to HS. The
bootstrap capacitor should be placed
as close to the IC as possible.
3
HO
High-side gate driver
output
Connect to the gate of high-side
MOSFET with a short, low
inductance path.
4
4
HS
High-side MOSFET
source connection
Connect to the bootstrap capacitor
negative terminal and the source of
the high-side MOSFET.
5
7
5
HI
High-side driver
control input
The LM5100A/B/C inputs have
CMOS type thresholds. The
LM5101A/B/C inputs have TTL type
thresholds. Unused inputs should be
tied to ground and not left open.
6
6
8
6
LI
Low-side driver
control input
The LM5100A/B/C inputs have
CMOS type thresholds. The
LM5101A/B/C inputs have TTL type
thresholds. Unused inputs should be
tied to ground and not left open.
7
7
7
9
7
VSS
Ground return
All signals are referenced to this
ground.
8
8
8
10
8
LO
Low-side gate driver
output
Connect to the gate of the low-side
MOSFET with a short, low
inductance path.
EP
EP
EP
EP
EP (LLP and PSOP and eMSOP
packages)
Solder to the ground plane under the
IC to aid in heat dissipation.
Note: For LLP-8, LLP-10 and eMSOP-8 package, it is recommended that the exposed pad on the bottom of the package is soldered to ground plane
on the PC board, and that ground plane should extend out from beneath the IC to help dissipate heat. For LLP-10 package, pins 5 and 6 have no
connection.
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4
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VDD to VSS
HB to HS
LI or HI Input
LO Output
HO Output
HS to VSS (Note 6)
HB to VSS
+150°C
−55°C to +150°C
2 kV
Recommended Operating
Conditions
−0.3V to +18V
−0.3V to +18V
−0.3V to VDD +0.3V
−0.3V to VDD +0.3V
VHS −0.3V to VHB +0.3V
−5V to +100V
118V
VDD
HS
HB
HS Slew Rate
Junction Temperature
+9V to +14V
−1V to 100V
VHS +8V to VHS +14V
< 50 V/ns
−40°C to +125°C
Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to
+125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the
most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD = VHB =
12V, VSS = VHS = 0V, No Load on LO or HO (Note 4).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SUPPLY CURRENTS
IDD
VDD Quiescent Current, LM5100A/B/C
LI = HI = 0V
0.1
0.2
VDD Quiescent Current, LM5101A/B/C
LI = HI = 0V
0.25
0.4
IDDO
VDD Operating Current
f = 500 kHz
2.0
3
mA
IHB
Total HB Quiescent Current
LI = HI = 0V
0.06
0.2
mA
IHBO
Total HB Operating Current
f = 500 kHz
1.6
3
mA
IHBS
HB to VSS Current, Quiescent
HS = HB = 100V
0.1
10
IHBSO
HB to VSS Current, Operating
f = 500 kHz
0.4
mA
µA
mA
INPUT PINS
VIL
Input Voltage Threshold LM5100A/B/C
Rising Edge
4.5
VIL
Input Voltage Threshold LM5101A/B/C
Rising Edge
1.3
VIHYS
Input Voltage Hysteresis LM5100A/B/C
VIHYS
Input Voltage Hysteresis LM5101A/B/C
RI
Input Pulldown Resistance
5.4
6.3
1.8
2.3
500
V
V
mV
50
mV
100
200
400
kΩ
6.0
6.9
7.4
V
UNDER VOLTAGE PROTECTION
VDDR
VDD Rising Threshold
VDDH
VDD Threshold Hysteresis
VHBR
HB Rising Threshold
VHBH
HB Threshold Hysteresis
0.5
5.7
6.6
V
7.1
0.4
V
V
BOOT STRAP DIODE
VDL
Low-Current Forward Voltage
IVDD-HB = 100 µA
0.52
0.85
V
VDH
High-Current Forward Voltage
IVDD-HB = 100 mA
0.8
1
V
RD
Dynamic Resistance LM5100A/B/C, LM5101A/B/ IVDD-HB = 100 mA
C
1.0
1.65
Ω
0.12
0.25
LO & HO GATE DRIVER
VOL
VOH
Low-Level Output Voltage LM5100A/LM5101A
Low-Level Output Voltage LM5100B/LM5101B
0.16
0.4
Low-Level Output Voltage LM5100C/LM5101C
0.28
0.65
0.24
0.45
0.28
0.60
0.60
1.10
High-Level Output Voltage LM5100A/LM5101A
High-Level Output Voltage LM5100C/LM5101C
IHO = ILO = 100 mA
VOH = VDD– LO or
VOH = HB - HO
Peak Pullup Current LM5100A/LM5101A
HO, LO = 0V
High-Level Output Voltage LM5100B/LM5101B
IOHL
IHO = ILO = 100 mA
V
3
Peak Pullup Current LM5100B/LM5101B
2
Peak Pullup Current LM5100C/LM5101C
1
5
V
A
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LM5100A/B/C, LM5101A/B/C
Junction Temperature
Storage Temperature Range
ESD Rating HBM (Note 2)
Absolute Maximum Ratings (Note 1)
LM5100A/B/C, LM5101A/B/C
Symbol
IOLL
Parameter
Peak Pulldown Current LM5100A/LM5101A
Conditions
Min
Typ
HO, LO = 12V
Max
Units
3
Peak Pulldown Current LM5100B/LM5101B
2
Peak Pulldown Current LM5100C/LM5101C
1
A
THERMAL RESISTANCE
θJA
Junction to Ambient
SOIC-8
170
LLP-8(Note 3)
40
LLP-10 (Note 3)
40
PSOP-8
40
eMSOP-8 (Note 3)
80
°C/W
Switching Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to
+125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the
most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD = VHB =
12V, VSS = VHS = 0V, No Load on LO or HO (Note 4).
Symbol
tLPHL
Parameter
Typ
Max
20
45
22
56
20
45
26
56
20
45
22
56
20
45
LO Turn-On Propagation Delay
LM5101A/B/C
26
56
Delay Matching: LO on & HO off
LM5100A/B/C
1
10
Delay Matching: LO on & HO off
LM5101A/B/C
4
10
Delay Matching: LO off & HO on
LM5100A/B/C
1
10
Delay Matching: LO on & HO off
LM5101A/B/C
4
10
LO Turn-Off Propagation Delay
LM5100A/B/C
Conditions
LI Falling to LO Falling
LO Turn-On Propagation Delay
LM5100A/B/C
LI Rising to LO Rising
ns
LO Turn-On Propagation Delay
LM5101A/B/C
tHPHL
HO Turn-Off Propagation Delay
LM5100A/B/C
HI Falling to HO Falling
ns
HO Turn-Off Propagation Delay
LM5101A/B/C
tHPLH
tMON
tMOFF
LO Turn-On Propagation Delay
LM5100A/B/C
HI Rising to HO Rising
ns
Either Output Rise/Fall Time
CL = 1000 pF
tR
Output Rise Time (3V to 9V) LM5100A/
LM5101A
CL = 0.1 µF
8
ns
570
Output Rise Time (3V to 9V) LM5100C/
LM5101C
990
CL = 0.1 µF
260
Output Fall Time (3V to 9V) LM5100B/
LM5101B
430
Output Fall Time (3V to 9V) LM5100C/
LM5101C
715
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ns
430
Output Rise Time (3V to 9V) LM5100B/
LM5101B
Output Fall Time (3V to 9V) LM5100A/
LM5101A
ns
ns
tRC, tFC
tF
Units
ns
LO Turn-Off Propagation Delay
LM5101A/B/C
tLPLH
Min
6
ns
Parameter
Conditions
Min
Typ
Max
Units
tPW
Minimum Input Pulse Width that Changes
the Output
50
ns
tBS
Bootstrap Diode Reverse Recovery Time IF = 100 mA,
IR = 100 mA
37
ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics tables.
Note 2: The Human Body Model (HBM) is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. 2 kV for all pins except Pin 2, Pin 3 and Pin 4
which are rated at 1000V for HBM. Machine Model (MM) ratings are : 100V(MM) for Options B and C; 50V(MM) for Option A.
Note 3: 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power
planes embedded in PCB. See Application Note AN-1187.
Note 4: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 5: The θJA is not a given constant for the package and depends on the printed circuit board design and the operating environment.
Note 6: In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not exceed -1V.
However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur,
the HS voltage must never be more negative than VDD-15V. For example if VDD = 10V, the negative transients at HS must not exceed -5V.
Typical Performance Characteristics
Peak Sourcing Current vs VDD
Peak Sinking Current vs VDD
20203128
20203127
Sink Current vs Output Voltage
Source Current vs Output Voltage
20203129
20203130
7
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LM5100A/B/C, LM5101A/B/C
Symbol
LM5100A/B/C, LM5101A/B/C
LM5100A/B/C IDD vs Frequency
LM5101A/B/C IDD vs Frequency
20203110
20203109
Operating Current vs Temperature
IHB vs Frequency
20203111
20203114
Quiescent Current vs Supply Voltage
Quiescent Current vs Temperature
20203119
20203118
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8
Undervoltage Threshold Hysteresis vs Temperature
20203122
20203117
Bootstrap Diode Forward Voltage
LM5100A/B/C Input Threshold vs Temperature
20203123
20203115
LM5101A/B/C Input Threshold vs Temperature
LM5100A/B/C Input Threshold vs VDD
20203125
20203124
9
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LM5100A/B/C, LM5101A/B/C
Undervoltage Rising Thresholds vs Temperature
LM5100A/B/C, LM5101A/B/C
LM5101A/B/C Input Threshold vs VDD
LM5100A/B/C Propagation Delay vs Temperature
20203126
20203112
LM5101A/B/C Propagation Delay vs Temperature
LO & HO Gate Drive - High Level Output Voltage vs
Temperature
20203113
20203120
LO & HO Gate Drive - Low Level Output Voltage vs
Temperature
LO & HO Gate Drive - Output High Voltage vs VDD
20203131
20203121
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10
LM5100A/B/C, LM5101A/B/C
LO & HO Gate Drive - Output Low Voltage vs VDD
20203132
Timing Diagram
20203104
FIGURE 2.
11
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LM5100A/B/C, LM5101A/B/C
discharge the MOSFET gate into a minimal physical
area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the
MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
b) The second high current path includes the bootstrap
capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low-side MOSFET
body diode. The bootstrap capacitor is recharged on a
cycle-by-cycle basis through the bootstrap diode from
the ground referenced VDD bypass capacitor. The
recharging occurs in a short time interval and involves
high peak current. Minimizing this loop length and area
on the circuit board is important to ensure reliable
operation.
A recommended layout pattern for the driver is shown in the
following figure. If possible a single layer placement is preferred.
Layout Considerations
The optimum performance of high and low-side gate drivers
cannot be achieved without taking due considerations during
circuit board layout. Following points are emphasized.
1. Low ESR / ESL capacitors must be connected close to
the IC, between VDD and VSS pins and between the HB
and HS pins to support the high peak currents being
drawn from VDD during turn-on of the external MOSFET.
2. To prevent large voltage transients at the drain of the top
MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch
node (HS pin), the parasitic inductances in the source of
top MOSFET and in the drain of the bottom MOSFET
(synchronous rectifier) must be minimized.
4. Grounding Considerations:
a) The first priority in designing grounding connections
is to confine the high peak currents that charge and
20203138
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12
LM5100A/B/C, LM5101A/B/C
Diode Power Dissipation VIN = 50V
Power Dissipation Considerations
The total IC power dissipation is the sum of the gate driver
losses and the bootstrap diode losses. The gate driver losses
are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply voltage (VDD) and can
be roughly calculated as:
PDGATES = 2 • f • CL • VDD2
There are some additional losses in the gate drivers due to
the internal CMOS stages used to buffer the LO and HO outputs. The following plot shows the measured gate driver
power dissipation versus frequency and load capacitance. At
higher frequencies and load capacitance values, the power
dissipation is dominated by the power losses driving the output loads and agrees well with the above equation. This plot
can be used to approximate the power losses due to the gate
drivers.
20203106
Gate Driver Power Dissipation (LO + HO)
VDD = 12V, Neglecting Diode Losses
20203105
The bootstrap diode power loss is the sum of the forward bias
power loss that occurs while charging the bootstrap capacitor
and the reverse bias power loss that occurs during reverse
recovery. Since each of these events happens once per cycle,
the diode power loss is proportional to frequency. Larger capacitive loads require more energy to recharge the bootstrap
capacitor resulting in more losses. Higher input voltages
(VIN) to the half bridge result in higher reverse recovery losses. The following plot was generated based on calculations
and lab measurements of the diode recovery time and current
under several operating conditions. This can be useful for approximating the diode power dissipation.
The total IC power dissipation can be estimated from the previous plots by summing the gate drive losses with the bootstrap diode losses for the intended application.
13
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LM5100A/B/C, LM5101A/B/C
Physical Dimensions inches (millimeters) unless otherwise noted
Controlling dimension is inch. Values in [ ] are millimeters.
Notes: Unless otherwise specified.
1. Standard lead finish to be 200 microinches/5.08 micrometers minimum lead/tin (solder) on copper.
2.
3.
Dimension does not include mold flash.
Reference JEDEC registration MS-012, Variation AA, dated May 1990.
SOIC-8 Outline Drawing
NS Package Number M08A
PSOP-8 Outline Drawing
NS Package Number MRA08A
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14
LM5100A/B/C, LM5101A/B/C
LLP-8 Outline Drawing
NS Package Number SDC08A
Notes: Unless otherwise specified.
1. For solder thickness and composition, see “Solder Information” in the packaging section of the National Semiconductor web page (www.national.com).
2.
3.
Maximum allowable metal burr on lead tips at the package edges is 76 microns.
No JEDEC registration as of May 2003.
LLP-10 Outline Drawing
NS Package Number SDC10A
15
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LM5100A/B/C, LM5101A/B/C
eMSOP-8 Outline Drawing
NS Package Number MUY08A
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16
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17
LM5100A/B/C, LM5101A/B/C
Notes
LM5100A/B/C, LM5101A/B/C 3A, 2A and 1A High Voltage High-Side and Low-Side Gate Drivers
Notes
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SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected
to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
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brand or product names may be trademarks or registered trademarks of their respective holders.
Copyright© 2011 National Semiconductor Corporation
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