NSC CLC416 Dual low-power, 120mhz op amp Datasheet

N
CLC416
Dual Low-Power, 120MHz Op Amp
General Description
Features
The CLC416 is a dual, wideband (120MHz) op amp. The
CLC416 consumes only 39mW per channel and can source or
sink an output current of 60mA. These features make the
CLC416 a versatile, high-speed solution for demanding
applications that are sensitive to both power and cost.
■
Utilizing National’s proven architectures, this dual current
feedback amplifier surpasses the performance of alternative
solutions and sets new standards for low power. This powerconserving dual op amp achieves low distortion with -80dBc and
-80dBc second and third harmonics respectively. Many high
source impedance applications will benefit from the CLC416’s
6MΩ input impedance. And finally, designers will have a bipolar
part with an exceptionally low 100nA non-inverting bias current.
■
■
■
■
■
■
Applications
■
■
■
■
■
■
■
With 0.1dB flatness to 30MHz and low differential gain and phase
errors, the CLC416 is an ideal part for professional video
processing and distribution. The 120MHz -3dB bandwidth (Av =
+2) coupled with a 400V/µs slew rate also makes the CLC416
a perfect choice in cost-sensitive applications such as video
monitors, fax machines, copiers, and CATV systems.
0.01%, 0.03° DG, Dφ
Very low input bias current: 100nA
High input impedance: 6MΩ
120MHz -3dB bandwidth (Av = +2)
Low power
High output current: 60mA
Low-cost
Desktop video systems
Video distribution
Flash A/D driver
High-speed driver
High-source impedance applications
Professional video processing
High resolution monitors
CLC416
Dual Low-Power, 120MHz Op Amp
September 1998
Frequency Response (Av = +2V/V)
Typical Application Diagram
Pinout
Instrumentation Amplifier
V1
DIP & SOIC
+
1/2
CLC416
348Ω
Vo1
348Ω
348Ω
Vout = 3(V2 - V1)
-
348Ω
348Ω
348Ω
CLC405
+
-
V2
1/2
CLC416
+
© 1998 National Semiconductor Corporation
Printed in the U.S.A.
Vinv1
Vnon-inv1
-VCC
+VCC
Vo2
Vinv2
Vnon-inv2
R1
348Ω
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CLC416 Electrical Characteristics (AV = +2, Rf = 348Ω: Vcc = + 5V, RL = 100Ω unless specified)
PARAMETERS
Ambient Temperature
CONDITIONS
CLC416AJ
TYP
+25˚C
MIN/MAX RATINGS
+25˚C
0 to 70˚C -40 to 85˚C
UNITS
NOTES
1
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
Vout < 1.0Vpp
Vout < 5.0Vpp
±0.1dB bandwidth
Vout < 1.0Vpp
gain flatness
Vout < 1.0Vpp
peaking
DC to 200MHz
rolloff
<30MHz
linear phase deviation
<20MHz
differential gain
4.43MHz, RL=150Ω
differential phase
4.43MHz, RL=150Ω
120
52
30
65
40
15
45
36
45
35
MHz
MHz
MHz
0.1
0
0.3
0.01
0.03
0.7
0.3
0.6
0.04
0.08
0.8
0.6
0.7
0.04
0.11
1.0
0.6
0.7
0.04
0.12
dB
dB
deg
%
deg
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.05%
overshoot
slew rate
AV = +2
AV = -1
4.3
22
3
400
700
6.5
30
12
300
7.2
38
12
260
7.4
41
12
250
ns
ns
%
V/µs
V/µs
2V step
2V step
2V step
2V step
1V step
DISTORTION AND NOISE RESPONSE
2Vpp, 1MHz
2nd harmonic distortion
3rd harmonic distortion
2Vpp, 1MHz
2nd harmonic distortion
2Vpp, 10MHz
3rd harmonic distortion
2Vpp, 10MHz
equivalent input noise
voltage
>1MHz
inverting current
>1MHz
non-inverting current
>1MHz
crosstalk, input referred
2Vpp, 10MHz
STATIC DC PERFORMANCE
input offset voltage
average drift
input bias current
average drift
input bias current
average drift
power supply rejection ratio
common-mode rejection ratio
supply current per channel
non-inverting
inverting
DC
DC
RL= ∞
MISCELLANEOUS PERFORMANCE
input resistance
non-inverting
input capacitance
non-inverting
common mode input range
output voltage range
RL = 100Ω
output voltage range
RL = ∞
output current
output resistance, closed loop
-80
-80
-65
-57
-55
-50
-50
-45
-47
-45
dBc
dBc
dBc
dBc
5
12
3
72
6.3
15
3.8
66
6.6
16
4.0
66
6.7
17
4.2
66
nV/√Hz
pA/√Hz
pA/√Hz
dB
1
30
100
3
1
17
52
50
3.9
5
47
45
4.5
7
50
1600
8
6
40
47
45
4.6
8
50
2800
11
8
45
45
43
4.9
mV
µV/˚C
nA
nA/˚C
µA
nA/˚C
dB
dB
mA
3
2
±1.8
+3.1/-2.8
+3.9/-3.3
44
0.2
2.4
2
±1.7
+2.9/-2.7
+3.8/-3.2
38
0.25
1
2
±1.5
+2.4/-1.7
+3.7/-2.8
20
0.4
MΩ
pF
V
V
V
mA
Ω
6
1
±2.2
+3.5,-2.9
+4.0,-3.4
60
0.06
900
5
A
A
A
A
Recommended gain range +1 to +40V/V
Transistor count = 110
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
supply voltage
Iout is short circuit protected to ground
common-mode input voltage
maximum junction temperature
storage temperature range
lead temperature (soldering 10 sec)
ESD rating (human body model)
Model
CLC416AJP
CLC416AJE
Notes
1) At temps < 0˚C, spec is guaranteed for RL = 500Ω.
A) J-level: spec is 100% tested at +25˚C.
±7V
±Vcc
+175˚C
-65˚C to +150˚C
+300˚C
1000V
Ordering Information
Package Thermal Resistance
Temperature Range
Package
-40˚C to +85˚C
-40˚C to +85˚C
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Description
8-pin PDIP
8-pin SOIC
Plastic (AJP)
Surface Mount (AJE)
2
θJC
θJA
80°C/W
95°C/W
95°C/W
115°C/W
CLC416 Typical Performance Characteristics (Vcc = ±5V, Av = +2, Rf = 348ΩΩ, RL = 100ΩΩ;
Inverting Frequency Response
0
-90
-180
Av = 10
Rf = 100Ω
-270
Av = 4
Rf = 200Ω
-360
-450
1
10
Av = -2
Rf = 348Ω
Av = -1
Rf = 2kΩ
Av = -4
Rf = 255Ω
0
-90
Vo = 1Vpp
Av = +2
-180
-270
-360
Av = -10
Rf = 200Ω
RL = 100Ω RL = 1kΩ
-450
RL = 50Ω
RL = 1kΩ
-90
RL = 100Ω
-180
RL = 50Ω
-270
-360
-630
10
-450
100
1
10
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. Vout
0
-540
1
100
Frequency Response vs. RL
Magnitude (1dB/div)
Normalized Magnitude (1dB/div)
Av = 2
Rf = 348Ω
Vo = 0.5Vpp
Phase (deg)
Av = 1
Rf = 1.65kΩ
Phase (deg)
Vo = 0.5Vpp
Phase (deg)
Normalized Magnitude (1dB/div)
Frequency Response
unless specified)
100
Frequency (MHz)
Open Loop Transimpedance Gain, Z(s)
Frequency Response vs. CL
130
200
Vo = 1Vpp
2Vpp
5Vpp
0.2Vpp
20 log [|Vo/|i|] (dBΩ)
Rs = 107Ω
CL = 10pF
Magnitude (1dB/div)
1Vpp
Rs = 39.25Ω
CL = 47pF
Rs = 27.4Ω
CL = 100pF
Rs = 8Ω
CL = 1000pF
Rs
348Ω
348Ω
CL
110
160
Gain
90
120
Phase
70
80
-
Ii
50
1k
CLC416
Vo
40
+
100Ω
30
1
10
1
100
10
Frequency (MHz)
Maximum Output Voltage vs. RL
Distortion Level (dBc)
80
Rs (Ω)
60
40
-2
20
0
200
300
400
500
100
2nd Harmonic Distortion vs. Pout
50Ω
10MHz
-70
-75
1MHz
-85
-60
-80
0.30
0.09
0.27
0.08
0.24
0.07
0.21
0.06
-5
0
5
0.18
0.05
0.15
Gain Negative
Sync
Phase Negative Sync
0.04
0.12
0.03
1MHz
0.09
0.02
500kHz
-100
-10
10
0.06
Phase Positive Sync
0.03
Gain Positive Sync
0
-10
Output Power (dBm)
-5
0
5
1
10
Small Signal Pulse Response
3
2
Output Power (dBm)
0
4
Number of 150Ω Loads
Large Signal Pulse Response
0.08
PSRR and CMRR
2
60
Av = +1
Output Voltage (V)
PSRR
0.04
0.02
0
-0.02
-0.04
1
Av = +2
0
-1
Av = -2
-0.06
0.1
0.01
-90
Output Voltage (V)
5MHz
-70
-90
500kHz
Gain (%)
Distortion (dBc)
5MHz
0.06
Differential Gain & Phase
10MHz
348Ω
348Ω
10
Frequency (MHz)
Po
50Ω
-50
348Ω
348Ω
-80
3rd, RL = 1kΩ
1
3rd Harmonic Distortion vs. Pout
50Ω
-65
2nd, RL = 1kΩ
-80
Phase (deg)
Distortion (dBc)
-60
Po
2nd, RL = 100Ω
-70
1000
-40
50Ω
-60
CL (pF)
Load (Ω)
-55
3rd, RL = 100Ω
Vo = 2Vpp
-50
-90
10
600
PSRR/CMRR (dB)
Maximum Output Voltage (V)
-40
2
-4
100M
Frequency (Hz)
100
0
10M
1M
100k
2nd & 3rd Harmonic Distoration
120
100
10k
Frequency (MHz)
Recommended Rs vs. Capacitive Load
4
0
0
1k
100
Phase (deg)
Magnitude (1dB/div)
Av = +2
50
CMRR
40
30
20
Av = -1
-0.08
-2
Time (5ns/div)
10
Time (5ns/div)
10k
100k
10M
1M
100M
Frequency (Hz)
3
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CLC416 Typical Performance Characteristics (Vcc = ±5V, Av = +2, Rf = 348ΩΩ, RL = 100ΩΩ; unless specified)
Equivalent Input Noise
Typical DC Errors vs. Temperature
Power Derating Curves
100
6
100
1.0
-1
IBI
3
-2
2
VIO
Inverting Current = 12pA/√Hz
10
10
Voltage = 5nV/√Hz
Non-Inverting Current = 3pA/√Hz
-3
0.8
Power (W)
4
Noise Voltage (nV/√Hz)
0
Noise Current (pA/√Hz)
IBN
Bias Current (µA)
Offset Voltage (mV)
1
5
-50
50
0
100
AJP
0.4
AJE
0.2
1
1
1
0.6
0
100
1k
10k
100k
1M
10M
0
20
Frequency (Hz)
Temperature (°C)
40
60
80
100 120 140 160 180
Ambient Temperature (°C)
CLC416 OPERATION
Description
The CLC416 is a dual current feedback amplifier with
the following features:
Feedback Resistor Selection
The feedback resistor, Rf, determines the loop gain
and frequency response of a current feedback
amplifier. Optimum performance of the CLC416, at a
gain of +2V/V, is achieved with Rf equal to 348Ω. The
frequency response plots in the typical performance
section illustrate the recommended Rf for several
gains. Within limits, Rf can be adjusted to optimize the
frequency response.
Differential gain and phase errors of 0.01%
and 0.03° into a 150Ω load
■ Low, 3.9mA, supply current per amplifier
■
The professional video quality differential gain and
phase errors and low power capabilities of the CLC416
make this product a good choice for video applications.
Decrease Rf to peak frequency response and
extend bandwidth
■ Increase Rf to roll off frequency response and
reduce bandwidth
■
Gain
The non-inverting and inverting gain equations for the
CLC416 are as follows:
Non-inverting Gain: 1+
Inverting Gain: −
As a rule of thumb, if the recommended Rf is doubled,
the bandwidth will be cut in half.
Rf
Rg
Rf
Rg
Channel Matching
Channel matching and crosstalk efficiency are largely
dependent on board layout. The layout of National’s
dual amplifier evaluation boards are designed to produce
optimum channel matching and isolation. Typical
channel matching for the CLC416 is shown in Figure 2.
Where Rf is the feedback resistor and Rg is the gain
setting resistor. Figure 1 shows the general non-inverting gain configuration including the recommended
bypass capacitors.
g
+Vcc
Channel A
+
0.1µF
Vo
CLC416
Rin
-
Rf
Channel B
Channel A
0
Channel B
-90
-180
Av = +2
RL = 100Ω
Vo = 2Vpp
RL
Phase (deg)
Vin
Magnitude (0.5dB/div)
6.8µF
-270
-360
-450
1
0.1µF
Rg
10
100
Frequency (MHz)
Figure 2: Channel Matching
6.8µF
-Vcc
The CLC416’s channel-to-channel isolation is better
than 70dB for input frequencies of 4MHz. Input
referred crosstalk vs. frequency is illustrated in Figure 3.
Figure 1: Recommended Non-Inverting Gain Circuit
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4
evaluation boards for the CLC416 (CLC730038 - DIP,
CLC730036 - SOIC) and suggests their use as a guide
for high frequency layout and as an aid for device testing and characterization.
-20
Crosstalk (dB)
-40
-60
Supply bypassing is required for best performance.
The bypass capacitors provide a low impedance return
current path at the supply pins. They also provide high
frequency filtering on the power supply traces. Other
layout factors play a major role in high frequency
performance. The following are recommended as a
basis for high frequency layout:
-80
-100
-120
1
10
100
Frequency (MHz)
1. Include 6.8µF tantalum and 0.1µF ceramic
capacitors on both supplies.
2. Place the 6.8µF capacitors within 0.75 inches
of the power pins.
3. Place the 0.1µF capacitors within 0.1 inches
of the power pins.
4. Remove the ground plane under and around
the part, especially near the input and output
pins to reduce parasitic capacitance.
5. Minimize all trace lengths to reduce series
inductances.
Figure 3: Input Referred Crosstalk vs. Frequency
Driving Cables and Capacitive Loads
When driving cables, double termination is used to
prevent reflections. For capacitive load applications, a
small series resistor at the output of the CLC416 will
improve stability. The Rs vs. Capacitive Load plot,
in the Typical Performance section, gives the
recommended series resistance value for optimum
flatness at various capacitive loads.
Power Dissipation
The power dissipation of an amplifier can be described
in two conditions:
Additional information is included in the evaluation
board literature.
Quiescent Power Dissipation PQ (No Load Condition)
■ Total Power Dissipation PT (with Load Condition)
■
SPICE Models
SPICE models provide a means to evaluate amplifier
designs. Free SPICE models are available for
National’s monolithic amplifiers that:
The following steps can be taken to determine the
power consumption for each CLC416 amplifier:
Support Berkeley SPICE 2G and its many
derivatives
■ Reproduce typical DC, AC, Transient, and
Noise performance
■ Support room temperature simulations
■
1. Determine the quiescent power
PQ = Icc (VCC - VEE)
2. Determine the RMS power at the output stage
PO = (Vcc - Vload) (Iload), where Vload and Iload
are the RMS voltage and current across the
external load.
3. Determine the total RMS power
PT = PQ + PO
The readme file that accompanies the diskette lists
released models, and provides a list of modeled parameters. The application note OA-18, Simulation
SPICE Models for National’s Op Amps, contains
schematics and a reproduction of the readme file.
Add the total RMS powers for both channels to determine the power dissipated by the dual.
Applications Circuits
The maximum power that the package can dissipate at
a given temperature is illustrated in the Power
Derating curves in the Typical Performance section.
The power derating curve for any package can be
derived by utilizing the following equation:
Instrumentation Amplifier
An instrumentation circuit is shown on the front page
and reproduced in Figure 4. The DC CMRR can be
fine tuned by adjusting R1.
V1
+
1/2
CLC416
(175° − Tamb)
P=
θ JA
348Ω
348Ω
348Ω
Vout = 3(V2 - V1)
where: Tamb = Ambient temperature (°C)
θJA = Thermal resistance, from junction to
ambient, for a given package (°C/W)
-
348Ω
348Ω
348Ω
CLC405
+
-
V2
Layout Considerations
A proper printed circuit layout is essential for achieving
high frequency performance. National provides
1/2
CLC416
+
R1
348Ω
Figure 4: Instrumentation Amplifier
5
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C
+
1/2
CLC416
R
R
R
R
1/2
CLC416
+
+Vin
R
Av = -1V/V
R
-
R
-
R
R
-
-
1/2
CLC416
R
-Vin
+
R1
Vin
+
R
1/2
CLC416
Ro Vo = 2Vin
+
C
Vo
CLC405
Av = -1V/V
-
R=
1
2πfr C
R1 = QR
Rf
Figure 5: Differential Line Receiver
Figure 6: Bandpass Filter Topology
Bandpass Filter
Figure 6 illustrates a low-sensitivity bandpass filter and
design equations. This topology utilizes the CLC416’s
closely matched amplifiers to obtain low op-amp
sensitivity at high frequencies. The CLC405 is used as
a buffer to obtain low output impedance. The overall
circuit gain is unity. For additional gain, the CLC405
can be configured as a non-inverting amplifier.
1.8dB
935kHz
0
Magnitude (dB)
CLC416
Dual Low-Power, 120MHz Op Amp
Differential Line Receiver
Figure 5 illustrates a Differential Line Receiver. The
circuit will convert differential signals to single-ended signals.
To design the filter, choose C and then determine values
for R and R1 based on the desired resonant frequency
(fr) and Q factor.
-10
-20
-30
-40
Figure 7 illustrates a bandpass filter with Q = 10 and
fr = 1MHz. The component values used are listed
below:
R1 = 4.9kΩ
R = 499Ω
C = 330pF
Rf = 2kΩ
1
10
Frequency (MHz)
Figure 7: Bandpass Response
Customer Design Applications Support
National Semiconductor is committed to design excellence. For sales, literature and technical support, call the
National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.
Life Support Policy
National’s products are not authorized for use as critical components in life support devices or systems without the express written approval
of the president of National Semiconductor Corporation. As used herein:
1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or
sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
N
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
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Tel: 1(800) 272-9959
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circuitry and specifications.
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6
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