Freescale MC100ES6210FA Low voltage 2.5/3.3 v differential ecl/pecl/hstl fanout buffer Datasheet

Freescale Semiconductor
Technical Data
Low Voltage 2.5/3.3 V Differential
ECL/PECL/HSTL Fanout Buffer
The MC100ES6210 is a bipolar monolithic differential clock fanout buffer.
Designed for most demanding clock distribution systems, the MC100ES6210
supports various applications that require to distribute precisely aligned
differential clock signals. Using SiGe technology and a fully differential
architecture, the device offers very low clock skew outputs and superior digital
signal characteristics. Target applications for this clock driver is high performance
clock distribution in computing, networking and telecommunication systems.
MC100ES6210
Rev 3, 02/2005
MC100ES6210
LOW VOLTAGE DUAL
1:5 DIFFERENTIAL PECL/ECL/HSTL
CLOCK FANOUT BUFFER
Features
•
•
•
•
•
•
•
•
•
•
•
•
Dual 1:5 differential clock distribution
30 ps maximum device skew
Fully differential architecture from input to all outputs
SiGe technology supports near-zero output skew
Supports DC to 3 GHz operation of clock or data signals
ECL/PECL compatible differential clock outputs
ECL/PECL compatible differential clock inputs
Single 3.3 V, –3.3 V, 2.5 V or –2.5 V supply
Standard 32 lead LQFP package
Industrial temperature range
Pin and function compatible to the MC100EP210
32-lead Pb-free Package Available
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
Functional Description
The MC100ES6210 is designed for low skew clock distribution systems and supports clock frequencies up to 3 GHz. The
device consists of two independent 1:5 clock fanout buffers. The input signal of each fanout buffer is distributed to five identical,
differential ECL/PECL outputs. Both CLKA and CLKB inputs can be driven by ECL/PECL compatible signals.
If VBB is connected to the CLKA or CLKB input and bypassed to GND by a 10 nF capacitor, the MC100ES6210 can be driven
by single-ended ECL/PECL signals utilizing the VBB bias voltage output.
In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even
if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts
being used on that side should be terminated.
The MC100ES6210 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the
MC100ES6210 supports positive (PECL) and negative (ECL) supplies. The is function and pin compatible to the MC100EP210.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
QA3
QA3
QA4
QB0
QB0
QB1
QB1
23
22
21
20
19
18
17
25
16
VCC
Q2
26
15
QB2
QA4
QA4
Q2
27
14
QB2
QB0
QB0
Q1
28
13
QB3
Q1
29
12
QB3
QB1
QB1
MC100ES6210
Q0
30
11
QB4
QB2
QB2
Q0
31
10
QB4
QB3
QB3
VCC
32
5
6
7
8
VEE
4
CLKB
3
CLKB
2
VBB
9
1
CLKA
CLKB
CLKB
24
VCC
CLKA
VCC
AQ4
QA2
QA2
N.C.
CLKA
CLKA
QA3
QA1
QA1
VCC
VCC
QA3
QA0
QA0
VCC
QB4
QB4
VBB
Figure 1. MC100ES6210 Logic Diagram
Figure 2. 32-Lead Package Pinout (Top View)
Table 1. Pin Configuration
Pin
I/O
Type
Function
CLKA, CLKA
Input
ECL/PECL
Differential reference clock signal input (fanout buffer A)
CLKB, CLKB
Input
ECL/PECL
Differential reference clock signal input (fanout buffer B)
QA[0-4], QA[0-4]
Output
ECL/PECL
Differential clock outputs (fanout buffer A)
QB[0-4], QB[0-4]
Output
ECL/PECL
Differential clock outputs (fanout buffer B)
VEE(1)
Supply
Negative power supply
VCC
Supply
Positive power supply. All VCC pins must be connected to the positive
power supply for correct DC and AC operation.
VBB
Output
DC
Reference voltage output for single ended ECL or PECL operation
1. In ECL mode (negative power supply mode), VEE is either –3.3 V or –2.5 V and VCC is connected to GND (0 V). In PECL mode (positive
power supply mode), VEE is connected to GND (0 V) and VCC is either +3.3 V or +2.5 V. In both modes, the input and output levels are
referenced to the most positive supply (VCC)
Table 2. Absolute Maximum Ratings(1)
Symbol
Min
Max
Unit
VCC
Supply Voltage
–0.3
3.6
V
VIN
DC Input Voltage
–0.3
VCC + 0.3
V
DC Output Voltage
–0.3
VCC + 0.3
V
DC Input Current
±20
mA
DC Output Current
±50
mA
125
°C
VOUT
IIN
IOUT
TS
Characteristics
Storage temperature
–65
Condition
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
MC100ES6210
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Table 3. General Specifications
Symbol
Characteristics
Min
Typ
Max
Unit
2(1)
VTT
Output Termination Voltage
MM
ESD Protection (Machine Model)
200
V
HBM
ESD Protection (Human Body Model)
2000
V
CDM
ESD Protection (Charged Device Model)
VCC –
Condition
V
V
LU
Latch-Up Immunity
CIN
Input Capacitance
200
θJA
Thermal Resistance Junction to Ambient
JESD 51-3, single layer test board
mA
4.0
JESD 51-6, 2S2P multilayer test board
θJC
Thermal Resistance Junction to Case
TJ
Operating Junction Temperature(2)
(continuous operation)
MTBF = 9.1 years
pF
Inputs
83.1
73.3
68.9
63.8
57.4
86.0
75.4
70.9
65.3
59.6
°C/W
°C/W
°C/W
°C/W
°C/W
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
59.0
54.4
52.5
50.4
47.8
60.6
55.7
53.8
51.5
48.8
°C/W
°C/W
°C/W
°C/W
°C/W
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
23.0
26.3
°C/W
MIL-SPEC 883E
Method 1012.1
110
°C
1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase.
2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according
to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are
specified up to 110°C junction temperature allowing the MC100ES6210 to be used in applications requiring industrial temperature range. It
is recommended that users of the MC100ES6210 employ thermal modeling analysis to assist in applying the junction temperature
specifications to their particular application.
Table 4. PECL DC Characteristics (VCC = 2.5 V ± 5% or VCC = 3.3 V ± 5%, VEE = GND, TJ = 0°C to +110°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL differential signals)
VPP
VCMR
IIN
Differential Input Voltage(1)
0.1
1.3
V
Differential operation
Differential Cross Point Voltage(2)
1.0
VCC – 0.3
V
Differential operation
±100
µA
VIN = VIL or VIN = VIH
Input
Current(1)
PECL Clock Outputs (QA0-4, QA0-4, QB0-4, QB0-4)
VOH
Output High Voltage
VOL
Output Low Voltage
VCC = 3.3 V±5%
VCC = 2.5 V±5%
VCC –1.2
VCC –1.005
VCC –0.7
V
IOH = –30 mA(3)
VCC –1.9
VCC –1.9
VCC –1.705
VCC –1.705
VCC –1.5
VCC –1.3
V
IOL = –5 mA(3)
60
100
mA
VCC –1.26
VCC –1.14
V
Supply Current and VBB
IEE
Maximum Quiescent Supply Current
without Output Termination Current
VBB
Output Reference Voltage
VCC –1.38
VEE pin
IBB = 0.2 mA
1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
3. Equivalent to a termination of 50 Ω to VTT.
MC100ES6210
Advanced Clock Drivers Devices
Freescale Semiconductor
3
Table 5. ECL DC Characteristics (VEE = –2.5 V ± 5% or VEE = –3.3 V ± 5%, VCC = GND, TJ = 0°C to +110°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
0.1
1.3
V
Differential operation
VEE + 1.0
–0.3
V
Differential operation
±100
µA
VIN = VIL or VIN = VIH
Clock Input Pair CLKA, CLKA, CLKB, CLKB (ECL differential signals)
VPP
VCMR
IIN
Differential Input Voltage(1)
Differential Cross Point
Input
Voltage(2)
Current(1)
ECL Clock Outputs (QA0–4, QA0–4, QB0–4, QB0–4)
VOH
Output High Voltage
VOL
Output Low Voltage
VCC = 3.3 V ±5%
VCC = 2.5 V ±5%
–1.2
–1.005
–0.7
V
IOH = –30 mA(3)
–1.9
–1.9
–1.705
–1.705
–1.5
–1.3
V
IOL = –5 mA(3)
60
100
mA
–1.26
–1.14
V
Supply Current and VBB
IEE
Maximum Quiescent Supply Current
without Output Termination Current
VBB
Output Reference Voltage
–1.38
VEE pin
IBB = 0.2 mA
1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
3. Equivalent to a termination of 50 Ω to VTT.
MC100ES6210
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Advanced Clock Drivers Devices
Freescale Semiconductor
Table 6. AC Characteristics (ECL: VEE = –3.3 V ± 5% or VEE = –2.5 V ± 5%, VCC = GND) or
(PECL: VCC = 3.3 V ± 5% or VCC = 2.5 V ± 5%, VEE = GND, TJ = 0°C to +110°C)(1) (2)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
0.3
1.3
V
1.2
VEE + 1.2
VCC – 0.3
–0.3 V
V
V
0
3000
MHz
Differential
350
ps
Differential
Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL or ECL differential signals)
VPP
VCMR
Differential Input Voltage(3) (peak-to-peak)
Differential Input Crosspoint Voltage
0.3
(4)
PECL
ECL
ECL Clock Outputs (Q0–9, Q0–9)
fCLK
Input Frequency
tPD
Propagation Delay
CLKA to QAx or CLKB to QBx
VO(P-P)
Differential Output Voltage (peak-to-peak)
fO < 1.1 GHz
fO < 2.5 GHz
fO < 3.0 GHz
tsk(O)
Output-to-Output Skew (per bank)
tsk(PP)
Output-to-Output Skew (part-to-part)
tJIT(CC)
Output Cycle-to-Cycle Jitter
175
260
0.45
0.35
0.20
0.70
0.55
0.35
13
(5)
tSK(P)
Output Pulse Skew
DCQ
Output Duty Cycle
tr, tf
Output Rise/Fall Time
fREF < 0.1 GHz
fREF < 1.0 GHz
49.5
45.0
50
50
30
V
V
V
30
ps
Differential
175
ps
Differential
1
ps
50
ps
50.5
55.0
%
%
DCREF = 50%
DCREF = 50%
250
ps
20% to 80%
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50 Ω to VTT.
3. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tPD and
device-to-device skew.
4. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the
VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device
propagation delay, device and part-to-part skew.
5. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |.
Differential Pulse
Generator
Z = 50 Ω
ZO = 50 Ω
RT = 50 Ω
ZO = 50 Ω
DUT
MC100ES6210
RT = 50 Ω
VTT
VTT
Figure 3. MC100ES6210 AC Test Reference
MC100ES6210
Advanced Clock Drivers Devices
Freescale Semiconductor
5
PACKAGE DIMENSIONS
4X
0.20 H
6
A-B D
D1
3
e/2
D1/2
PIN 1 INDEX
32
A, B, D
25
1
E1/2 A
F
B
6 E1
E
4
F
DETAIL G
8
17
9
7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08-mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07-mm.
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1-mm AND
0.25-mm FROM THE LEAD TIP.
4
D
4X
A-B D
H
SEATING
PLANE
DETAIL G
D
D/2
0.20 C
E/2
28X
e
32X
C
0.1 C
DETAIL AD
PLATING
BASE
METAL
b1
c
c1
b
8X
(θ1˚)
0.20
R R2
A2
5
8
C A-B D
SECTION F-F
R R1
A
M
0.25
GAUGE PLANE
A1
(S)
L
(L1)
θ˚
DETAIL AD
DIM
A
A1
A2
b
b1
c
c1
D
D1
e
E
E1
L
L1
q
q1
R1
R2
S
MILLIMETERS
MIN
MAX
1.40
1.60
0.05
0.15
1.35
1.45
0.30
0.45
0.30
0.40
0.09
0.20
0.09
0.16
9.00 BSC
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
0.50
0.70
1.00 REF
0˚
7˚
12 REF
0.08
0.20
0.08
--0.20 REF
CASE 873A-03
ISSUE B
32-LEAD LQFP PACKAGE
MC100ES6210
6
Advanced Clock Drivers Devices
Freescale Semiconductor
NOTES
MC100ES6210
Advanced Clock Drivers Devices
Freescale Semiconductor
7
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MC100ES6210
Rev. 3
02/2005
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