DSC2011FI2-F0017 Crystal-less™ Configurable Clock Generator General Description Features The DSC2011FI2-F0017 is a programmable, high performance dual LVCMOS output oscillator utilizing Micrel's proven silicon MEMS technology to provide excellent jitter and stability while incorporating additional device functionality. Two LVCMOS outputs are controlled by separate supply voltages to allow for independent voltage level control. The frequencies of the outrputs can be identical or independently derived from a common PLL frequency source. The DSC2011FI2-F0017 has provision for up to eight user-defined pre-programmed, pin-selectable output frequency combinations. The DSC2011FI2-F0017 is also equipped with independent pin-selectable output drive strengths to reduce EMI and noise. • Frequency and output formats: - LVCMOS 24/24MHz - LVCMOS 200/100MHz • Low RMS phase jitter: <1ps (typ) • ±25ppm frequency stability • -40°C to +85°C industrial temperature range • High supply noise rejection: -50dBc • Pin-selectable configurations - 2-bit output drive strength - Up to 8 output frequency combinations • Separate power supply (VDD2) for CLK2 • Excellent shock & vibration immunity - Qualified to MIL-STD-883 • High reliability - 20x better MTF than quartz oscillators • Supply range of 2.25 to 3.6V • AEC-Q100 automotive qualified • 14-pin 3.2mm x 2.5mm QFN package Applications • Consumer Electronics • Storage Area Networks - SATA, SAS, Fibre Channel • Passive Optical Networks - EPON, 10G-EPON, GPON, 10G-GPON • Ethernet - 1G, 10GBASE-T/KR/LR/SR, and FCoE • HD/SD/SDI Video & Surveillance • PCI Express • Automotive VDD/VDD2 Block Diagram O1S0/O1S1 Control Circuitry MEMS ÷2 ÷ M1 CLK1 24MHz LVCMOS ÷2 ÷ M2 CLK2 200MHz LVCMOS PLL FS0/FS1/FS2 O2S0/O2S1 OE VSS Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com April 27, 2015 2918 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. DSC2011FI2-F0017 Ordering Information Ordering Part Number Industrial Temperature Range Shipping Package DSC2011FI2-F0017 -40°C to +85°C Tube 14-pin 3.2mm x 2.5mm QFN DSC2011FI2-F0017T -40°C to +85°C Tape and Reel 14-pin 3.2mm x 2.5mm QFN VDD2 O2S1 Pin Configuration VDD Devices are Green and RoHS compliant. Sample material may have only a partial top mark. O1S1 O2S0 O1S0 GND CLK1 FS2 NC FS1 CLK2 FS0 OE 14-pin 3.2mm x 2.5mm QFN Pin Description Pin Number Pin Name Pin Type 1 OE I 2 NC 3 O2S0 I 4 GND PWR 5 FS0 I Least significant bit for frequency selection, see Table 2 for details 6 FS1 I Middle bit for frequency selection, see Table 2 for details 7 FS2 I Most significant bit for frequency selection, see Table 2 for details 8 CLK1 O LVCMOS output 9 O1S0 I Least significant bit for drive strength selection for CLK1, see Table 1 for details 10 O1S1 I Most significant bit for drive strength selection for CLK1, see Table 1 for details 11 CLK2 O LVCMOS output 12 VDD2 PWR Power supply for LVCMOS output CLK2, 1.65V to 3.6V (VDD2 ≤ VDD) 13 VDD PWR Power supply 14 O2S1 I April 27, 2015 2918 Pin Function Enables outputs when high and disables outputs when low Leave unconnected or connect to ground Least significant bit for drive strength selection for CLK2, see Table 1 for details Ground Most significant bit for drive strength selection for CLK2, see Table 1 for details 2 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. DSC2011FI2-F0017 Operational Description The DSC2011FI2-F0017 is a dual output LVCMOS oscillator consisting of a MEMS resonator and a supporting PLL IC. The two LVCMOS outputs are generated through independent 8-bit programmable dividers from the output of the internal PLL. The two constraints are imposed on the output frequencies: 1) f2 = M x f1/N, where M and N are even integers between 4 and 254, 2) 1.2GHz < N x f2 < 1.7GHz. The actual frequencies output by DSC2011FI2-F0017 are controlled by an internal pre-programmed memory (OTP). This memory stores all coefficients required by the PLL for up to eight different frequency combinations. Three control pins (FS0 - FS2) select the output frequency combination. DSC2011FI2-F0017 has independent control of the output voltage levels of the two outputs. The high voltage level of CLK1 is equal to the main supply voltage, VDD (pin 13). VDD2 (pin 12) sets the high voltage level of CLK2. VDD2 must be equal to or less than VDD at all times to insure proper operation. VDD2 can be as low as 1.65V. When OE (pin 1) is floated or connected to VDD, the DSC2011FI2-F0017 is in operational mode. Driving Enable to ground will tri-state both output drivers (hi-impedance mode). DSC2011FI2-F0017 has programmable output drive strength for each output. Using two control pins (OXS0OXS1) for each output, the drive strength can be independently adjusted to match circuit board impedances to reduce spower supply noise, overshoot/undershoot and EMI. Table 1 displays typical rise / fall times for the output with a 15pF load capacitance as a function of these control pins at VDD = 3.3V and room temperature. Output Drive Strength Bits [OXS1, OXS0] - Default is [11] 00 01 10 11 tr (ns) 1.6 1.4 1.2 1.1 tf (ns) 2.4 2.2 1.5 1.4 Table 1. Rise/Fall Times for Drive Strengths Output Clock Frequencies Frequency select bits are weakly tied high so if left unconnected the default setting will be [111] and the device will output the associated frequency highlighted in bold. Freq Select Bits [FS2, FS1, FS0] - Default is [111] Freq (MHz) 000 001 010 011 100 101 110 111 CLK1 24 NA NA NA NA NA NA 24 CLK2 100 NA NA NA NA NA NA 200 Table 2. Pin-Selectable Output Frequencies Absolute Maximum Ratings Item Min. Max. Units Supply Voltage -0.3 +4.0 V Input Voltage -0.3 VDD + 0.3 V Junction Temp - +150 °C Storage Temp -55 +150 °C Soldering Temp - +260 °C ESD HBM MM CDM - 4000 400 1500 Condition 40sec max. V 1000+ years of data retention on internal memory April 27, 2015 2918 3 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. DSC2011FI2-F0017 Specifications (Unless specified otherwise: T = 25°C, max LVCMOS drive strength) Parameter Symbol Condition Min. Typ. Supply Voltage¹ VDD VDD2 VDD2 ≤ VDD 2.25 1.65 Supply Current IDD OE pin low - outputs are disabled 21 Supply Current² IDD OE pin high - outputs are enabled CL = 15pF, F01 = F02 = 125MHz 32 Max. Units 3.6 3.6 V 23 mA mA Frequency Stability F Includes frequency variation due to initial tolerance, temp. and power supply voltage ±25 ppm Aging F First year (@ 25°C) ±5 ppm T = 25°C 5 ms 0.25 x VDD V Startup Time³ tSU Input Logic Levels Input Logic High Input Logic Low VIH VIL 4 0.75 x VDD - Output Disable Time tDA 5 ns Output Enable Time tEN 20 ns Pull-Up Resistor² Pull-up exists on all digital IO 40 kOhms LVCMOS Outputs Output Logic Levels Output Logic High Output Logic Low VOH VOL I = ±6mA Output Transition Time4 Rise Time Fall Time tR tF 20% to 80% CL = 15pF 1.1 1.4 CLK1 CLK2 [FS2, FS1, FS0] = [1, 1, 1] 24 200 Frequency Output Duty Cycle 5 0.9 x VDD - SYM 0.1 x VDD 45 Period Jitter JPER F01 = F02 = 125MHz Integrated Phase Noise JPH 200kHz to 20MHz @ 125MHz 100kHz to 20MHz @ 125MHz 12kHz to 20MHz @ 125MHz 2 2 ns MHz 55 3 0.3 0.38 1.7 V % psRMS psRMS 2 Notes: 1. Pin 12 VDD2, and pin 13 VDD should be filtered with 0.1uF capacitors. 2. Output is enabled if OE pin is floated or not connected. 3. tSU is time to 100ppm stable output frequency after VDD is applied and outputs are enabled. 4. Output Waveform and Test Circuit figures below define the parameters. 5. Period Jitter includes crosstalk from adjacent output. April 27, 2015 2918 4 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. DSC2011FI2-F0017 Nominal Performance Parameters (Unless specified otherwise: T = 25°C, VDD = 3.3V) Figure 1. LVCMOS Phase Jitter (integrated phase noise) LVCMOS Output Waveform Output OE Figure 2. LVCMOS Output Waveform MSL 1 @ 260°C refer to JSTD-020C Ramp-Up Rate (200°C to Peak Temp) 3°C/sec Max. Preheat Time 150°C to 200°C 60 - 180 sec Time maintained above 217°C 60 - 150 sec Peak Temperature 255 - 260°C Time within 5°C of actual Peak 20 - 40 sec Ramp-Down Rate 6°C/sec Max. Time 25°C to Peak Temperature 8 min Max. April 27, 2015 2918 5 Revision 1.0 [email protected] or (408) 955-1690 Micrel, Inc. DSC2011FI2-F0017 Solder Reflow Profile Figure 3. Solder Reflow Profile Package Information7 3.2mm x 2.5mm 14 Lead Plastic Package Notes: 6. Connect the exposed die paddle to ground. 7. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com. Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel's terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2015 Micrel, Incorporated. April 27, 2015 2918 6 Revision 1.0 [email protected] or (408) 955-1690