Cypress CY7C1011CV33-12ZI 2-mbit (128k x 16) static ram Datasheet

CY7C1011CV33
2-Mbit (128K x 16) Static RAM
Features
Functional Description
• Pin equivalent to CY7C1011BV33
The CY7C1011CV33 is a high-performance CMOS Static
RAM organized as 131,072 words by 16 bits.
• High speed
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
— tAA = 10 ns
• Low active power
— 360 mW (max.)
• Data Retention at 2.0
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Easy memory expansion with CE and OE features
• Available in Pb-free and non Pb-free 44-pin TSOP II,
44-pin TQFP and non Pb-free 48-ball VFBGA packages
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1011CV33 is available in a standard 44-pin TSOP
II package with center power and ground pinout, a 44-pin Thin
Plastic Quad Flatpack (TQFP), as well as a 48-ball fine-pitch
ball grid array (VFBGA) package.
Logic Block Diagram
Pin Configuration
TSOP II
Top View
128K x 16
ARRAY
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
INPUT BUFFER
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
I/O0–I/O7
I/O8–I/O15
A9
A10
A 11
A 12
A 13
A 14
A 15
A 16
COLUMN
DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document #: 38-05232 Rev. *E
•
198 Champion Court
•
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
San Jose, CA 95134-1709
•
408-943-2600
Revised October 6, 2006
[+] Feedback
CY7C1011CV33
Selection Guide
–10
–12
–15
Unit
10
12
15
ns
mA
Maximum Access Time
Maximum Operating Current
Com’l
90
85
80
Ind’l
100
95
90
10
10
10
Maximum CMOS Standby Current Com’l/Ind’l
mA
Pin Configurations
A11
A10
A9
OE
BHE
BLE
39
38
37
36
35
34
A12
40
A13
A14
A15
A16
44-pin TQFP
(Top View)
42
41
43
44
1
1
33
I/O15
I/O0
2
32
I/O14
I/O1
3
31
I/O13
I/O2
4
30
I/O12
I/O3
5
29
VSS
6
28
VCC
I/O11
CE
VCC
20
21
22
A6
A7
A8
NC
19
23
A5
11
18
I/O7
17
I/O8
A4
10
NC
I/O6
16
I/O9
A3
25
24
14
9
15
I/O5
A1
I/O10
A2
26
13
8
12
7
I/O4
WE
A0
VSS
27
48-ball VFBGA
(Top View)
Document #: 38-05232 Rev. *E
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11 NC
A7
I/O3
VCC
D
VCC
I/O12
NC
A16
I/O4
VSS
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
H
Page 2 of 11
[+] Feedback
CY7C1011CV33
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-up Current...................................................... >200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
[1]
Supply Voltage on VCC to Relative GND
DC Voltage Applied to Outputs
in High-Z State[1] ....................................–0.5V to VCC + 0.5V
.... –0.5V to +4.6V
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
3.3V ± 0.3V
DC Input Voltage[1] .................................–0.5V to VCC + 0.5V
Industrial
–40°C to +85°C
DC Electrical Characteristics Over the Operating Range
–10
Parameter
Description
Test Conditions
Min.
–12
Max.
2.4
Min.
–15
Max.
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
2.4
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
2.0
VCC
+ 0.3
2.0
VCC
+ 0.3
VIL
Input LOW Voltage[1]
–0.3
0.8
–0.3
IIX
Input Leakage Current
–1
+1
IOZ
Output Leakage Current GND < VOUT < VCC,
Output Disabled
–1
+1
ICC
VCC Operating
Supply Current
VCC = Max.,
f = fMAX = 1/tRC
ISB1
Automatic CE
Power-down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Max.
2.4
0.4
GND < VI < VCC
Min.
Unit
V
0.4
0.4
V
2.0
VCC
+ 0.3
V
0.8
–0.3
0.8
V
–1
+1
–1
+1
µA
–1
+1
–1
+1
µA
Com’l
90
85
80
mA
Ind’l
100
95
90
mA
40
40
40
mA
10
10
10
mA
Com’l/
Ind’l
Capacitance[2]
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
Max.
Unit
8
pF
8
pF
TA = 25°C, f = 1 MHz, VCC = 3.3V
Thermal Resistance[2]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
TSOP II
TQFP
VFBGA
Unit
44.56
42.66
46.98
°C/W
10.75
14.64
9.63
°C/W
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05232 Rev. *E
Page 3 of 11
[+] Feedback
CY7C1011CV33
AC Test Loads and Waveforms[3]
12-, 15-ns devices:
10-ns devices:
Z = 50Ω
50 Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
R 317Ω
3.3V
OUTPUT
OUTPUT
30 pF*
R2
351Ω
30 pF
1.5V
(b)
(a)
High-Z characteristics:
R 317Ω
3.3V
ALL INPUT PULSES
3.0V
90%
90%
GND
OUTPUT
10%
10%
(c)
Rise Time: 1 V/ns
R2
351Ω
5 pF
Fall Time: 1 V/ns
(d)
AC Switching Characteristics Over the Operating Range[4]
–10
Parameter
Description
Min.
–12
Max.
Min.
–15
Max.
Min.
Max.
Unit
Read Cycle
tpower[5]
VCC(typical) to the first access
1
tRC
Read Cycle Time
10
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low-Z
1
12
10
3
15
12
3
10
ns
15
3
12
5
0
µs
1
6
0
ns
ns
15
ns
7
ns
0
ns
OE HIGH to
High-Z[6, 7]
CE LOW to
Low-Z[7]
tHZCE
CE HIGH to
High-Z[6, 7]
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
10
12
15
ns
tDBE
Byte Enable to Data Valid
5
6
7
ns
tLZBE
Byte Enable to Low-Z
tHZBE
Byte Disable to High-Z
tHZOE
tLZCE
5
3
6
3
5
0
3
6
0
0
7
ns
ns
0
6
ns
ns
0
0
6
7
ns
7
ns
Notes:
3. AC characteristics (except High-Z) for all 10-ns parts are tested using the load conditions shown in (a). All other speeds are tested using the Thevenin load shown
in (b). High-Z characteristics are tested for all speeds using the test load shown in (d).
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
5. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
Document #: 38-05232 Rev. *E
Page 4 of 11
[+] Feedback
CY7C1011CV33
AC Switching Characteristics Over the Operating Range[4] (continued)
–10
Parameter
Description
Min.
–12
Max.
Min.
–15
Max.
Min.
Max.
Unit
[8, 9]
Write Cycle
tWC
Write Cycle Time
10
12
15
ns
tSCE
CE LOW to Write End
7
8
10
ns
tAW
Address Set-up to Write End
7
8
10
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
7
8
10
ns
tSD
Data Set-up to Write End
5
6
7
ns
tHD
Data Hold from Write End
0
0
0
ns
Low-Z[7]
tLZWE
WE HIGH to
tHZWE
WE LOW to High-Z[6, 7]
3
tBW
Byte Enable to End of Write
3
5
7
3
6
ns
7
8
10
ns
ns
Data Retention Waveform
DATA RETENTION MODE
3.0V
VCC
VDR > 2V
3.0V
tR
tCDR
CE
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
10. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.
11. WE is HIGH for read cycle.
Document #: 38-05232 Rev. *E
Page 5 of 11
[+] Feedback
CY7C1011CV33
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA OUT
tHZBE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
IICC
CC
50%
50%
IISB
SB
Write Cycle No. 1 (CE Controlled)[13, 14]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATAI/O
Notes:
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O is high-impedance if OE or BHE and/or BLE = VIH.
14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05232 Rev. *E
Page 6 of 11
[+] Feedback
CY7C1011CV33
Switching Waveforms (continued)
Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
tSA
BHE, BLE
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATAI/O
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Document #: 38-05232 Rev. *E
Page 7 of 11
[+] Feedback
CY7C1011CV33
Truth Table
CE
OE
WE
BLE
BHE
I/O0–I/O7
I/O8–I/O15
Mode
Power
H
X
X
X
X
High-Z
High-Z
Power-down
Standby (ISB)
L
L
H
L
L
Data Out
Data Out
Read All Bits
Active (ICC)
L
L
H
L
H
Data Out
High-Z
Read Lower Bits Only
Active (ICC)
L
L
H
H
L
High-Z
Data Out
Read Upper Bits Only
Active (ICC)
L
X
L
L
L
Data In
Data In
Write All Bits
Active (ICC)
L
X
L
L
H
Data In
High-Z
Write Lower Bits Only
Active (ICC)
L
X
L
H
L
High-Z
Data In
Write Upper Bits Only
Active (ICC)
L
H
H
X
X
High-Z
High-Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
10
12
15
Ordering Code
CY7C1011CV33-10ZC
CY7C1011CV33-10ZXC
CY7C1011CV33-10ZXI
CY7C1011CV33-10BVI
CY7C1011CV33-12ZC
CY7C1011CV33-12ZXC
CY7C1011CV33-12ZI
CY7C1011CV33-12ZXI
CY7C1011CV33-12AXI
CY7C1011CV33-12BVI
CY7C1011CV33-15ZXC
CY7C1011CV33-15AI
Document #: 38-05232 Rev. *E
Package
Name
51-85087
51-85150
51-85087
51-85064
51-85150
51-85087
51-85064
Package Type
44-pin TSOP II
44-pin TSOP II (Pb-Free)
44-pin TSOP II (Pb-Free)
48-ball (6 x 8 x 1 mm) VFBGA
44-pin TSOP II
44-pin TSOP II (Pb-Free)
44-pin TSOP II
44-pin TSOP II (Pb-Free)
44-pin TQFP (Pb-Free)
48-ball (6 x 8 x 1 mm) VFBGA
44-pin TSOP II (Pb-Free)
44-pin TQFP
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Page 8 of 11
[+] Feedback
CY7C1011CV33
Package Diagrams
44-Pin TSOP II (51-85087)
51-85087-*A
44-pin Thin Plastic Quad Flat Pack (51-85064)
12.00±0.25 SQ
10.00±0.10 SQ
44
34
0° MIN.
1
33
0.37±0.05
R. 0.08 MIN.
0.20 MAX.
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
GAUGE PLANE
R. 0.08 MIN.
0.20 MIN.
0-7°
0.20 MIN.
0.60±0.15
1.00 REF.
11
0.80
B.S.C.
23
DETAIL
12
A
22
NOTE:
1. JEDEC STD REF MS-026
SEATING PLANE
1.60 MAX.
12°±1°
(8X)
1.40±0.05
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.10
0.20 MAX.
51-85064-*C
SEE DETAIL
Document #: 38-05232 Rev. *E
A
Page 9 of 11
[+] Feedback
CY7C1011CV33
Package Diagrams (continued)
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW
TOP VIEW
A1 CORNER
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30±0.05(48X)
2
3
4
5
6
6
4
5
3
2
1
C
C
E
F
G
D
E
2.625
D
0.75
A
B
5.25
A
B
8.00±0.10
8.00±0.10
1
F
G
H
H
A
1.875
A
B
0.75
6.00±0.10
3.75
6.00±0.10
0.15(4X)
0.10 C
0.21±0.05
0.25 C
0.55 MAX.
B
51-85150-*D
C
1.00 MAX
0.26 MAX.
SEATING PLANE
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05232 Rev. *E
Page 10 of 11
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
CY7C1011CV33
Document History Page
Document Title: CY7C1011CV33, 2-Mbit (128K x 16) Static RAM
Document Number: 38-05232
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
117132
07/31/02
HGK
New Data Sheet
*A
118057
08/19/02
HGK
Pin configuration for 48-ball FBGA correction
*B
119702
10/11/02
DFP
Updated FBGA to VFBGA; updated package code on page 8 to BV48A.
Updated address pinouts on page 1 to A0 to A16. Updated CMOS standby
current on page 1 from 8 to 10 mA
*C
386106
See ECN
PCI
Added lead-free parts in Ordering Information Table
*D
498501
See ECN
NXR
Corrected typo in the Logic Block Diagram on page# 1
Incuded the Maximum Ratings for Static Discharge Voltage and Latch up
Current on page# 3
Changed the description of IIX from Input Load Current to
Input Leakage Current in DC Electrical Characteristics table
Updated the Ordering Information Table
*E
522620
See ECN
VKN
Added Thermal Resistance Table
Document #: 38-05232 Rev. *E
Page 11 of 11
[+] Feedback
Similar pages