ESMT M12L16161A-7TG2Q 512k x 16bit x 2bank Datasheet

ESMT
M12L16161A (2Q)
SDRAM
512K x 16Bit x 2Banks
Synchronous DRAM
FEATURES
z
z
z
z
z
z
z
z
z
GENERAL DESCRIPTION
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
CAS Latency (2 & 3 )
Burst Length (1, 2, 4, 8 & full page)
Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
32ms refresh period (2K cycle)
The M12L16161A is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the use
of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance
memory system applications.
ORDERING INFORMATION
Product ID
Max Freq.
Package
Comments
M12L16161A-5TG2Q
200MHz
TSOP(II)
Pb-free
143MHz
TSOP(II)
Pb-free
M12L16161A-7TG2Q
PIN CONFIGURATION (TOP VIEW)
(TSOPII 50L, 400milX825mil Body, 0.8mm Pin Pitch)
Elite Semiconductor Memory Technology Inc.
VDD
1
50
VSS
DQ0
2
49
DQ15
DQ1
3
48
DQ14
VSSQ
4
47
VSSQ
DQ2
5
46
DQ13
DQ3
6
45
DQ12
VDDQ
7
44
VDDQ
DQ4
8
43
DQ11
DQ5
9
42
DQ10
VSSQ
10
41
VSSQ
DQ6
11
40
DQ9
DQ7
12
39
DQ8
VDDQ
13
38
VDDQ
LDQM
14
37
N.C/RFU
WE
15
36
UDQM
CAS
16
35
CLK
RAS
17
34
CKE
CS
18
33
N.C
BA
19
32
A9
A10/AP
20
31
A8
A0
21
30
A7
A1
22
29
A6
A2
23
28
A5
A3
24
27
A4
VDD
25
26
VSS
50PIN TSOP(II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
Publication Date : Sep. 2011
Revision : 1.0
1/28
ESMT
M12L16161A (2Q)
FUNCTIONAL BLOCK DIAGRAM
512K x 16
Output Buffer
Col. Buffer
LCKE
512K x 16
Sense AMP
Row Decoder
LRAS
LCBR
ADD
Row Buffer
Refresh Counter
Address Register
CLK
Data Input Register
I/O Control
Bank Select
LWE
LDQM
DQi
Column Decoder
Latency & Burst Length
Programming Register
LRAS
LCBR
LWE
LCAS
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
PIN FUNCTION DESCRIPTION
Pin
CLK
Name
System Clock
CS
Chip Select
CKE
Clock Enable
A0 ~ A10/AP
Address
BA
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
L(U)DQM
Data Input / Output Mask
DQ0 ~ 15
VDD/VSS
Data Input / Output
Power Supply/Ground
VDDQ/VSSQ
Data Output Power/Ground
N.C/RFU
No Connection/
Reserved for Future Use
Elite Semiconductor Memory Technology Inc.
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
This pin is recommended to be left No Connection on the device.
Publication Date : Sep. 2011
Revision : 1.0
2/28
ESMT
M12L16161A (2Q)
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Voltage on any pin relative to VSS
Parameter
VIN,VOUT
-1.0 ~ 4.6
V
Voltage on VDD supply relative to VSS
VDD,VDDQ
-1.0 ~ 4.6
TA
0 ~ 70
V
TSTG
-55 ~ + 150
°C
°C
Power dissipation
PD
0.7
W
Short circuit current
IOS
50
mA
Operating ambient temperature
Storage temperature
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V)
Parameter
Supply voltage
Symbol
Min
Typ
Max
Unit
VDD,VDDQ
3.0
3.3
3.6
V
Note
Input logic high voltage
VIH
2.0
3.0
VDD+0.3
V
1
Input logic low voltage
VIL
-0.3
0
0.8
V
2
Output logic high voltage
VOH
2.4
-
-
V
IOH =-2mA
Output logic low voltage
VOL
-
-
0.4
V
IOL = 2mA
Input leakage current
IIL
-5
-
5
uA
3
Output leakage current
IOL
-5
-
5
uA
4
Note:
1.VIH (max) = 4.6V AC for pulse width ≤ 10ns acceptable.
2.VIL (min) = -1.5V AC for pulse width ≤ 10ns acceptable.
3.Any input 0V ≤ VIN ≤ VDD, all other pins are not under test = 0V.
4.Dout is disabled, 0V ≤ VOUT ≤ VDD.
CAPACITANCE (VDD = 3.3V, TA = 25 °C , f = 1MHz)
Pin
Symbol
Min
Max
Unit
CLOCK
CCLK
2.5
4.0
pF
CIN
2.5
5.0
pF
ADDRESS
CADD
2.5
5.0
pF
DQ0 ~DQ15
COUT
4.0
6.5
pF
RAS , CAS , WE , CS , CKE, LDQM,
UDQM
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
3/28
ESMT
M12L16161A (2Q)
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, VIH(min)/VIL(max)=2.0V/0.8V)
Parameter
Operating Current
(One Bank Active)
Precharge Standby
Current in power-down
mode
Precharge Standby
Current in non
power-down mode
Active Standby Current
in power-down mode
Symbol
Test Condition
CAS
Latency
Version
-5
-7
100
80
ICC1
Burst Length = 1
tRC ≥ tRC (min), tCC ≥ tCC (min), IOL= 0mA
ICC2P
CKE ≤ VIL(max), tCC =15ns
2
ICC2PS
CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞
2
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC =15ns
Input signals are changed one time during 30ns
Unit Note
mA
mA
25
mA
mA
ICC2NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
10
ICC3P
CKE ≤ VIL(max), tCC =15ns
10
ICC3PS
CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞
10
1
mA
CKE ≥ VIH(min), CS ≥ VIH(min), tCC=15ns
Active Standby Current
in non power-down
mode
(One Bank Active)
ICC3N
Input signals are changed one time during 2clks
ICC3NS
CKE ≥ VIH (min), CLK ≤ VIL(max), tCC= ∞
Input signals are stable
Operating Current
(Burst Mode)
ICC4
IOL= 0mA, Page Burst
All Band Activated, tCCD = tCCD (min)
Refresh Current
ICC5
tRFC ≥ tRFC(min)
Self Refresh Current
ICC6
CKE ≤ 0.2V
All other pins ≥ VDD-0.2V or ≤ 0.2V
25
mA
10
mA
3
100
80
2
100
80
100
80
1
mA
1
mA
2
mA
Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min).
2.Refresh period is 32ms. Addresses are changed only one time during tCC(min).
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
4/28
ESMT
M12L16161A (2Q)
AC OPERATING TEST CONDITIONS (VDD=3.3V ± 0.3V)
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4 / 0.4
1.4
tr / tf = 1 / 1
1.4
See Fig.2
Unit
V
V
ns
V
3.3V
Vtt =1.4V
1200 Ω
50
Output
VOH(DC) = 2.4V, IOH = -2mA
VOL(DC) = 0.4V, IOL = 2mA
870 Ω
Output
Z0=50
Ω
Ω
30 pF
30 pF
(Fig.2) AC Output Load Circuit
(Fig.1) DC Output Load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Version
Symbol
-5
-7
Unit
Note
Row active to row active delay
tRRD(min)
10
14
ns
1
RAS to CAS delay
tRCD(min)
15
20
ns
1
Row precharge time
tRP(min)
15
20
ns
1
tRAS(min)
30
42
ns
1
Row active time
Row cycle time
tRAS(max)
100
us
@Operating
tRC(min)
48
63
ns
1
@Auto refresh
tRFC(min)
55
63
ns
1, 5
Last data in to new col. Address delay
tCDL(min)
1
CLK
2
Last data in to row precharge
tRDL(min)
2
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. Address to col. Address delay
tCCD(min)
1
CLK
3
CAS Latency=3
2
CAS Latency=2
1
ea
4
Number of valid output data
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
5. A new command may be given tRFC after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
5/28
ESMT
M12L16161A (2Q)
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
-5
Symbol
Min
CLK cycle time
CLK to valid
output delay
CAS Latency =3
CAS Latency =2
CAS Latency =3
CAS Latency =2
tCC
tSAC
5
7
-7
Max
1000
Min
7
8.6
Unit
Note
ns
1
ns
1
Max
1000
-
4.5
-
6
-
5
-
6
Output data hold time
tOH
2
2
ns
2
CLK high pulse width
tCH
2
2
ns
3
CLK low pulse width
tCL
2
2
ns
3
Input setup time
tSS
2
2
ns
3
Input hold time
tSH
1
1
ns
3
CLK to output in Low-Z
tSLZ
1
1
ns
2
CLK to output in
Hi-Z
CAS Latency =3
CAS Latency =2
tSHZ
-
4.5
-
6
-
5
-
6
ns
*All AC parameters are measured from half to half.
Note: 1.Parameters depend on programmed CAS latency.
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3.Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the
parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
6/28
ESMT
M12L16161A (2Q)
Mode Register
BA
0
BA
X
A10
0
A10
x
A9
0
A9
1
A8
0
A8
0
A7
1
A7
0
A6
BA
A10
A9
BA
X
BA
0
A10
x
A10
0
A9
x
A9
0
A8
1
A8
1
A8
0
A7
0
A7
1
A7
0
A5
A4
A3
A2
A1
A0
A6 A5 A4 A3
LTMODE
WT
A2
A1
BL
A0
A6
JEDEC Standard Test Set (refresh counter test)
A5
Burst Read and Single Write (for Write
Through Cache)
A4
A3
A2
A1
A0
A6 A5 A4
v
v
v
A6 A5 A4
LTMODE
A3
v
A3
WT
A2
v
A2
A1
v
A1
BL
A0
v
A0
Use in future
Vender Specific
v =Valid
x =Don’t care
Mode Register Set
Burst length
Wrap type
Bit2-0
000
001
010
011
100
101
110
111
0
1
Bits6-4
Latency mode
000
001
010
011
100
101
110
111
WT=0
1
2
4
8
R
R
R
Full page
WT=1
1
2
4
8
R
R
R
R
Sequential
Interleave
CAS Latency
R
R
2
3
R
R
R
R
Remark R : Reserved
Mode Register Write Timing
CLOCK
CKE
CS
RAS
CAS
WE
A0-A10, BA
Mode Register Write
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
7/28
ESMT
M12L16161A (2Q)
Burst Length and Sequence
(Burst of Two)
Starting Address
(column address A0 binary)
0
1
Sequential Addressing
Sequence (decimal)
0,1
1,0
Interleave Addressing
Sequence (decimal)
0,1
1,0
Sequential Addressing
Sequence (decimal)
0,1,2,3
1,2,3,0
2,3,0,1
3,0,1,2
Interleave Addressing
Sequence (decimal)
0,1,2,3
1,0,3,2
2,3,0,1
3,2,1,0
(Burst of Four)
Starting Address
(column address A1-A0, binary)
00
01
10
11
(Burst of Eight)
Starting Address
(column address A2-A0, binary)
000
001
010
0 11
100
101
11 0
111
Sequential Addressing
Sequence (decimal)
0,1,2,3,4,5,6,7
1,2,3,4,5,6,7,0
2,3,4,5,6,7,0,1
3,4,5,6,7,0,1,2
4,5,6,7,0,1,2,3
5,6,7,0,1,2,3,4
6,7,0,1,2,3,4,5
7,0,1,2,3,4,5,6
Interleave Addressing
Sequence (decimal)
0,1,2,3,4,5,6,7
1,0,3,2,5,4,7,6
2,3,0,1,6,7,4,5
3,2,1,0,7,6,5,4
4,5,6,7,0,1,2,3
5,4,7,6,1,0,3,2
6,7,4,5,2,3,0,1
7,6,5,4,3,2,1,0
Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 1Mx16 device.
POWER UP SEQUENCE
1.Apply power and start clock, attempt to maintain CKE= “H”, L(U)DQM = “H” and the other pin are NOP condition at the inputs.
2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3.Issue precharge commands for all banks of the devices.
4.Issue 2 or more auto-refresh commands.
5.Issue mode register set command to initialize the mode register.
Cf.)Sequence of 4 & 5 is regardless of the order.
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
8/28
ESMT
M12L16161A (2Q)
SIMPLIFIED TRUTH TABLE
COMMAND
Register
CKEn-1 CKEn CS
Mode Register Set
Auto Refresh
Entry
Refresh
Self Refresh
H
H
X
H
L
DQM BA A10/AP A9~A0 Note
RAS
CAS
WE
L
L
L
L
X
OP CODE
L
L
L
H
X
X
H
X
L
H
X
H
H
X
H
X
V
L
H
H
X
L
H
L
H
X
L
H
L
H
X
V
Write & Column Auto Precharge Disable
Address
Auto Precharge Enable
H
X
L
H
L
L
X
V
Burst Stop
H
X
L
H
H
L
X
H
X
L
L
H
L
X
Entry
H
L
Exit
L
H
Entry
H
L
Exit
L
H
H
L
X
H
L
H
L
X
H
X
X
H
X
H
X
X
H
X
H
X
X
H
X
H
X
H
X
X
H
X
H
X
H
X
H
Exit
Bank Active & Row Addr.
Read &
Column Address
Auto Precharge Disable
Precharge
Auto Precharge Enable
Bank Selection
Both Banks
Clock Suspend or
Active Power Down
Precharge Power Down Mode
DQM
No Operation Command
H
H
H
X
H
L
X
X
1,2
3
3
3
3
X
Row Address
Column
4
Address
(A0~A7) 4,5
Column
4
Address
(A0~A7) 4,5
L
H
L
H
X
V
X
L
H
X
6
4
4
X
X
X
X
X
V
X
X
X
7
(V= Valid, X= Don’t Care, H= Logic High, L = Logic Low)
Note:
1. OP Code: Operation Code
A0~ A10/AP, BA: Program keys.(@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto / self refresh can be issued only at both banks idle state.
4. BA: Bank select address.
If “Low”: at read, write, row active and precharge, bank A is selected.
If “High”: at read, write, row active and precharge, bank B is selected.
If A10/AP is “High” at row precharge, BA ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read /write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
9/28
ESMT
M12L16161A (2Q)
Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency=3, Burst Length=1
tCH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
tCL
tCC
HIGH
CKE
tRAS
tRC
*Note1
tSH
CS
tRP
tRCD
tSS
tSH
RAS
tSS
tCCD
tSH
CAS
tSS
tSS
tSH
ADDR
Ra
Ca
Cb
*Note2
Rb
Cc
tSH
tSS
*Note2,3
BA
BS
BS
A10 /AP
Ra
*Note 3
*Note2,3
*Note2,3
BS
BS
*Note 3
*Note 3
*Note4
*Note2
BS
BS
*Note4
Rb
tRAC
tSAC
tSH
DQ
tSLZ
Qc
Db
Qa
tSS
tOH
tSH
WE
tSS
tSS
tSH
DQM
Row Active
Read
W rite
Read
Row Active
Precharge
:D on' t Care
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
10/28
ESMT
M12L16161A (2Q)
*Note: 1. All inputs expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by BA.
BA
Active & Read/Write
0
Bank A
1
Bank B
3.Enable and disable auto precharge function are controlled by A10/AP in read/write command.
A10/AP
0
1
BA
Operation
0
Disable auto precharge, leave bank A active at end of burst.
1
Disable auto precharge, leave bank B active at end of burst.
0
Enable auto precharge, precharge bank A at end of burst.
1
Enable auto precharge, precharge bank B at end of burst.
4.A10/AP and BA control bank precharge when precharge command is asserted.
A10/AP
BA
precharge
0
0
Bank A
0
1
Bank B
1
X
Both Banks
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
11/28
ESMT
M12L16161A (2Q)
Power Up Sequence
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High level is necessary
CS
tRFC
tRFC
tRP
RAS
CAS
ADDR
RAa
Key
BA
Key
A10/AP
Key
RAa
High-Z
DQ
WE
DQM
High level is necessary
Precharge
All Banks
Auto Refresh
Auto Refresh
Mode Register Set
(A-Bank)
Row Active
: Don't care
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
12/28
ESMT
M12L16161A (2Q)
Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Db2
Db3
18
19
CLOCK
HIGH
CKE
t RC
*Note1
CS
tR C D
RAS
*Note 2
CAS
ADDR
Ra
Rb
Ca0
Cb0
BA
A10 /AP
Ra
Rb
tOH
CL =2
Qa0
t R AC
QC
Qa2
Qa1
t S AC
*Note3
CL =3
t R AC
*No te3
Qa3
tO H
Qa1
Qa0
Db0
t SH Z
Qa2
t RDL
Qa3
Db0
t S HZ
t S AC
Db1
*Note4
Db1
*Note4
Db2
Db3
tRDL
WE
DQM
Row Active
(A-Ba nk )
Read
(A-B ank )
Precharge
Row Active
(A-Ban k)
(A-Ba nk )
Precharge
W ri te
(A-Ban k)
(A-Ban k)
: Don't care
*Note: 1.Minimum row cycle times is required to complete internal DRAM operation.
2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z(tSHZ) after the clock.
3.Access time from Row active command. tcc*(tRCD +CAS latency-1)+tSAC
4.Output will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
Burst can’t end in Full Page Mode.
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
13/28
ESMT
M12L16161A (2Q)
Page Read & Write Cycle at Same Bank @ Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
tRCD
RAS
*Note2
CAS
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
BA
A10/AP
Ra
tRDL
CL=2
Qa0
Qa1
Qb0
Qb1
Qb2
Dc0
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
DQ
CL=3
Dc1
Dd0
Dd2
tCDL
WE
*Note3
*Note1
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note: 1.To write data before burst read ends, DQM should be asserted three cycles prior to write command to avoid bus
contention.
2.Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
14/28
ESMT
M12L16161A (2Q)
Page Read Cycle at Different Bank @ Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
*Note1
CS
RAS
*Note2
CAS
ADDR
RAa
CAa
CAc
CBb
RBb
CBd
CAe
BA
A10/AP
RAa
RBb
CL=2
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2
QBb3
QAc0
QAc1
QBd0
QBd1
QAe0
QAe1
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2 QBb3
QAc0
QAc1
QBd0
QBd1
QAe0
DQ
CL=3
QAe1
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(B-Bank)
: Don't care
*Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going edge.
2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
15/28
ESMT
M12L16161A (2Q)
Page Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
*Note2
ADDR
RAa
CAa
CBb
RBb
CAc
CBd
BA
A10/AP
RAa
DQ
RBb
DAa0
DAa1
DAa2
DAa3
DBb0
DBb1
DBb2 DBb3
DAc0
DAc1
DBd0
tCDL
DBd1
tRDL
WE
*Note1
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
Write
(A-Bank)
Write
(B-Bank)
Precharge
(Both Banks)
Write
(A-Bank)
Write
(B-Bank)
: Don't care
*Note: 1.To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2.To interrupt burst write by row precharge, both the write and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
16/28
ESMT
M12L16161A (2Q)
Read & Write Cycle at Different Bank @ Burst Length = 4
*Note: 1.tCDL should be met to complete write.
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
17/28
ESMT
M12L16161A (2Q)
Read & Write Cycle with auto Precharge @ Burst Length =4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
Ra
Rb
Ra
Rb
Cb
Ca
BA
A10 /A P
CL= 2
Qa0
Q a1
Qa2
Q a3
Q a1
Qa2
Db0
Db1
Db2
Db3
Db0
Db1
Db2
Db3
DQ
CL=3
Q a0
Qa3
WE
DQM
Row Active
( A - Bank )
Read with
Auto Precharge
( A - Bank )
Auto Precharge
Start Point
( A - Bank)
W rite with
Auto Pr echarge
( B- Bank )
Auto Pr echarge
Star t Poin t
( B- Bank )
Row Active
( B - Bank )
:D on' t Ca re
*Note: 1.tCDL should be controlled to meet minimum tRAS before internal precharge start
(In the case of Burst Length=1 & 2 and BRSW mode)
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
18/28
ESMT
M12L16161A (2Q)
Clock Suspension & DQM Operation Cycle @ CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
BA
A10 /AP
Ra
Q a0
DQ
Qa1
Q a2
Qb0
Q a3
tSHZ
Q b1
Dc2
Dc 0
tSHZ
WE
*Note1
DQM
Row Active
Read
Clock
Suspension
Read
W rite
DQM
Read DQM
W rite
W rite
DQM
Cloc k
Sus pension
:Don't Car e
*Note: 1.DQM is needed to prevent bus contention.
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
19/28
ESMT
M12L16161A (2Q)
Read Interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length=Full page
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
BA
A10 /AP
RAa
*Note2
1
1
QAa0 QAa1 QAa2 QAa 3 QAa4
CL=2
DQ
QAb0 QAb1 QAb 2 QAb3 QAb4 QAb5
2
2
CL=3
QAa0 QAa1 QAa 2 QAa3 QAa4
WE
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
*Note1
DQM
Row Active
( A- B an k )
Read
(A- Ban k)
Burst Stop
Read
(A- Ban k)
Precharge
( A- B an k )
:Don't Care
*Note: 1.Burst can’t end in full page mode, so auto precharge can’t issue.
2.About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycle”.
3.Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
20/28
ESMT
M12L16161A (2Q)
Write Interrupted by Precharge Command & Write Burst stop Cycle @ Burst Length=Full page
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
RAS
CAS
RAa
ADDR
CAa
CAb
BA
A10 /AP
RAa
tBDL
tRDL
*Note2
DQ
DAa0 DAa1 DAa2 DAa3 DAa4
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
WE
DQM
Row Active
( A- B an k )
W rite
(A- Ban k )
Burst Stop
W rite
(A- Ban k )
Precharge
( A- B an k )
:Don't Care
*Note: 1. Burst can’t end in full page mode, so auto precharge can’t issue.
2.Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by
AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
Input data after Row precharge cycle will be masked internally.
3.Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
21/28
ESMT
M12L16161A (2Q)
Burst Read Single bit Write Cycle @ Burst Length=2
CLOCK
*Note1
HIGH
CKE
CS
RAS
*Note2
CAS
RAa
ADDR
CAa
RBb
CAb
CBc
RAc
CAd
BA
A10 /AP
RAa
RAc
RBb
CL=2
DAa0
CL= 3
DAa0
QAb0 QAb1
QAd0 QAd1
DBc0
DQ
QAb0 QAb1
QAd0 QAd1
DBc0
WE
DQM
Row Active
( A- B an k )
Row Active
(B-Bank)
W rite
(A- Ban k)
Read with
Auto Precharge
(A-Bank)
Read
( A- B an k )
Row Act ive
( A- B an k )
Precharge
( A- B an k )
W rite with
Auto Pr echarge
( B- Bank )
:Don't Care
*Note: 1.BRSW modes is enabled by setting A9 “High” at MRS(Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length.
2.When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge
command will be issued after two clock cycles.
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
22/28
ESMT
M12L16161A (2Q)
Active/Precharge Power Down Mode @ CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Q a0
Qa1
16
17
18
19
CLOCK
*Note2
tSS
CKE
tS S
*Note1
tS S
*Not e3
CS
RAS
CAS
Ra
ADDR
Ca
BA
A10 /A P
Ra
tSHZ
DQ
Qa2
WE
DQM
Pr ech ar ge
Pow er - Dow n
Entry
Row Active
Precharge
Power-Down
Exit
Active
Power-down
Entry
Read
Precharge
Active
Power-down
Exit
: Don't care
*Note: 1.Both banks should be in idle state prior to entering precharge power down mode.
2.CKE should be set high at least 1CLK+tss prior to Row active command.
3.Can not violate minimum refresh specification. (32ms)
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
23/28
ESMT
M12L16161A (2Q)
Self Refresh Entry & Exit Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
*Note2
*Note4
tRFCmin
*Note6
*Note1
*Note3
CKE
tSS
CS
*Note5
RAS
*Note7
CAS
ADDR
BA
A10/AP
Hi-Z
DQ
Hi-Z
WE
DQM
Self Refresh Entry
Self Refresh Exit
Auto Refresh
: Don't care
*Note: TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS Starts from high.
6. Minimum tRFC is required after CKE going high to complete self refresh exit.
7. 2K cycle of burst auto refresh is required immediately before self refresh entry and immediately after self refresh
exit.
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
24/28
ESMT
M12L16161A (2Q)
Mode Register Set Cycle
0
1
2
3
4
Auto Refresh Cycle
5
6
0
1
2
3
4
5
6
7
8
9
10
CLOCK
HIGH
CKE
HIGH
CS
*Note2
tRFC
RAS
*Note1
CAS
*Note3
ADDR
Key
DQ
Ra
Hi-Z
Hi-Z
WE
DQM
MRS
New Command
Auto Refresh
New Command
:Don't Care
*Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note: 1. CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register.
2.Minimum 2 clock cycles should be met before new RAS activation.
3.Please refer to Mode Register Set table.
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
25/28
ESMT
M12L16161A (2Q)
PACKAGE DIMENSIONS
50-LEAD TSOP(II) SDRAM(400mil)
26
50
C1
C
E
E1
B
B1
WITH PLATING
BASE METAL
SECTION Y-Y
1
Y Y
"A"
e
25
GAGE PLANE
D
Y
Symbol
A
A1
A2
B
B1
C
C1
D
E
E1
L
L1
e
Y
θ
Min
0.051
0.95
0.30
0.30
0.12
0.10
20.82
11.56
10.03
0.40
0
SEATING PLANE
Dimension in mm
Nom
0.127
1.00
0.35
0.127
20.95
11.76
10.16
0.50
0.80 REF
0.80 BSC
-
A
L
L1
A1
A2
θ°
DETAIL "A"
Max
1.20
0.203
1.05
0.45
0.40
0.21
0.16
21.08
11.96
10.29
0.60
Min
0.002
0.037
0.012
0.012
0.005
0.004
0.820
0.455
0.394
0.016
0.1
8
0
Dimension in inch
Nom
0.005
0.039
0.014
0.005
0.825
0.463
0.400
0.020
0.031 REF
0.031 BSC
-
Max
0.047
0.008
0.041
0.018
0.016
0.008
0.006
0.830
0.471
0.405
0.024
0.004
8
Controlling dimension : Millimeter
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
26/28
ESMT
M12L16161A (2Q)
Revision History
Revision
Date
0.1
2011.03.25
Original
1.0
2011.09.27
1. Delete “Preliminary”
2. Modify the specification of tOH
Elite Semiconductor Memory Technology Inc.
Description
Publication Date : Sep. 2011
Revision : 1.0
27/28
ESMT
M12L16161A (2Q)
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by
any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the
time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.
The information contained herein is presented only as a guide or examples
for the application of our products. No responsibility is assumed by ESMT for
any infringement of patents, copyrights, or other intellectual property rights of
third parties which may result from its use. No license, either express ,
implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure,
should be provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date : Sep. 2011
Revision : 1.0
28/28
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