ICST ICS93V857YG-125T 2.5v wide range frequency clock driver (33mhz - 233mhz) Datasheet

ICS93V857-XXX
Integrated
Circuit
Systems, Inc.
2.5V Wide Range Frequency Clock Driver (33MHz - 233MHz)
Recommended Application:
• DDR Memory Modules / Zero Delay Board Fan Out
• Provides complete DDR DIMM logic solution with
ICSSSTV16857, ICSSSTV16859 or ICSSSTV32852
Pin Configuration
Product Description/Features:
• Low skew, low jitter PLL clock driver
• 1 to 10 differential clock distribution (SSTL_2)
• Feedback pins for input to output synchronization
• PD# for power management
• Spread Spectrum tolerant inputs
• Auto PD when input signal removed
• Choice of static phase offset available,
for easy board tuning;
-XXX = device pattern number for options listed
below.
- ICS93V857-025 ...... 0ps
- ICS93V857-125 +125ps
- ICS93V857-130 .. +40ps
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS93V857-025/125/130
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
VDD
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
GND
CLKC7
CLKT7
VDD
PD#
FB_INT
FB_INC
VDD
FB_OUTC
FB_OUTT
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
48-Pin TSSOP & TVSOP
6.10 mm. Body, 0.50 mm. pitch = TSSOP
4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)
Switching Characteristics:
• Period jitter (>66MHz): <40ps
• CYCLE - CYCLE jitter (66MHz): <120ps
• CYCLE - CYCLE jitter (>100MHz): <65ps
• OUTPUT - OUTPUT skew: <60ps
• Output Rise and Fall Time: 650ps - 950ps
• DUTY CYCLE: 49.5% - 50.5%
Block Diagram
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
Functionality
Control
INPUTS
PD#
OUTPUTS
PLL State
AVDD PD#
CLK_INT
Logic
CLKT2
CLKC2
CLKT3
CLKC3
CLK_INC CLKT CLKC FB_OUTT FB_OUTC
GND
H
L
H
L
H
L
H
Bypassed/off
GND
H
H
L
H
L
H
L
Bypassed/off
2.5V
(nom)
L
L
H
Z
Z
Z
Z
off
2.5V
(nom)
L
H
L
Z
Z
Z
Z
off
2.5V
(nom)
H
L
H
L
H
L
H
on
CLKT7
CLKC7
2.5V
(nom)
H
H
L
H
L
H
L
on
CLKT8
CLKC8
2.5V
(nom)
X
Z
Z
Z
Z
off
CLKT9
CLKC9
<20MHz)(1)
0693K—03/13/03
1
CLKT4
CLKC4
FB_INT
FB_INC
CLK_INC
CLK_INT
CLKT5
CLKC5
PLL
CLKT6
CLKC6
ICS93V857-XXX
Pin Descriptions
PIN NUMBER
4, 11, 12, 15, 21,
28, 34, 38, 45,
PIN NAME
TYPE
DESCRIPTION
VDD
PWR
Power supply 2.5V
1, 7, 8, 18, 24, 25,
GND
31, 41, 42, 48
PWR
Ground
16
AVDD
PWR
Analog power supply, 2.5V
17
AGND
PWR
A n a l o g gr o u n d .
27, 29, 39, 44, 46,
CLKT(9:0)
22, 20, 10, 5, 3
OUT
"Tr ue" Clock of differential pair outputs.
26, 30, 40, 43, 47,
CLKC(9:0)
23, 19, 9, 6, 2
OUT
"Complementary" clocks of differential pair outputs.
14
CLK_INC
IN
"Complementary" reference clock input
13
CLK_INT
IN
"True" reference clock input
33
FB_OUTC
OUT
"Complementary" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC.
32
FB_OUTT
OUT
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT.
36
FB_INT
IN
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
35
FB_INC
IN
"Complementary" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error.
37
PD#
IN
Power Down. LVCMOS input
This PLL Clock Buffer is designed for a VDD of 2.5V, AVDD of 2.5V and differential data input and output levels.
ICS93V857-XXX is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT,
FB_OUTC). The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,
FB_INC), the 2.5-V LVCMOS input (PD#) and the Analog Power input (AVDD). When input (PD#) is low while power is
applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are Tri-Stated. When AVDD
is grounded, the PLL is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will enter
a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,
will detect the low frequency condition and perform the same low power features as when the (PD#) input is low. When
the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and
outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input
clock pair (CLK_INC, CLK_INT).
The PLL in ICS93V857-XXX clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT [0:9], CLKC [0:9]).
ICS93V857-XXX is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
ICS93V857-XXX is characterized for operation from 0°C to 85°C.
0693K—03/13/03
2
ICS93V857-XXX
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . .
-0.5V to 4.6V
GND - 0.5V to VDD + 0.5V
0°C to +85°C
-65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Input High Current
Input Low Current
Operating Supply
Current
Input Clamp Voltage
High-level output
voltage
Low-level output voltage
SYMBOL
I IH
I IL
IDD2.5
IDDPD
VIK
VOH
VOL
CONDITIONS
VI = VDD or GND
VI = VDD or GND
CL = 0pf @ 100MHz
CL = 0pf
VDDQ = 2.3V Iin = -18mA
IOH = -1 mA
IOH = -12 mA
IOL=1 mA
IOL=12 mA
VI = GND or V DD
VOUT = GND or VDD
CIN
Input Capacitance1
COUT
Output Capacitance1
1
Guaranteed by design at 233MHz, not 100% tested in production.
0693K—03/13/03
3
MIN
5
TYP
MAX
5
250
65
VDD - 0.1
1.7
2.45
2.10
0.05
0.35
3
3
90
-1.2
0.1
0.6
UNITS
µA
µA
mA
mA
V
V
V
V
V
pF
pF
ICS93V857-XXX
Recommended Operating Condition (see note1)
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
Supply Voltage
Low level input voltage
High level input voltage
DC input signal voltage
(note 2)
Differential input signal
voltage (note 3)
Output differential crossvoltage (note 4)
Input differential crossvoltage (note 4)
High level output current
Low level output current
High Impedance
Output Current
Operating free-air
temperature
SYMBOL
V DDQ, AVDD
VIL
VIH
CONDITIONS
MIN
2.3
CLK_INT, CLK_INC, FB_INC,
FB_INT
PD#
-0.3
CLK_INT, CLK_INC, FB_INC,
VDD/2 + 0.18
FB_INT
PD#
1.7
TYP
2.5
MAX
2.7
UNITS
V
0.4
V DD/2 - 0.18
V
0.7
V
2.1
V
V DD + 0.6
V
-0.3
V DD + 0.3
V
0.36
V DD + 0.6
V
0.7
V DD + 0.6
V
V OX
VDD/2 - 0.15
VDD/2 + 0.15
V
VIX
V DD/2 - 0.2
VDD/2 + 0.2
V
-12
12
mA
mA
±10
mA
85
°C
VIN
VID
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT
VDD/2
IOH
IOL
IOZ
VDD=2.7V, VOUT=VDD or GND
0.1
0
TA
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of VDD and is the
voltage at which the differential signal must be crossing.
0693K—03/13/03
4
ICS93V857-XXX
Timing Requirements
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
CONDITIONS
PARAMETER
SYMBOL
MIN
MAX
3
freqop
Max clock frequency
Application Frequency
Range3
Input clock duty cycle
freqApp
CLK stabilization
TSTAB
2.5V+0.2V
2.5V+0.2V
dtin
UNITS
33
233
MHz
60
170
MHz
40
60
%
100
µs
TYP
MAX
Switching Characteristics
PARAMETER
Low-to high level
propagation delay time
High-to low level propagation
delay time
Output enable time
Output disable time
Period jitter
Half-period jitter
Input clock slew rate
Output clock slew rate
Cycle to Cycle Jitter1
Phase error
Output to Output Skew
Rise Time, Fall Time
SYMBOL
CONDITION
MIN
UNITS
tPLH1
CLK_IN to any output
5.5
ns
tPHL1
CLK_IN to any output
5.5
ns
5
5
ns
ns
ps
ps
ps
v/ns
v/ns
ps
ps
ps
ps
ten
tdis
tjit (per)
tjit(hper)
t sl(I)
t sl(o)
tcyc -tcyc
t(phase error)4
t skew
t r, t f
PD# to any output
PD# to any output
66/100/125/133/167MHz
100 to <170MHz
≥170MHz to 233MHz
66/100/133/167MHz
66/100/125/133/167MHz
-40
-100
-120
1
1
-50
Load = 120Ω/16pF
650
0
40
800
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, were
the cycle (tc) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
0693K—03/13/03
5
40
100
50
4
2
60
50
60
950
ICS93V857-XXX
Parameter Measurement Information
VDD
V(CLKC)
R = 60Ω
R = 60Ω VDD /2
V(CLKC)
ICS93V857
GND
Figure 1. IBIS Model Output Load
VDD/2
C = 14 pF -VDD/2
ICS93V857
R = 10Ω
Z = 60Ω
SCOPE
Z = 50Ω
R = 50Ω
V(TT)
R = 10Ω
Z = 60Ω
Z = 50Ω
R = 50Ω
V(TT)
C = 14 pF
-VDD/2
-VDD/2
NOTE: V(TT) = GND
Figure 2. Output Load Test Circuit
YX, FB_OUTC
YX, FB_OUTT
tc(n)
tc(n+1)
tjit(cc) = tc(n) ± tc(n+1)
Figure 3. Cycle-to-Cycle Jitter
0693K—03/13/03
6
ICS93V857-XXX
Parameter Measurement Information
CLK_INC
CLK_INT
FB_INC
FB_INT
t( ) n
n=N
t( ) n
1
t( )=
N
(N is a large number of samples)
Figure 4. Static Phase Offset
YX#
YX
YX, FB_OUTC
YX, FB_OUTT
t(skew)
Figure 5. Output Skew
YX, FB_OUTC
YX, FB_OUTT
tC(n)
YX, FB_OUTC
YX, FB_OUTT
1
fO
t(jit_per) = tc(n) - 1
fO
Figure 6. Period Jitter
0693K—03/13/03
7
t ( ) n+1
ICS93V857-XXX
Parameter Measurement Information
YX, FB_OUTC
YX, FB_OUTT
t jit(hper_n+1)
t jit(hper_n)
1
fo
tjit(hper) = t jit(hper_n)
-
1
2xfO
Figure 7. Half-Period Jitter
80%
80%
VID, VOD
Clock Inputs
and Outputs
20%
20%
tslr
tslf
Figure 8. Input and Output Slew Rates
0693K—03/13/03
8
ICS93V857-XXX
c
N
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-1.20
-.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
D
8.10 BASIC
0.319 BASIC
E
E1
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
e
L
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
N
0°
8°
0°
8°
α
aaa
-0.10
-.004
L
E1
INDEX
AREA
E
1 2
D
A
A2
A1
VARIATIONS
-C-
e
N
SEATING
PLANE
b
48
aaa C
D mm.
MIN
MAX
12.40
12.60
D (inch)
MIN
.488
MAX
.496
Reference Doc.: JEDEC Publication 95, M O-153
10-0039
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
(240 mil)
Choice of static phase offset available, for easy board tuning;
-XXX = device pattern number for options listed below.
- ICS93V857-025 ...... 0ps
- ICS93V857-125 +125ps
- ICS93V857-130 .. +40ps
Ordering Information
ICS93V857yG-025T ICS93V857yG-125T ICS93V857yG-130T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
0693K—03/13/03
Prefix
ICS = Standard Device
9
ICS93V857-XXX
c
N
L
E1
INDEX
AREA
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
N
α
aaa
E
1 2
α
D
A
A2
A1
VARIATIONS
-C-
e
N
SEATING
PLANE
b
48
D mm.
MIN
9.60
D (inch)
MAX
9.80
MIN
.378
MAX
.386
Reference Doc.: JEDEC Publication 95, MO-153
aaa C
10-0037
Choice of static phase offset available, for easy board tuning;
-XXX = device pattern number for options listed below.
- ICS93V857-025 ...... 0ps
- ICS93V857-125 +125ps
- ICS93V857-130 .. +40ps
4.40 mm. Body, 0.40 mm. pitch TSSOP
(173 mil)
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
-1.20
-.047
0.05
0.15
.002
.006
0.80
1.05
.032
.041
0.13
0.23
.005
.009
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
6.40 BASIC
0.252 BASIC
4.30
4.50
.169
.177
0.40 BASIC
0.016 BASIC
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
-0.08
-.003
(16 mil)
Ordering Information
ICS93V857yL-025T ICS93V857yL-125T ICS93V857yL-130T
Example:
ICS XXXX y L - PPP - T
Designation for tape and reel packaging
Pattern Number
Package Type
L=TSSOP (TVSOP)
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS = Standard Device
0693K—03/13/03
10
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