Anpec APW7055DNC-TRL Advanced pwm and linear power controller Datasheet

APW7055
Advanced PWM and Linear Power Controller
Features
General Description
•
•
The APW7055 provides the power control and protections for two output voltages on M/B DDR applications.
It integrates one PWM controller , one source-sink
linear controller(LC) for DDR source-sink purpose, as
well as the monitor and protection functions into a
single package. The PWM controller supplies the
VMEM(2.5V) with a standard buck converter. The
source-sink linear controller regulates VTT(1.25V)
power for DDR Termination.
Operates from 5V input supply
2 Regulated Voltage are provided
− Standard Buck Switching Power for VMEM
(2.5V)
− Linear Controller with Source-Sink Regula
tion for VTT(1.25V)
•
Simple Single-Loop Control Design
− Voltage-Mode PWM Control
•
Excellent Output Voltage Regulation
Additional built-in over-voltage protection (OVP) will
be started when the VMEM output is above 115% of
the internal DAC setting(VDAC) . OVP function will shutdown the upper MOSFET and disable all output voltage . The PWM controller’s over-current function monitors the output current by sensing the voltage drop
across the upper MOSFET‘s rDS(ON) , eliminating the
need for a current sensing resistor .
− VMEM Output : VMEM ±1.5% Over Tem-per
ature
− VTT Output : 1/2 VIN ±25mV Over Temperature
•
Fast Transient Response
− Built-in Feedback Compensation
− Full 0% to 100% Duty Ratio
•
•
•
Over-Voltage and Over-Current Fault Monitors
Pin Description
Constant Frequency Operation(200kHz)
16 pins, SSOP Package
Applications
•
•
•
M/B DDR Power Regulation
AGP/PCI Graphics Power Regulation
SSTL-2 Termination
VCC
1
16
BOOT
SS
2
15
UGATE
SD
3
14
PHASE
SOURCE
4
13
PGND
SINK
5
12
MEM1
FB
6
11
MEM0
VIN
7
10
OCSET
GND
8
9
VSEN
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev.A.1 - Dec., 2001
1
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APW7055
Ordering Information
V o lt a g e C o d e
A : 2 .4 0 ~ 2 .5 5 V
B : 2 .6 0 ~ 2 .7 5 V
C : 2 .8 0 ~ 2 .9 5 V
D : 3 .0 0 ~ 3 .1 5 V
P ackage C ode
N : S S O P -1 6
Tem p. R ange
C : 0 to 7 0 ° C
H a n d lin g C o d e
TU : Tube
TR : Tape & Reel
L e a d F re e C o d e
L : L e a d F r e e D e v ic e
B la n k : O r ig in a l D e v ic e
APW 7055
L e a d F re e C o d e
H a n d lin g C o d e
Tem p. R ange
P ackage C ode
V o lt a g e C o d e
Block Diagram
VCC
SS
OCSET
200uA
VCC
OCP
PHASE
28µ A
BOOT
Power O n
Reset
G a te
C o n tro l
UG ATE
4 .5 V
PGND
OVP
SD
E .A
115%
VSEN
PW M
S o ft S ta rt a n d
F a u lt L o g ic
O s c illa t o r
SOURCE
IN H IB IT
T T L D /A
C o n v e rte r
T h e rm a l
P r o t e c t io n
M EM 0
M EM 1
V M EM
FB
S IN K
V TT
C o n tro l
GND
V TT
50%
V IN
Absolute Maximum Ratings
Symbol
VCC
VI , VO
Parameter
Supply Voltage
Input , Output or I/O Voltage
Rating
Unit
15
V
GND -0.3 V to VCC +0.3
V
TA
Operating Ambient Temperature Range
0 to 70
°C
TJ
Junction Temperature Range
0 to 125
°C
TSTG
Storage Temperature Range
-65 to +150
°C
300 ,10 seconds
°C
TS
Soldering Temperature
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.1 - Dec., 2001
2
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APW7055
Thermal Characteristics
Symbol
R JA
Parameter
Thermal Resistance in Free Air
SOIC
SOIC (with 3in2 of Copper)
Value
Unit
75
65
°C/W
Electrical Characteristics
1. Recommended operating conditions, Unless otherwise noted.
2. Refer to Block and Simplified Power System Diagrams , and Typical Application Schematic.
Symbol
Parameter
Test Conditions
Min.
APW 7055
Typ.
Max.
Unit
Supply Current
ICC
Nominal Supply Current
SD=0V, GATE Drive Open
7
Shutdown Supply Current
SD=5V
2.7
Rising VCC Threshold
Vocset=3V
4.2
Falling VCC Threshold
Vocset=3V
mA
Power-on Reset
V CC
V OCSET
V SD
4.6
V
3.6
Rising V OC SET Threshold
1.26
Shutdown Input High
Voltage
Shutdown Input Low Voltage
V
2.0
V
0.8
Oscillator
F OSC
Free Running Frequency
185
∆V OSC Ramp Am plitude
PW M Controller Reference Voltage
V DAC
DAC Voltage Accuracy
-1.5
ISource
Source Drive Current
IUGATE
R GATE
UGATE Source
+1.5
0.8
-10mV 0.495VIN +10mV
-10mV 0.505VIN +10mV
0.8
ISINK
Sink Drive Current
PW M Controllers Gate Drivers
V
A
1
V CC =5V,V UGATE =1V
3
V CC =12V, V UGATE =6V
3
3
V
1
UGATE Sink
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.1 - Dec., 2001
%
mA
0.8
V CC =5V,V BOOT =9.5V,
V UGATE =6V
V CC =12V,V BOOT =9.5V,
V UGATE =6V
kHz
V
2.0
MEM 0-1 Input Low Voltage
Source-Sink Linear Controller
V SOURCE Source Regulation Voltage
Sink Regulation Voltage
215
1.9
MEM 0-1 Input High Voltage
V SINK
200
3.5
Ω
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APW7055
Electrical Characteristics (Cont.)
1. Recommended operating conditions, Unless otherwise noted.
2. Refer to Block and Simplified Power System Diagrams , and Typical Application Schematic.
Symbol
Parameter
Test Conditions
Min.
APW7055
Typ.
Max.
Unit
Protection
VSEN O.V. trip point (VSEN/V DAC)
VSEN Rising
115
VSEN O.V. Hysteresis
IOCSET
ISS
Ocset Current Source
120
2
Vocset=3V
Soft start Current
170
200
28
230
%
uA
Functional Pin Description
VCC (Pin 1)
Provide a +5V bias supply for the IC to this pin. This
pin also provides the gate bias charge for the MOS
FETs of the source-sink regulator. The voltage at th
is pin is monitored for Power-On Reset (POR)
purposes.
upper external MOSFET as a source regulator.
SS (Pin 2)
This pin provides the soft start for the standard buck
converter and source-sink regulator. Connect a capacitor from this pin to ground.This capacitor, along
with an internal 28uA current source,sets the soft-start
interval of the converter and preventing the outputs from
overshoot as well as limiting the input current .
FB (Pin 6)
Connect this pin to output of the source-sink regulator.
This pin provide the voltage feedback path for source
and sink regulators. This pin is internally connected
to the negative input of the source controller, and also
connected to the positive input of the sink controller.
SD (Pin 3)
The pin shuts down all the outputs. A TTL-compatible,
logic level high signal applied at this pin immediately
discharges the soft-start capacitor,disabling all the
outputs.When IC re-enabled, the IC undergoes a new
soft-start cycle.Left open, this pin is pulled low by an
internal pull-down resistor,enabling operation.
VIN (Pin 7)
Connect this pin to a voltage source. Two voltages,
above 0.5VIN, are generated by an internal resistor
divider as the reference voltage of the source and sink
controllers. The internal resistor divider provides an
offset voltage to ensure higher sink regulation voltage
and prevent an direct current path through the upper
and lower MOSFETs, damaging the two MOSFETs.
SINK (Pin 5)
Connect the pin to the lower MOSFET gate drive of
the source-sink regulator.This pin is used to drive the
lower external MOSFET as a sink regulator.
SOURCE (Pin 4)
Connect the pin to the upper MOSFET gate drive of
the source-sink regulator. This pin is used to drive the
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.1 - Dec., 2001
GND (Pin 8)
Signal ground for the IC. All voltage levels are mea
sured with respect to this pin voltage protection.
4
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APW7055
Functional Pin Description (Cont.)
VSEN (Pin 9)
This pin is connected to the standard buck converter’s
output voltage to provide the voltage feedback path for
PWM converter. The OVP(Over-Voltage-Protection)
comparator circuit use this signal to monitor output
voltage status for over-voltage protection.
PGND (Pin 13)
This is the power ground connection.Tie this pin to
the anode of the flywheel diode of the standard buck
PWM converter’s circuit.
PHASE (Pin 14)
Connect the PHASE pin to the standard buck PWM
converter’s MOSFET source.This pin is used to monitor the voltage drop across the MOSFET for over-cur
rent protection.
OCSET (Pin 10)
Connect a resistor (ROCSET ) from this pin to the drain of
the standard buck PWM converter’s MOSFET. ROCSET,
an internal 200mA current source (IOCSET ), and the
MOSFET’s on-resistance(rDS(ON)) set the converter’s
over-current (OC) trip point according to the following
equation:
IPEAK =
UGATE (Pin 15)
Connect this pin to the MOSFET gate of the standard
buck PWM converter.This pin provides the gate drive
for the external MOSFET.
IO CSET x ROCSET
rDS(ON)
BOOT (Pin 16)
This pin provides bias voltage to the external MOSFET
driver. A bootstrap circuit may be used to pump a
boot voltage for enforcing the driving capability of the
gate driver and improving the performance of the
MOSFET.
An over-current trip cycles the soft-start function
.
MEM0-1 (Pin 11-12)
MEM0-1 are TTL-compatible logic level input pins of
the 2-bits DAC.The status of these 2 pins set the internal reference voltage(VDAC) for the standard buck
converter and also sets the OVP threshold voltage.Table
1 shows the DAC table voltage.
Table 1 DAC Table
APW7055 - A
Pin Name
MEM1
MEM0
APW7055 - B
Pin Name
MEM1
MEM0
VMEM
Voltage
VMEM
Voltage
0
0
2.40
0
0
2.60
0
1
2.45
0
1
2.65
1
0
2.50
1
0
2.70
1
1
2.55
1
1
2.75
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.1 - Dec., 2001
5
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APW7055
Table 1 DAC Table
APW7055 - C
Pin Name
MEM1
MEM0
APW7055 - D
Pin Name
MEM1
MEM0
VMEM
Voltage
VMEM
Voltage
0
0
2.80
0
0
3.00
0
1
2.85
0
1
3.05
1
0
2.90
1
0
3.10
1
1
2.95
1
1
3.15
Simplified Power System Diagram
V MEM
5V D U A L
Q2
Q1
S ource -S ink
LC
V TT
PW M
C ontroller
V MEM
D1
Q3
A P W 7055
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.1 - Dec., 2001
6
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APW7055
Typical Application Circuit
D4
1N 4 14 8
R1
10
C1
1u F
+5 VD U A L
1
10 k
R1 1
NC
VCC
7
VI N
O CSET
C1 3
0 .1u F
U G ATE
V MEM
P H AS E
+
VTT
4
Q 2A
A PM7 31 3
+
C8
10 00 u F
+
C1 2
10 00 u F
10
R7
0
SO U RCE
V SEN
5
Q2 B
A PM7 31 3
+
C3
10 00 u F
2u H
1k
R3
15
Q1
A PM9 41 0
0
14
V MEM
L2
4.7u H
1N 4 14 8
D5
P GN D
C1 0
1u F
R2
R1 2
C7
10 00 u F
L1
C6
2 00p F
BO O T
U1
R4
VI N
C1 4
0 .1u F
16
5 VS B
D1
B3 4
1k
13
R5
0
+
C4
10 00 u F
+
C5
10 00 u F
+
C1 7
10 00 u F
9
R6
SP ARE
S IN K APW 705 5
J2
6
FB
MEM1
MEM0
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.1 - Dec., 2001
SS
SD
3
4
2
1
3
8
2
C1 1
0 .1u F
GN D
R8
NC
12
11
7
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APW7055
Package Informaion
SSOP-16
D
N
H
G A UG E
P LA NE
E
1 2 3
A
Millimeters
1
A1
B
e
L
Variations- D
Inches
Variations- D
Dim
Min.
Max.
Variations
Min.
Max.
Dim
Min.
Max. Variations
Min.
Max.
A
1.350
1.75
SSOP-16
4.75
5.05
A
0.053
0.069
0.187
0.199
A1
0.10
0.25
A1
0.004
0.010
B
0.20
0.30
B
0.008
0.012
D
See variations
D
See variations
E
3.75
E
0.147
e
4.05
0.625 TYP.
e
0.160
0.025 TYP.
H
5.75
6.25
H
0.226
0.246
L
0.4
1.27
L
0.016
0.050
See variations
N
See variations
N
φ1
0°
φ1
8°
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.1 - Dec., 2001
8
SSOP-16
0°
8°
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APW7055
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
C ritical Zone
T L to T P
T e m p e ra tu re
R am p-up
TL
tL
T sm ax
T sm in
R am p-down
ts
Preheat
25
t 25 °C to Peak
T im e
Classificatin Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Large Body
Small Body
Average ramp-up rate
3°C/second max.
(TL to TP)
Preheat
- Temperature Min (Tsmin)
100°C
- Temperature Mix (Tsmax)
150°C
- Time (min to max)(ts)
60-120 seconds
Tsmax to TL
- Ramp-up Rate
Tsmax to TL
- Temperature(TL)
183°C
- Time (tL)
60-150 seconds
Peak Temperature(Tp)
225 +0/-5°C
240 +0/-5°C
Time within 5°C of actual Peak
10-30 seconds
10-30 seconds
Temperature(tp)
Ramp-down Rate
6°C/second max.
6 minutes max.
Time 25°C to Peak Temperature
Pb-Free Assembly
Large Body
Small Body
3°C/second max.
150°C
200°C
60-180 seconds
3°C/second max
217°C
60-150 seconds
245 +0/-5°C
250 +0/-5°C
10-30 seconds
20-40 seconds
6°C/second max.
8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface.
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.1 - Dec., 2001
9
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APW7055
Reliability test program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C , 5 SEC
1000 Hrs Bias @ 125 °C
168 Hrs, 100 % RH , 121°C
-65°C ~ 150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms , Itr > 100mA
Carrier Tape & Reel Dimensions
t
D
P
Po
E
P1
Bo
F
W
Ko
Ao
D1
T2
J
C
A
B
T1
Application
SSOP-16
A
B
D0
6.95
5.4
T
T2
W
0.3±0.05
2.2
12.0±0.3
D1
E
F
P0
P1
P2
1.75±0.1
5.5±0.05
4.0±0.1
8.0±0.1
2.0±0.05
W1
C1
C2
T1
T2
C
9.5
13±0.3
21±0.8
13.5±0.5
2.0±0.2
80±1
1.55±0.05 1.55±0.1
(mm)
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.1 - Dec., 2001
10
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APW7055
Cover Tape Dimensions
Application
SOP- 16
Carrier Width
24
Cover Tape Width
21.3
Devices Per Reel
1000
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright  ANPEC Electronics Corp. Rev. A.
Rev.A.1 - Dec., 2001
11
www.anpec.com.tw
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