TI LPV321DBVRE4 General-purpose, low-voltage, low-power,rail to rail output operational amplifier Datasheet

SLOS433I − FEBRUARY 2004 − REVISED MARCH 2005
D
D
D
D
D
D
D
D
D
D
D
2.7-V and 5-V Performance
−40°C to 125°C Specification at 5 V
No Crossover Distortion
Gain Bandwith of 152 kHz
Low Supply Current
− LPV321 . . . 9 µA
− LPV358 . . . 15 µA
− LPV324 . . . 28 µA
Rail-to-Rail Output Swing at 100-kΩ Load
− VCC+ − 3.5 mV
− VCC− + 90 mV
VICR . . . −0.2 V to VCC+ − 0.8 V
Stable With Capacitive Load of 1000 pF
Applications
− Active Filters
− General-Purpose, Low-Voltage
Applications
− Low-Power and/or Portable Applications
Latch-Up Performance Exceeds 100 mA per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
LPV321 . . . DBV OR DCK PACKAGE
(TOP VIEW)
1
IN+
VCC−
IN−
5
VCC+
4
OUTPUT
2
3
LPV358 . . . D, DDU, OR DGK PACKAGE
(TOP VIEW)
1OUT
1IN−
1IN+
VCC−
1
8
2
7
3
6
4
5
VCC+
2OUT
2IN−
2IN+
LPV324 . . . D OR PW PACKAGE
(TOP VIEW)
1OUT
1IN−
1IN+
VCC+
2IN+
2IN−
2OUT
1
14
2
13
3
12
4
11
5
10
6
9
7
8
4OUT
4IN−
4IN+
VCC−
3IN+
3IN−
3OUT
description/ordering information
The LPV321/358/324 devices are low-power (9 µA per channel at 5 V) versions of the LMV321/358/324
operational amplifiers. These are additions to the LMV321/358/324 family of commodity operational amplifiers.
The LPV321/358/324 devices are the most cost-effective solutions for applications where low voltage,
low-power operation, space saving, and low price are needed. These devices have rail-to-rail output-swing
capability, and the input common-mode voltage range includes ground. They all exhibit excellent speed-power
ratios, achieving 152 kHz of bandwidth, with a supply current of only 9 µA typical.
The LPV321, LPV358, and LPV324 are characterized for operation from −40°C to 85°C. The LPV321I,
LPV358I, and LPV324I are characterized for operation from −40°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2005, Texas Instruments Incorporated
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description/ordering information (continued)
ORDERING INFORMATION
ORDERABLE
PART NUMBER
PACKAGE†
TA
SOT23-5 (DBV)
Single
SC-70 (DCK)
SOIC-8 (D)
−40°C
−40
C to 85
85°C
C
Dual
VSSOP-8 (DDU)
VSSOP-8 (DGK)
SOIC-14 (D)
Quad
TSSOP-14 (PW)
SOT23-5 (DBV)
Single
SC-70 (DCK)
SOIC-8 (D)
−40°C
−40
C to 125
125°C
C
Dual
VSSOP-8 (DDU)
VSSOP-8 (DGK)
SOIC-14 (D)
Quad
TSSOP-14 (PW)
TOP-SIDE
MARKING
Reel of 3000
LPV321DBVR
5C7_
Reel of 250
LPV321DBVT
PREVIEW
Reel of 3000
LPV321DCKR
52_
Reel of 250
LPV321DCKT
PREVIEW
Tube of 75
LPV358D
Reel of 2500
LPV358DR
Reel of 3000
LPV358DDUR
5A56
Reel of 2500
LPV358DGKR
546
Reel of 250
LPV358DGKT
PREVIEW
Tube of 50
LPV324D
Reel of 2500
LPV324DR
Tube of 90
LPV324PW
Reel of 2000
LPV324PWR
Reel of 3000
LPV321IDBVR
5C1_
Reel of 250
LPV321IDBVT
PREVIEW
Reel of 3000
LPV321IDCKR
53_
Reel of 250
LPV321IDCKT
PREVIEW
Tube of 75
LPV358ID
Reel of 2500
LPV358IDR
Reel of 3000
LPV358IDDUR
5AE6
Reel of 2500
LPV358IDGKR
556
Reel of 250
LPV358IDGKT
PREVIEW
Tube of 50
LPV324ID
Reel of 2500
LPV324IDR
Tube of 90
LPV324IPW
Reel of 2000
LPV324IPWR
PV358
LPV324
PV324
PV358I
LPV324I
PV324I
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
‡ DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
symbol (each amplifier)
−
IN−
OUT
2
+
IN+
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LPV324 simplified schematic
VCC
VBIAS1
+
VCC
−
VBIAS2
+
Output
−
VCC VCC
VBIAS3
+
IN−
IN+
−
VBIAS4
+
−
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC+ − VCC− (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VCC
Input voltage range, VI (either input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC− to VCC+ − 1 V
Package thermal impedance, θJA (see Notes 3 and 4): 5-pin DBV package . . . . . . . . . . . . . . . . . . . 206°C/W
5-pin DCK package . . . . . . . . . . . . . . . . . . . 252°C/W
8-pin D package . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
8-pin DDU package . . . . . . . . . . . . . . . . . . TBD°C/W
8-pin DGK package . . . . . . . . . . . . . . . . . . . 172°C/W
14-pin D package . . . . . . . . . . . . . . . . . . . . . . 86°C/W
14-pin PW package . . . . . . . . . . . . . . . . . . . 113°C/W
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages and VCC specified for the measurement of IOS, are with respect to the network GND.
2. Differential voltages are at IN+ with respect to IN−.
3. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Selecting the maximum of 150°C can affect reliability.
4. The package thermal impedance is calculated in accordance with JESD 51-7.
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recommended operating conditions
MIN
VCC
TA
Supply voltage
Operating free-air temperature
MAX
2.7
5
LPV3xx
−40
85
LPV3xxI
−40
125
UNIT
V
°C
ESD protection
TEST CONDITIONS
Human-Body Model
Machine model
Charged-Device Model
4
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TYP
UNIT
2
kV
200
V
1
kV
SLOS433I − FEBRUARY 2004 − REVISED MARCH 2005
2.7-V electrical characteristics
TA = 25°C, VCC+ = 2.7 V, VCC− = 0 V, VIC = 1 V, VO = VCC+/2, and RL > 1 MΩ (unless otherwise
noted)
PARAMETER
VIO
Input offset voltage
αVIO
Average temperature
coefficient of
input offset voltage
IIB
IIO
TEST CONDITIONS
MIN
TYP†
MAX
1.2
7
UNIT
mV
mV/°C
4
Input bias current
1.7
50
nA
Input offset current
0.6
40
nA
CMRR
Common-mode
rejection ratio
0 ≤ VIC ≤ 1.7 V
50
70
dB
kSVR
Supply-voltage
rejection ratio
2.7 V ≤ VCC+ ≤ 5 V, VIC = 1 V, VO = 1 V
50
65
dB
VICR
Common-mode
input voltage range
CMRR ≥ 50 dB
0 to 1.7
−0.2 to 1.9
V
VO
Output swing
RL = 100 kΩ to 1.35 V
VCC+ − 0.100
VCC+ − 0.003
0.080
High level
Low level
LPV321
ICC
Supply current
LPV358 (both amplifiers)
LPV324 (all four amplifiers)
0.180
4
8
8
16
16
24
V
mA
SR
Slew rate‡
0.1
V/ms
GBW
Gain bandwidth product
CL = 22 pF (see Note 5)
205
kHz
Fm
Phase margin
CL = 22 pF (see Note 5)
71
deg
Gain margin
CL = 22 pF (see Note 5)
11
dB
Vn
Equivalent input
noise voltage
f = 1 kHz
178
nV/√Hz
In
Equivalent input
noise current
f = 1 kHz
0.5
pA/√Hz
† All typical values are at VCC = 2.7 V, TA = 25°C.
‡ Number specified is the slower of the positive and negative slew rates.
NOTE 5: Closed-loop gain = 18 dB, VIC = VCC+/2
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5-V electrical characteristics
TA = 25°C, VCC+ = 5 V, VCC− = 0 V, VIC = 2 V, VO = VCC+/2, and RL > 1 MΩ (unless otherwise noted)
PARAMETER
VIO
TEST CONDITIONS
Input offset voltage
TA
25°C
MIN
TYP†
MAX
1.5
7
−40°C to 85°C
10
−40°C to 125°C
11
UNIT
mV
αVIO
Average temperature
coefficient of
input offset voltage
IIB
Input bias current
CMRR
Common-mode
rejection ratio
0 ≤ VIC ≤ 4 V
25°C
50
71
dB
kSVR
Supply-voltage
rejection ratio
2.7 V ≤ VCC+ ≤ 5 V,
VIC = 1 V, VO = 1 V
25°C
50
65
dB
VICR
Common-mode
input voltage range
CMRR ≥ 50 dB
25°C
0 to 4
25°C
4
25°C
2
Input offset current
60
−40°C to 125°C
65
VO
Output swing
RL = 100 kΩ to 2.5 V
0.6
55
VCC+ − 0.100 VCC+ − 0.0035
VCC+ − 0.200
−40°C to 125°C
VCC+ − 0.225
0.090
−40°C to 85°C
IOS
Output short-circuit
current
Sinking, VO = 5 V
25°C
17
20
72
25°C
9
LPV358 (both amplifiers)
15
AV‡
Large-signal
voltage gain
RL = 100 kΩ
24
−40°C to 125°C
80
28
−40°C to 85°C
46
125
25°C
15
−40°C to 85°C
10
−40°C to 125°C
10
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mA
42
−40°C to 125°C
100
SR§
Slew rate
25°C
0.1
† All typical values are at VCC = 5 V, TA = 25°C.
‡ RL is connected to VCC−. The output voltage is 0.5 V ≤ VO ≤ 4.5 V.
§ Number specified is the slower of the positive and negative slew rates. Connected as a voltage follower with 3-V step input.
6
20
−40°C to 85°C
25°C
LPV324 (all four amplifiers)
12
40
25°C
Supply current
mA
15
−40°C to 125°C
ICC
V
0.240
2
−40°C to 85°C
LPV321
0.180
nA
0.220
−40°C to 125°C
Sourcing, VO = 0 V
40
−40°C to 125°C
−40°C to 85°C
nA
V
50
25°C
Low
level
−0.2 to 4.2
−40°C to 85°C
25°C
High
level
50
−40°C to 85°C
25°C
IIO
mV/°C
V/mV
V/ms
SLOS433I − FEBRUARY 2004 − REVISED MARCH 2005
5-V electrical characteristics
TA = 25°C, VCC+ = 5 V, VCC− = 0 V, VIC = 2 V, VO = VCC+/2, and RL > 1 MΩ (unless otherwise noted)
(continued)
PARAMETER
GBW
Gain bandwidth product
CL = 22 pF (see Note 5)
Fm
Phase margin
CL = 22 pF (see Note 5)
25°C
Gain margin
CL = 22 pF (see Note 5)
25°C
12
dB
Equivalent input noise voltage
f = 1 kHz
25°C
146
nV/√Hz
In
Equivalent input noise current
f = 1 kHz
† All typical values are at VCC = 5 V, TA = 25°C.
NOTE 5: Closed-loop gain = 18 dB, VIC = VCC+/2
25°C
0.3
pA/√Hz
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MIN
TYP†
TA
25°C
Vn
TEST CONDITIONS
MAX
UNIT
237
kHz
74
deg
7
SLOS433I − FEBRUARY 2004 − REVISED MARCH 2005
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
(LPV324 − All Channels)
INPUT BIAS CURRENT
vs
TEMPERATURE
6
25
IB, IIB − Input Bias Current − nA
ICC − Supply Current − A
30
TA = 85C
TA = 40C
TA = 25C
20
15
10
5
1
2
3
4
5
VCC+ = 5 V
VIN = VCC+/2
4
3
2
1
0
−40
0
0
5
6
−20
0
VCC+ − Supply Voltage − V
SOURCING CURRENT
vs
OUTPUT VOLTAGE
80
100
1K
100
IO − Source Current − mA
IO − Source Current − mA
60
SOURCING CURRENT
vs
OUTPUT VOLTAGE
1K
VCC+ = 2.7 V
10
1
0.1
0.01
0.01
0.1
1
10
100
VCC+ = 5 V
10
1
0.1
0.01
0.001
0.001
Output Voltage Referenced to V+ − V
0.01
0.1
Figure 4
POST OFFICE BOX 655303
1
Output Voltage Referenced to V+ − V
Figure 3
8
40
Figure 2
Figure 1
0.001
0.001
20
TA − Temperature − C
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SLOS433I − FEBRUARY 2004 − REVISED MARCH 2005
SINKING CURRENT
vs
OUTPUT VOLTAGE
SINKING CURRENT
vs
OUTPUT VOLTAGE
1k
1k
10
1
0.1
10
1
0.1
0.01
0.01
0.001
0.001
0.01
0.1
1
0.001
0.001
10
Figure 5
10
220
Rl Terminated to Opposing Supply Rail
RL = 10 kΩ
200
180
Negative Swing
RL = 100 kΩ
140
120
100
80
Positive Swing
RL = 10 kΩ
40
20
Input Voltage Noise − nV/Hz
Output Voltage From Supply Voltage − mV
1
INPUT VOLTAGE NOISE
vs
FREQUENCY
240
60
0.1
Figure 6
OUTPUT VOLTAGE SWING
vs
SUPPLY VOLTAGE
160
0.01
Output Voltage Referenced to GND − V
Output Voltage Referenced to GND − V
220
VCC+ = 5 V
100
VCC+ = 2.7 V
IO − Sink Current − mA
IO − Sink Current − mA
100
200
VCC+ = 2.7 V
180
160
VCC+ = 5 V
140
120
RL = 100 kΩ
0
2.5
3
3.5
4
4.5
5
5.5
100
10
100
VCC+ − Supply Voltage − V
Frequency − Hz
Figure 7
Figure 8
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1k
9
SLOS433I − FEBRUARY 2004 − REVISED MARCH 2005
INPUT CURRENT NOISE
vs
FREQUENCY
CROSSTALK REJECTION
vs
FREQUENCY
140
0.40
130
VCC+ = 2.7 V
Crosstalk Rejection − dB
0.30
0.25
0.20
VCC+ = 5 V
0.15
0.10
0.05
120
110
100
90
80
70
60
50
0.00
10
100
1k
40
100
10k
VCC+ = 5 V
RL = 100 k
AV = 1
VI = 3 VPP
1k
Frequency − Hz
10k
Figure 9
Figure 10
PSRR
vs
FREQUENCY
FREQUENCY
vs
RL
85
180
40
VCC+ = 5 V,
+PSRR
75
RL = 10 kΩ
65
VCC+ = 2.7 V
RL = 10 kΩ
RL = 100 kΩ
Phase
30
VCC+ = 2.7 V,
+PSRR
25
Gain
80
10
60
40
VCC+ = −2.7 V,
−PSRR
0
20
−5
−15
100
0
1k
10k
100k
1M
−10
1k
Frequency − Hz
10k
100k
Frequency − Hz
Figure 11
10
140
100
20
15
5
160
120
VCC+ = −5 V,
−PSRR
45
Gain − dB
PSRR − dB
55
35
100k
Frequency − Hz
Figure 12
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1M
−20
10M
Phase Margin − Deg
Input Current Noise − pA/Hz
0.35
SLOS433I − FEBRUARY 2004 − REVISED MARCH 2005
FREQUENCY RESPONSE
vs
CL
180
40
140
Gain
VCC+ = 5 V
RL = 10 kΩ
RL = 100 kΩ
10
80
60
40
0
Gain − dB
100
20
100k
20
10
CL = 22 pF
CL = 200 pF
CL = 1,000 pF
1k
SLEW RATE
vs
SUPPLY VOLTAGE
0.13
100
0.12
80
0.11
60
Gain
40
20
20
0
10
−20
VCC+ = 5.0 V
CL = 22 pF
CL = 200 pF
CL = 1,000 pF
100k
Slew Rate − V/s
120
Phase Margin − Deg
30
Gain − dB
−60
10M
1M
Figure 14
FREQUENCY RESPONSE
vs
CL
10k
100k
Frequency − Hz
Phase
−10
1k
−40
10k
Figure 13
0
−20
−10
1M
Frequency − Hz
40
80
40
Gain
0
−20
10k
100
60
20
0
1k
120
0
20
−10
CL = 22 pF
CL = 200 pF
CL = 1000 pF
30
Phase Margin − Deg
120
140
VCC+ = 2.7 V
Phase
160
Phase
30
Gain − dB
40
Phase Margin − Deg
FREQUENCY
vs
RL
0.1
0.09
0.08
Falling Edge
0.07
0.06
−40
0.05
−60
0.04
−80
1M
Positive Edge
Open Loop
VID = 100 mV
VCC+ = 5 V
0.03
2.5
3
3.5
4
4.5
5
5.5
VCC − Supply Voltage − V
Frequency − Hz
Figure 16
Figure 15
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NONINVERTING SMALL-SIGNAL PULSE RESPONSE
NONINVERTING LARGE-SIGNAL PULSE RESPONSE
0.16
3
TA = 25°C
RL = 10 kΩ
VCC = 5 V/0 V
AV = 1
2
1
0
Input − 20 mV/Div
Input − 1 V/Div
4
0.12
0.08
0.04
VI = 100 mV/0 V
0
−1
100 s/Div
−0.04
0.16
Output − 20 mV/Div
Output − 1 V/Div
4
100 s/Div
3
2
TA = 25°C
RL = 10 kΩ
VCC = 5 V/0 V
AV = 1
1
0
0.12
0.08
TA = 25°C
VCC+ = 5 V/0 V
RL = 10 kΩ
AV = 1
0.04
0
−1
100 s/Div
100 s/Div
Figure 18
Figure 17
INVERTING LARGE-SIGNAL PULSE RESPONSE
INVERTING SMALL-SIGNAL PULSE RESPONSE
Input − 20 mV/Div
Input − 1 V/Div
6
4
2
0
−2
TA = 25°C
0.08
0.04
0
−0.04
−0.08
−4
100 s/Div
TA = 25°C
AV = −5
RL = 10 kΩ Rf = 10 kΩ
VCC+ = 5 V Ri = 2 kΩ
0
−2
−4
Output − 20 mV/Div
Output − 1 V/Div
2
0.16
0.12
0.08
0
100 s/Div
TA = 25°C
RL = 10 kΩ
VCC+ = 5 V
AV = −5
Rf = 10 kΩ
Ri = 2 kΩ
0.04
100 s/Div
Figure 20
Figure 19
12
100 s/Div
0.20
6
4
TA = 25 C
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
LPV321DBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV321DBVRE4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV321DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV321DCKRE4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV321IDBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV321IDBVRE4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV321IDCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV321IDCKRE4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV324D
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV324DE4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV324DR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV324DRE4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV324ID
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV324IDE4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV324IDR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV324IDRE4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV324IPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV324IPWE4
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV324IPWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV324IPWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV324IPWRE4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV324IPWRG4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV324PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV324PWE4
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV324PWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 1
Lead/Ball Finish
MSL Peak Temp (3)
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
LPV324PWRE4
ACTIVE
TSSOP
PW
14
LPV358D
ACTIVE
SOIC
D
8
LPV358DDUR
ACTIVE
VSSOP
DDU
LPV358DDURE4
ACTIVE
VSSOP
LPV358DE4
ACTIVE
LPV358DGKR
2000 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DDU
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOIC
D
8
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV358DGKRG4
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV358DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV358DRE4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV358ID
ACTIVE
SOIC
D
8
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV358IDDUR
ACTIVE
VSSOP
DDU
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV358IDDURE4
ACTIVE
VSSOP
DDU
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV358IDE4
ACTIVE
SOIC
D
8
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV358IDGKR
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV358IDGKRG4
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV358IDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LPV358IDRE4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
75
75
75
75
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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