Samsung CXB1828ER 2.5gbps laser diode driver Datasheet

CXB1828ER
2.5Gbps Laser Diode Driver
Description
The CXB1828ER is a high-speed monolithic laser
diode driver. This IC can drive the data rate of 2.5Gbps
and the modulation current of up to 50mA. The bias
current of up to 50mA can be supplied and it is
controlled by the built-in APC (automatic power
control). The modulation current and bias current are
designed to be linearly controlled by the voltage input
to the control pin.
This IC has a built-in DFF, and through mode or DFF
mode can be selected. In through mode the signal
goes as it is, and in DFF mode the input signal is
retimed by the external clock. The data input pin and
the clock input pin can accept the differential input of
PECL and CML, and the 50Ω termination resistors are
provided in the IC.
The shutdown function which shuts down the
modulation current and bias current, the activity error
detect circuit which detects that the signal has no
input, and the alarm output power-on reset circuit.
Furthermore, the duty cycle control circuit which
corrects the modulation output signal duty is
included in this IC.
The CXB1828ER employs the 4.8mm × 4.8mm
of 32-pin plastic package, contributing to the
miniaturization of the optical mode.
Features
• Direct laser diode drive
• Maximum data rate of 2.5Gbps
• Power-on reset function
• Automatic power control (APC) for bias current
• Alarm function and shutdown function
• Differential PECL and CML inputs or AC coupled
input
• Internal duty cycle correction circuit
• Activity error detector function for laser safety
• Typical rise time is 80ps.
• Built-in 50Ω input termination resistor
• Compact package size: 4.8mm × 4.8mm
• Single +3.3V supply voltage
32 pin VQFN (Plastic)
Absolute Maximum Ratings
• Supply voltage
Vcc – VEE
–0.3 to +6.0 V
• Data and clock input voltage difference
|VD – VDN|
2.5
V
• Bias output current
100
mA
• Modulation output current
100
mA
• Storage temperature
Tstg
–65 to +150 °C
Recommended Operating Conditions
• Supply voltage
Vcc – VEE
3.14 to 3.46
• Operating ambient temperature
Ta
–40 to +85
V
°C
Important Notes
The IC requires SLOW turning power on and off.
See Vcc rise and fall time in AC characteristics.
Electrostatic Strength
This IC has a very sensitive electrostatic strength,
so care should be taken for handling.
Typical Transmit Block Diagram
Transmit Path
Sony
CXB1828ER
Applications
• Gigabit ethernet: 1.25Gbps
• SONET/SDH: 622Mbps, 2.5Gbps
Sony
SerDes
Laser Diode
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01Y22A2Z-PS
BIAS_MON
DUTY
THRUMODE
Block Diagram
MOD_MON
CXB1828ER
Vcc – 1.4V
QB
10kΩ
DIN
Q
50Ω
1
MUX
0
50Ω
DINB
Duty
Control
Vcc – 1.4V
10kΩ
D
CKIN
Q
50:1
50Ω
kill
Q
50Ω
CKINB
Activity Error
Detector
BIAS
AED_CAP
50:1
AED_DISABLE
kill
1.8V
WCVH
High
S
Vref Gen.
WCVL
Q
BIAS_SET
4kΩ
Low
0.3V
Vcc
Voltage Error
Det.
R
Time
Stretcher
Q
OP_OUT
Vref 1.1V
OP_IN
to Modulation/Bias Control
TIME_CAP
SHUTDOWN
SHUTDOWNB
60kΩ
BIAS_MON
MOD_MON
AED_CAP
TIME_CAP
THRUMODE
VEE2
DUTY
Pin Assignment
AED_DISABLE
RREF
ALARM
15kΩ
24 23 22 21 20 19 18 17
DIN 25
16 VCCO
DINB 26
15 QB
VEE1 27
14 Q
VCC1 28
13 VEEO1
CKIN 29
12 VEEO2
CKINB 30
11 BIAS
WCVH 31
10 OP_IN
2
3
4
5
6
7
8
VCC2
SHUTDOWN
ALARM
RREF
VREF
MOD_SET
BIAS_SET
9
1
SHUTDOWNB
WCVL 32
–2–
OP_OUT
Vref
Gen 1.9V
VREF
MOD_SET
CXB1828ER
Pin Description
Pin
No.
1
2
Symbol
Vcc2
SHUTDOWNB
Typical pin
voltage (V) I/O
DC
Description
Equivalent circuit
3.3
0 or Vcc
Positive power supply.
TTL input.
The modulation current and bias
current is shut down by inputting
the Low voltage to this pin. High
level when open.
Vcc2
I
10kΩ
2
10kΩ
3
3
SHUTDOWN
0 or Vcc
I
TTL input.
The modulation current and bias
current is shut down by inputting
the High voltage to this pin. High
level when left open.
VEE2
Vcc2
4
ALARM
TTL output.
High when the abnomality is
detected from the OP_IN pin
voltage. The abnormal voltage of
OP_IN is Vop < 0.3V or Vop > 1.8V.
4
O
VEE2
Vcc2
5
5
Connect an external resistor of
18kΩ between this pin and Vcc.
RREF
VEE2
–3–
CXB1828ER
Pin
No.
Symbol
Typical pin
voltage (V) I/O
DC
Equivalent circuit
Description
Vcc2
6
VREF
1.9
Reference voltage output.
GND reference 1.9V.
6
O
26.4KΩ
VEE2
Vcc2
7
MOD_SET
0.2 to 2.0
Modulation current control.
The modulation current is
controlled by this pin voltage.
I
7
8
8
BIAS_SET
0.2 to 2.0
Bias current control.
The bias current is controlled by
the voltage of this pin.
I
VEE2
Vcc2
150kΩ
9
OP_OUT
4kΩ
9
O
Internal operational amplifier
output.
Used for the bias current
automatic power control (APC).
The OP_OUT pin is connected to
the BIAS_SET pin. Connect a
0.1µF capacitor between this pin
and GND.
VEE2
Vcc2
The internal operational amplifier
input for the bias current automatic
power control (APC).
10
10
OP_IN
0.3 to 1.8
I
VEE2
–4–
CXB1828ER
Pin
No.
Symbol
Typical pin
voltage (V) I/O
DC
Equivalent circuit
Description
VCC1
11
11
BIAS
O
Laser bias current output.
Current
Source
VEEO2
12
VEEO2
0
Negative power supply for the
modulation and bias output.
13
VEEO1
0
Negative power supply for the
modulation output.
VCCO
14
14
Q
O
15
QB
O
15
Current
Source
VEEO1
16
VccO
VEEO1
BIAS_MON
Complementary current output.
Connect the laser diode not to this
pin, but to the Q pin.
Positive power supply for the
modulation output.
3.3
VCC1
17
Laser modulation current output.
Open collector output.
O
17
Bias current monitor.
1/50 of the bias current flows
to this pin. This pin is connected to
Vcc either through a resistor 1kΩ
or directly.
18
Current
Source
18
MOD_MON
O
VEE1 (MOD_MON)
VEEO2 (BIAS_MON)
–5–
Modulation current monitor.
1/50 of the modulation current
flows to this pin. This pin is
connected to Vcc either through a
resistor 1kΩ or directly.
CXB1828ER
Pin
No.
Symbol
Typical pin
voltage (V) I/O
DC
Equivalent circuit
Description
Vcc2
30pF
19
19
AED_CAP
500Ω
Capacitor connection for the
activity error detector. If the active
detector function is not required,
this pin can be left open.
When a capacitor is connected
between the AED_CAP pin and
Vcc, the time till the error is
detected can be extended.
VEE2
Vcc2
20
20
TIME_CAP
500Ω
30pF
Capacitor connection for the alarm
power-on reset.
The period of the power-on reset
time is controlled by a capacitor
(recommended value is 0.01µF)
connected between the TIME_CAP
pin and GND.
If the ALARM function is not
required, this pin can be left open.
VEE2
Vcc2
10kΩ
21
10kΩ
21
AED_DISABLE
I
TTL input.
This pin controls the activity error
detector circuit.
When High (open or connected to
Vcc), the activity error detector
function is disabled. When Low
(connected to GND), the activity
error detector function is enabled.
VEE2
Vcc2
10kΩ
22
10kΩ
22
THRUMODE
I
VEE2
–6–
TTL input.
When High (open or connected to
Vcc), the input data goes not
through the D flip-flop.
When Low (connected to GND),
the serial input data goes through
the D flip-flop within the chip.
CXB1828ER
Pin
No.
Symbol
Typical pin
voltage (V) I/O
DC
Equivalent circuit
Description
Vcc1
23
DUTY
300Ω
23
300Ω
Resistor connection for the duty
cycle control.
When an external resistor is
connected between the DUTY pin
and GND, the modulation pulse
width can be expanded.
VEE1
24
VEE2
Negative power supply.
0
Vcc1
25
DIN
PECL
or
CML
26
25
50Ω
I
50Ω
10kΩ
26
Differential PECL and CML data
inputs.
These two inputs are internally
connected by 100Ω and biased by
10kΩ to Vcc – 1.4V.
DINB
VEE1
27
VEE1
0
Negative power supply.
28
Vcc1
3.3
Positive power supply.
Vcc1
29
CKIN
PECL
or
CML
30
29
50Ω
I
50Ω
10kΩ
30
Differential PECL and CML clock
inputs.
These two inputs are internally
connected by 10kΩ and biased by
10kΩ to Vcc – 1.4V.
CKINB
VEE1
Vcc2
31
WCVH
Window comparator's higher
threshold voltage for ALARM.
The default high alarm assert
voltage for the comparator is 1.8V.
1.8
31
36kΩ
VEE2
–7–
CXB1828ER
Pin
No.
Symbol
Typical pin
voltage (V) I/O
DC
Equivalent circuit
Description
Vcc2
32
WCVL
0.3
8kΩ
31
6kΩ
VEE2
–8–
Window comparator's lower
threshold voltage for ALARM.
The default low alarm assert
voltage for the comparator is 0.3V.
CXB1828ER
Electrical Characteristics
DC Characteristics
Item
(Vcc – VEE = 3.14 to 3.46V, Ta = –40 to +85°C)
Symbol
Conditions
Vcc – VEE
Min.
Typ.
Max.
Unit
3.14
3.3
3.46
V
DC power supply voltage
VDC
Supply current
(DATA THRU MODE)
ICC_THRU IQ = 0mA, IB = 0mA
62
84
mA
Supply current (D-FF MODE)
ICC_DFF
65
88
mA
Maximum modulation output
current
IQMAX
Minimum modulation output
current
IQMIN
Modulation output voltage range
VQ
Maximum bias output current
IBMAX
Minimum bias output current
IBMIN
Bias output voltage range
VB
Modulation shutdown current
IQ = 0mA, IB = 0mA
mA
50
Vcc – 2
7
mA
Vcc
V
mA
50
3
mA
Vcc
V
IQSHD
100
µA
Bias shutdown current
IBSHD
100
µA
DIN, CKIN input High voltage
(PECL)
VEIH
∗1
Vcc –
1.17
Vcc –
0.81
V
DIN, CKIN input Low voltage
(PECL)
VEIL
∗1
Vcc –
1.84
Vcc –
1.48
V
DIN, CKIN differential input
voltage (CML)
VIN
∗2
400
2000
mVp-p
Internal resistance between
DIN and DINB, CKIN and CKINB
RDI, RCK
70
130
Ω
Internal input reference voltage at
DIN, DINB, CKIN, CKINB
VEIR
TTL input High voltage
VTIH
2.0
Vcc +
0.3
V
TTL input Low voltage
VTIL
–0.3
0.8
V
TTL input current High
ITIH
5
µA
TTL input current Low
ITIL
ALARM output High voltage
VTOH
Iin = –0.4mA
2.4
Vcc
V
ALARM output Low voltage
VTOL
Iin = 2.0mA
0
0.5
V
VREF output voltage
VREF
Iout = 0 to 500µA
1.80
2.05
V
WCVH output voltage
VWH
Open voltage
1.70
2.05
V
WCVL output voltage
VWL
Open voltage
0.28
0.37
V
Vcc voltage error detect voltage
Vcc_err
2.59
3.08
V
Vcc – 2
Vcc –
1.37
V
µA
–250
∗1 Since the internal input reference voltage may become lower than the Low level of ECL, input the signal
into DIN and CKIN by AC coupling at the time of a single phase input.
–9–
CXB1828ER
∗2
Min.: 200mV for each input
Max.: 1000mV for each input
VIN
AC Characteristics
(Vcc – VEE = 3.14 to 3.46V, Ta = –40 to +85°C)
Item
Symbol
Conditions
Min.
Typ.
Max.
Unit
2.488
Gbps
100
ps
Maximum data rate
fdmax
Maximum variable High pulse width
by duty cycle control
tdelay
Data rate = 2.5Gbps
IQ = 50mA, RL = 25Ω
80
ps
Fall time (80 to 20%)
tr
tf
IQ = 50mA, RL = 25Ω
90
ps
DIN – CKIN setup time
ts
Rise and fall time of
input = 130ps∗3
30
ps
DIN – CKIN hold time
th
Rise and fall time of
input = 130ps∗3
50
ps
Vcc rise time
tvccr
tvccf
10 to 90%
5
ms
90 to 10%
5
ms
Rise time (20 to 80%)
Vcc fall time
∗3
DIN
ts
CKIN
th
Setup time, Hold time
DC/AC Characteristics for the APC Circuit
Item
Symbol
OP_IN input voltage range
VI_OP
OP_OUT output maximum voltage
VO_OPMAX
OP_OUT output minimum voltage
VO_OPMIN
Minimum OP_OUT output voltage
at shutdown condition
VO_OPSDN
OP_IN input current
II_OP
OP_OUT output source current
(Vcc – VEE = 3.14 to 3.46V, Ta = –40 to +85°C)
Conditions
Min.
Typ.
Max.
Unit
V
Fig. 15
2.0
V
V
0.2
0.2
V
1
µA
IO_OPSORC
4
µA
OP_OUT output sink current
IO_OPSINK
4
µA
APC operational amplifier gain
AV
Monitor photodiode current range
IMPD
–2.0
dB
12
10
– 10 –
1000
µA
CXB1828ER
Functional Block Description
APC (Automatic power control)
The APC loop consists of the laser driver and APC operational amplifier. The APC operational amplifier is
configured as an inverting integrator. It is the input voltage that is derived from the monitor current by the
monitor photodiode and an external resistor RPD to OP_IN.
The input voltage is inverted and the output from OP_OUT. The bias current is controlled by inputting the
output to the BIAS_SET pin. The bias current is set by RPD. A capacitor CPD with a value of 1000pF works for
stability and reduces the noise. Use CAPC (recommended value 0.1µF) between the OP_OUT pin and VEE.
CAPC controls the rapid rise of the OP_OUT pin when the shutdown is cancelled, and suppresses the excess
current flowing to the laser diode.
Vcc
CXB1828ER
LD
CXB1828ER
Monitor PD
Modulation Current
APC Operational Amplifier
Q
Bias Current
Vref_1.1V
OP_IN
BIAS
OP_OUT
4kΩ
15kΩ
CPD
1000pF
RPD
CAPC
0.1µF
60kΩ
Fig.1. APC Function Block Diagram
Alarm function
This circuit is for the APC operation. When the input OP_IN is provided with an excess voltage or minimal
voltage, the window comparator output goes High, and this signal is latched resulting in the output of alarm
signal. The WCVH and WCVL pin voltages are the upper and the lower threshold values of the window
comparator for ALARM. The default value of WCVH is 1.8V and that of WCVL is 0.3V. If the voltage of OP_IN is
lower than WCVL or higher than WCVH, ALARM signal is asserted High. This alarm signal returns to Low only
by the Vcc power-on reset function. Power-on reset time (TTIME) is set by the external capacitor put between
the TIME_CAP pin and VEE. (Refer to Fig. 8.) It is necessary for the alarm signal output to be Low forcibly
because the excess voltage or minimal voltage may be applied to the OP_IN pin till the APC operation completes.
The recommended value of the capacitor is 0.01µF.
SHUTDOWN/SHUTDOWNB
Modulation/Bias Current OFF
Activity Error Detector
Vcc
Voltage Error
Detector
S Q
Time
Stretcher
R
Vcc < 2.9V
RS-FF
Monitor PD
ALARM
IN
Window Comparator
1.8V
OP_IN
RPD
OUT
0.3V
Vcc Voltage Error Detector
AED_DISABLE
L
SHUTDOWN
L
SHUTDOWNB
H
Vcc > 2.9V
Modulation/Bias Current OFF
APC Settling
Operational Amplifier for APC
Alarm Reset
TTIME
TIME_CAP
CTIME
0.01µF
Fig.2. Alarm Function Block Diagram
Fig.3. Timing Chart of Alarm Function
– 11 –
ALARM
ENABLE
CXB1828ER
Data input
The PECL/CML signal is input to the data buffer at a maximum data rate of 2.5Gbps. This input pin is biased
by the reference bias voltage (Vcc – 1.4V) for the AC coupling input. An on-chip 100Ω resistor is put between
the DIN and DINB pins. The data buffer has the frequency detector and input amplitude voltage detector for the
Activity Error Detector (AED).
Clock input
The PECL/CML clock is input to the clock buffer at a maximum data rate of 2.5GHz. This input pin is biased by
the reference bias voltage (Vcc – 1.4V) for the AC coupling input. An on-chip 100Ω resistor is put between the
CKIN and CKINB pins.
Signal duty cycle correction
The output pulse width can be extended as shown in Fig.9 by connecting an external resistor between the
DUTY pin and VEE, and setting its resistor value from 0Ω to 4kΩ. The output pulse width can be extended up to
100ps (min.). Short the DUTY pin to VEE when not want to vary the duty.
DUTY
23
0 to 4kΩ
Fig.4. Duty Cycle Control
10kΩ
VREF
MOD_SET
BIAS_SET
Bias current and modulation current control
The bias current and modulation current can be controlled linearly by the voltage input to the BIAS_SET and
MOD_SET pins as shown in Figs.10 and 11. The voltage applied to the BIAS_SET and MOD_SET pins can be
set by the external resistor between the VREF pin and VEE. Refer to Fig.5.
6
7
8
10kΩ
RMOD
RBIAS
Fig.5. Modulation/Bias Control
Bias current and modulation current monitor
This circuit monitors the bias and modulation current. The BIAS_MON and the MOD_MON pins should be
connected to VCC either directly or through a resistor. The modulation current and monitor current are in the
rate of approximately 50:1. (Refer to Fig.12 and Fig.13.)
Thru-mode
When this pin is High or connected to Vcc, the input data goes not through the internal flip-flop. If this pin is
grounded the input data goes through the D flip-flop.
– 12 –
CXB1828ER
Shutdown function
This circuit disables the output current, that is, the bias and modulation current is turned off and used to shut
off the laser. And the voltage of OP_OUT is set to VEE. The function block diagram for all of the shutdown
mechanism for the circuit is shown in Fig.6. The shutdown functions when one of the following conditions is met.
1) SHUTDOWN is High.
2) SHUTDOWNB is Low.
3) The activity error detector detects an error of the DIN/DINB input signal.
4) The voltage error detector detects Vcc is below 2.59 to 3.08V.∗
(∗ The bias current may flow at approximately Vcc = 2.0V.)
Modulation/Bias Current OFF,
The voltage of OP_OUT is set to VEE.
SHUTDOWN
SHUTDOWNB
Input Buffer
DIN/DINB
Activity Error
Detector
Alarm Reset
TIME_CAP
Time
Stretcher
AED_DISABLE
AED_CAP
Vcc
Voltage Error
Detector
Fig.6. Shutdown Function Block Diagram
Activity error detect function
The activity error detect circuit monitors the DIN/DINB input signal, and shuts down the output current when
this circuit determines that the input data signal has no input. The conditions where the input signal is
determined to be no signal are when the input data signal logic is not varied over a period of the time set by
the user and when the voltage swing is too small (< 100mVpp-diff). Either of these conditions is met, the
shutdown circuit is enabled and the modulation current and laser bias current are shut down.
If needed, the time till the activity error detect can be extended. Fig.14 shows the graphs of the activity error
detection time (TAED) vs. CAED. When the activity error detect function is not required, connect the AED_DISABE
pin to VCC or leave it the pin open.
Signal Loss
IN
OUT
DIN/DINB
AED_DISABLE L
Active Error Detector
TAED
Fig.7. Timing Chart of AED Function
– 13 –
CXB1828ER
DC Electrical Characteristics Measurement Circuit
24
A
A
A
23
22
21
20
19
A
A
18
17
16
25Ω
Vcc – 1.4V
15
10kΩ
A
25
A
14
50Ω
1
MUX
0
50Ω
A
26
Duty
Control
13
27
28
D
Vcc – 1.4V
Q
50:1
A
12
kill
10kΩ
Q
29
50Ω
Activity Error
Detector
50Ω
A
30
11
A
50:1
kill
1.8V
V
31
V
32
High
Vref Gen.
Low
0.3V
Vcc
Voltage Error
Det.
Time
Stretcher
S
Q
R
Q
Vref 1.1V
10
A
to Modulation/Bias Control
15kΩ
1
2
3
A
A
4
V
60kΩ
4kΩ
Vref
Gen 1.9V
9
5
6
0.4mA
or –2.0mA
V
7
8
A
A
V
0 to
500µA
18kΩ
A
3.3V
– 14 –
CXB1828ER
AC Electrical Characteristics Measurement Circuit
0 to 4kΩ
24
23
22
21
20
19
18
17
16
51Ω
25Ω
Vcc – 1.4V
0.1µF
15
Z0 = 50Ω
10kΩ
25
14
50Ω
51Ω
0.1µF
1
MUX
0
50Ω
26
Duty
Control
51Ω
13
27
D
28 Vcc – 1.4V
51Ω
0.1µF
Q
50:1
12
kill
10kΩ
Q
29
50Ω
0.1µF
Activity Error
Detector
50Ω
30
11
50:1
kill
1.8V
31
High
Vref Gen.
32
Low
0.3V
Vcc
Voltage Error
Det.
Time
Stretcher
S
Q
R
Q
Vref 1.1V
10
15kΩ
to Modulation/Bias Control
51Ω
1
2
3
4
60kΩ
4kΩ
Vref
Gen 1.9V
9
5
6
10kΩ
0 to 100kΩ
7
8
10kΩ
0 to 100kΩ
18kΩ
Oscilloscope
3.3V
– 15 –
Oscilloscope
50Ω
input
CXB1828ER
Application Circuit
BIAS_MON
MOD_MON
DUTY
THRUMODE
RDUTY
0 to 4kΩ
Laser
Diode
Monitor
Photodiode
RQB
QB
Vcc – 1.4V
10kΩ
RQ
Q
DIN
CPD
1000pF
50Ω
1
MUX
0
50Ω
DINB
RPD
Duty
Control
Vcc – 1.4V
10kΩ
D
CKIN
Ferrite
Bead
Q
50:1
50Ω
kill
Q
50Ω
Vcc
CKINB
BIAS
Activity Error
Detector
CAED
AED_CAP
50:1
AED_DISABLE
kill
1.8V
S
Vref Gen.
WCVL
BIAS_SET
CAPC
0.1µF
4kΩ
Low
0.3V
TIME_CAP
Q
Vcc
Voltage Error
Det.
Time
Stretcher
R
Q
OP_OUT
Vref 1.1V
15kΩ
to Modulation/Bias Control
CTIME
0.01µF
SHUTDOWN
SHUTDOWNB
ALARM
Vcc
18kΩ
OP_IN
60kΩ
Vref
Gen 1.9V
VREF
MOD_SET
RVREF
10kΩ
RMOD_SET
RREF
WCVH
High
RRREF
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 16 –
CXB1828ER
Example of Representative Characteristics
160
Amount of increases in pulse width time [ps]
60
50
TTIME [ms]
40
30
20
10
0
0
0.02
0.04
0.06
0.08
120
100
80
60
40
Ta = –40˚C
Ta = +40˚C
Ta = +85˚C
20
0
0.10
0
3
4
RDUTY [kΩ]
Fig. 8. Power-on reset time (TTIME) vs. CTIME
Fig. 9. Increment of output pulse width vs. RDUTY
90
80
80
70
60
Bias current [mA]
60
50
40
30
Ta = –40˚C
Ta = +40˚C
Ta = +85˚C
10
0
50
40
30
20
20
0
500
1000
1500
2000
Ta = –40˚C
Ta = +40˚C
Ta = +85˚C
10
0
2500
0
MOD_SET input voltage [mV]
Ratio of bias current and bias monitor current [mA]
70
60
50
40
30
20
0
Ta = –40˚C
Ta = +40˚C
Ta = +85˚C
0
500
1000
1500
2000
1000
1500
2000
2500
Fig. 11. Bias current vs. BIAS_SET input voltage
80
10
500
BIAS_SET input voltage [mV]
Fig. 10. Modulation current vs.
MOD_SET input voltage
Ratio of modulation current and
modulation monitor current [mA]
2
1
CTIME [µF]
70
Modulation current [mA]
140
2500
MOD_SET input voltage [mV]
80
70
60
50
40
30
20
Ta = –40˚C
Ta = +40˚C
Ta = +85˚C
10
0
0
500
1000
1500
2000
2500
BIAS_SET input voltage [mV]
Fig. 12. Ratio of modulation current (IQ)
and modulation monitor current vs.
MOD_SET input voltage
– 17 –
Fig. 13. Ratio of bias current (IB)
and bias monitor current vs.
BIAS_SET input voltage
CXB1828ER
100
80
OP_OUT output voltage [V]
TAED (AED error detection time) [µs]
90
70
60
50
40
30
20
Ta = –40˚C
Ta = +40˚C
Ta = +85˚C
10
0
0
200
400
600
800
100
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Ta = –40˚C
Ta = +40˚C
Ta = +85˚C
Vcc = 3.3V
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
CAED [pF]
OP_IN input voltage [V]
Fig. 14. Activity error detect time (TAED) vs.
CAED
Fig. 15. OP_OUT output voltage vs.
OP_IN input voltage
RL = 25Ω
Ta = 25˚C
IQ = 30mA
Pattern = PRBS23 – 1
Data Rate = 2.5Gbps
Time base: 100.0ps/div
250mV/div
Fig. 16. Electrical Output Waveform
2
FP LD (λ = 1310nm)
Ta = 25˚C
Pattern = PRBS23 – 1
Data Rate = 2.5Gbps
Filter
Mask: OC-48
1
3
Time base: 100.0ps/div
Fig. 17. Optical Output Waveform
– 18 –
CXB1828ER
0.8
Unit: mm
0.6 ± 0.2
2.3
0.
15
Foot Print
4.8
39
0.
Via hole in PWB
Package outline
VEE in PWB
VEE or solder resist in PWB 0.14
(This area is VEE in IC)
0.4
0.2
IC pin size
Foot pattern
recommended
– 19 –
CXB1828ER
Unit: mm
32PIN VQFN (PLASTIC)
0.9 ± 0.1
0.6 ± 0.1
0.05 S
4R
0.7
C
24
2.3
0.
3
4.8
4.4
17
25
16
A
B
PIN1 INDEX
9
0.
6
(0
.1
5)
4 5˚
C
8
1
9)
.3
(0
32
x4
0.4
S
1.4
0.1 S A-B C
0.05 M S A-B C
0.2 ± 0.01
0.1 S A-B C
0.23 ± 0.02
x4
0.03 ± 0.03(∗1)
(Stand Off)
Solder Plating
0.13 ± 0.025
+ 0.09
0.14 – 0.03
NOTE: 1) The dimensions of the terminal section apply to the
ranges of 0.1mm and 0.25mm from the end of a terminal.
2) The dimension of (∗1) is apply to DiePad and the lead.
TERMINAL SECTION
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.05g
SONY CODE
VQFN-32P-04
32PIN VQFN (PLASTIC)
0.9 ± 0.1
0.6 ± 0.1
3
2.3
0.05 S
0.7
4-
C
24
R
0.
4.8
4.4
17
25
16
A
B
PIN1 INDEX
9
.3
(0
45˚
0.
6
(0
.1
5)
9)
32
8
x4
0.4
S
1.4
0.1 S A-B C
0.1 S A-B C
0.05 M S A-B C
0.2 ± 0.01
0.03 ± 0.03(∗1)
(Stand Off)
x4
0.23 ± 0.02
1
C
Package Outline
Solder Plating
NOTE: 1) The dimensions of the terminal section apply to the
ranges of 0.1mm and 0.25mm from the end of a terminal.
2) The dimension of (∗1) is apply to DiePad and the lead.
0.13 ± 0.025
+ 0.09
0.14 – 0.03
TERMINAL SECTION
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.05g
SONY CODE
VQFN-32P-04
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18µm
– 20 –
Sony Corporation
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