Austin AS5LC512K8F-25L/XT 512k x 8 sram 3.3 volt high speed sram with center power pinout Datasheet

SRAM
Austin Semiconductor, Inc.
512K x 8 SRAM
AS5LC512K8
PIN ASSIGNMENT
(Top View)
3.3 VOLT HIGH SPEED SRAM with
CENTER POWER PINOUT
36-Pin PSOJ (DJ)
36-Pin CLCC (EC)
AVAILABLE AS MILITARY
SPECIFICATIONS
•MIL-STD-883 for Ceramic
•Extended Temperature Plastic (COTS)
FEATURES
• Ultra High Speed Asynchronous Operation
• Fully Static, No Clocks
• Multiple center power and ground pins for improved
noise immunity
• Easy memory expansion with CE\ and OE\
options
• All inputs and outputs are TTL-compatible
• Single +3.3V Power Supply +/- 0.3V
36-Pin Flat Pack (F)
• Data Retention Functionality Testing
• Cost Efficient Plastic Packaging
• Extended Testing Over -55ºC to +125ºC for plastics
OPTIONS
MARKING
• Timing
12ns access
15ns access
20ns access
25ns access
-12
-15
-20
-25
• Operating Temperature Ranges
Military (-55oC to +125oC)
Industrial (-40oC to +85oC)
XT
IT
• Package(s)
Ceramic Flatpack
Plastic SOJ (400 mils wide)
Ceramic LCC
F
DJ
EC
• 2V data retention/low power
L
GENERAL DESCRIPTION
No. 307
The AS5LC512K8 is a 3.3V high speed SRAM. It offers
flexibility in high-speed memory applications, with chip enable (CE\)
and output enable (OE\) capabilities. These features can place the
outputs in High-Z for additional flexibility in system design.
Writing to these devices is accomplished when write enable (WE\)
and CE\ inputs are both LOW. Reading is accomplished when WE\
remains HIGH and CE\ and OE\ go LOW.
As a option, the device can be supplied offering a reduced power
standby mode, allowing system designers to meet low standby power
requirements. This device operates from a single +3.3V power supply
and all inputs and outputs are fully TTL-compatible.
The AS5LC512K8DJ offers the convenience and reliability of the
AS5LC512K8 SRAM and has the cost advantage of a plastic
encapsulation.
No. 210
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS5LC512K8
Rev. 2.1 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SRAM
AS5LC512K8
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
GND
I/O
CONTROLS
DQ8
ROW DECODER
A0-A18
INPUT BUFFER
VCC
4,194,304-BIT
MEMORY ARRAY
1024 ROWS X
4096 COLUMNS
DQ1
CE\
OE\
COLUMN DECODER
WE\
*POWER
DOWN
*On the low voltage Data Retention option.
PIN FUNCTIONS
TRUTH TABLE
MODE
OE\ CE\ WE\
STANDBY
X
H
X
READ
L
L
H
NOT SELECTED H
L
H
WRITE
X
L
L
I/O
HIGH-Z
Q
HIGH-Z
D
POWER
STANDBY
ACTIVE
ACTIVE
ACTIVE
X = Don’t Care
AS5LC512K8
Rev. 2.1 08/09
A0 - A18
Address Inputs
WE\
Write Enable
CE\
Chip Enable
OE\
Output Enable
I/O0 - I/O7
Data Inputs/Outputs
VCC
Power
VSS
Ground
NC
No Connection
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
AS5LC512K8
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
** Junction temperature depends upon package type, cycle
time, loading, ambient temperature and airflow, and humidity.
Voltage on Vcc Supply Relative to Vss
Vcc .........................................................................-.5V to 4.6V
Storage Temperature .....................................-65°C to +150°C
Short Circuit Output Current (per I/O)…........................20mA
Voltage on any Pin Relative to Vss........................-.5V to 4.6V
Maximum Junction Temperature**..............................+150°C
Power Dissipation ................................................................1W
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TA < +125oC & -40oC < TA < +85oC ; Vcc = 3.3V +0.3%)
MAX
DESCRIPTION
CONDITIONS
SYM
-12
-15
-20
-25
UNITS NOTES
ICCSP
80
70
60
55
ICCLP
60
50
40
35
mA
ISBTSP
20
20
20
20
mA
ISBTLP
15
15
15
15
mA
ISBCSP
15
15
15
15
mA
ISBCLP
9
9
9
9
mA
CE\ < VIL; Vcc = MAX
f = MAX = 1/t RC
Outputs Open
Power Supply
Current: Operating
"L" Version Only
CE\ > VIH, All other inputs < VIL,
Vcc = MAX, f = 0,
Outputs Open
Power Supply
Current: Standby
"L" Version Only
CE\ > Vcc -0.2V; Vcc = MAX
VIN<Vss +0.2V or
mA
3, 2
VIN>Vcc -0.2V; f = 0
"L" Version Only
" " " " # $#%&
' ( )!
' )!
μ!
μ!
(
*
CAPACITANCE
PARAMETER
Input Capacitance
Output Capactiance
AS5LC512K8
Rev. 2.1 08/09
CONDITIONS
SYMBOL
MAX
UNITS
NOTES
CI
9
pF
4
Co
6
pF
4
o
TA = 25 C, f = 1MHz
VIN = 0
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
AS5LC512K8
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55oC < TA < +125oC or -40oC to +85oC; Vcc = 3.3V +0.3%)
DESCRIPTION
SYM
-12
MIN
-15
MIN
MAX
-20
MAX
MIN
-25
MAX
MIN
MAX
UNITS NOTES
READ CYCLE
Read Cycle Time
tRC
Address Access Time
tAA
Chip Enable Access Time
tACE
Output Hold From Address Change
tOH
2
2
2
2
Chip Enable to Output in Low-Z
tLZCE
2
2
2
2
ns
4, 6, 7
Chip Disable to Output in High-Z
tHZCE
6
7
8
9
ns
4, 6, 7
Output Enable Acess Time
tAOE
6
7
8
9
ns
Output Enable to Output in Low-Z
tLZOE
Output Disable to Output in High-Z
WRITE CYCLE
WRITE Cycle Time
tHZOE
12
15
12
20
15
12
15
0
0
6
25
20
20
0
7
ns
25
ns
25
ns
ns
0
8
9
ns
4, 6, 7
ns
4, 6, 7
tWC
12
15
20
25
ns
Chip Enable to End of Write
tCW
8
10
12
13
ns
Address Valid to End of Write
tAW
8
10
12
13
ns
Address Setup Time
tAS
0
0
0
0
ns
Address Hold From End of Write
tAH
0
0
0
0
ns
WRITE Pulse Width
tWP
10
12
15
15
ns
Data Setup Time
tDS
6
7
8
8
ns
Data Hold Time
tDH
1
1
1
1
ns
Write Disable to Output in Low-Z
tLZWE
2
2
2
2
ns
4, 6, 7
Write Enable to Output in High-Z
tHZWE
5
6
7
7
ns
4, 6, 7
AS5LC512K8
Rev. 2.1 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
AS5LC512K8
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels ...................................................... Vss to 3.0V
Input rise and fall times ......................................................... 3ns
Input timing reference levels ............................................... 1.5V
Output reference levels ........................................................ 1.5V
Output load ................................................. See Figures 1 and 2
3.3V
RL = 50Ω
Q
ZO=50Ω
319Ω
VL = 1.5V
Q
30 pF
5 pF
353Ω
Fig. 1 Output Load Equivalent
Fig. 2 Output Load Equivalent
NOTES
1. All voltages referenced to VSS (GND).
2. ICC limit shown is for absolute worst case switching of
ADDR, ADDR\, ADDR, etc.
3. ICC is dependent on output loading and cycle rates.
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tLZCE, tLZWE, tLZOE, t HZCE, tHZOE and tHZWE
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV from steady state voltage.
7. At any given temperature and voltage condition,
t
HZCE is less than tLZCE, and tHZWE is less than
t
LZWE.
8. WE\ is HIGH for READ cycle.
9.
10.
11.
12.
13.
14.
15.
Device is continuously selected. Chip enables and
output enables are held in their active state.
Address valid prior to, or coincident with, latest
occurring chip enable.
t
RC = Read Cycle Time.
Chip enable and write enable can initiate and
terminate a WRITE cycle.
Output enable (OE\) is inactive (HIGH).
Output enable (OE\) is active (LOW).
ASI does not warrant functionality nor reliability of
any product in which the junction temperature
exceeds 150°C. Care should be taken to limit power to
acceptable levels.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
Vcc for Retention Data
Data Retention Current
CONDITIONS
CE\ > VCC -0.2V
VIN > VCC -0.2 or 0.2V
Vcc = 2.0V
Chip Deselect to Data
Operation Recovery Time
AS5LC512K8
Rev. 2.1 08/09
SYM
MIN
VDR
2
MAX
NOTES
V
6.5
ICCDR
UNITS
mA
tCDR
0
ns
4
tR
20
ms
4, 11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
SRAM
AS5LC512K8
Austin Semiconductor, Inc.
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
4.5V
4.5V
VDR > 2V
tR
t CDR
123456789012345
1234
VIH- 123456
123456789012345
1234
123456
CE\
VIL-
123456
123456789012345
1234
123456
1234
123456789012345
123456
1234
123456789012345
123456
123456789012345
1234
123456
1234
123456789012345
123456
1234
123456789012345
123456789012345
1234567
12345
123456789012345
1234567
12345
123456789012345
1234567
12345
1234567
12345
123456789012345
1234567
12345
123456789012345
123456789012345
1234567
12345
1234567
12345
123456789012345
1234567
12345
123456789012345
VDR
READ CYCLE NO. 11, 2
(Address Controlled, CE\ = OE\ = VIL, WE\ = VIH)
t RC
ADDRESS
VALID
tOH
I/O, DATA IN
& OUT
Previous Data Valid
tAA
1234567
12345678901
12
1234567
12
1234567
12345678901
12
1234567
12
12345678901
1234567
12
1234567
12
1234567
12345678901
12
1234567
12
12345678901
1234567
12
1234567
12
12345678901
1234567
12
1234567
Data Valid
READ CYCLE NO. 2
(WE\ = VIH)
t RC
ADDRESS
t AOE
t HZOE
t LZOE
CE\
t LZCE
t ACE
I/O, DATA IN
& OUT
High-Z
1234567
112345
1234567
11
1234567
112345
1234567
1234567
112345
1234567
11
1234567
12345
1
1234567
1234567
112345
1234567
11
1234567
112345
1234567
t HZCE
Data Valid
t PU
t PD
Icc
NOTES:
1. WE\ is HIGH for READ cycle.
2. Device is continuously selected. Chip enables and output enables are held in their
active state.
AS5LC512K8
Rev. 2.1 08/09
1234
1234
1234
Don’t Care
1234
1234
123456
123456
123456
123456
123456
Undefined
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
SRAM
AS5LC512K8
Austin Semiconductor, Inc.
WRITE CYCLE NO. 11
(CE Controlled)
t WC
ADDRESS
t AW
t AS
tAH
t CW
CE\
12345678901234567890123456
123456789012345678901234
1234567890
12345678901234567890123456
123456789012345678901234
1234567890
123456789012345678901234
1234567890
WE\12345678901234567890123456
12345678901234567890123456
123456789012345678901234
1234567890
123456
123456789012345678
123456
123456789012345678
123456789012345678
123456
123456789012345678
123456
t WP1
tDH
t DS
Data Valid
I/O, DATA IN
I/O, DATA OUT
High-Z
High-Z
WRITE CYCLE NO. 21, 2
(Write Enabled Controlled)
t WC
ADDRESS
t AW
123456789012345678901
12345678901234567890
1234567890
12345678901234567890
123456789012345678901
1234567890
123456789012345678901
12345678901234567890
1234567890
CE\ 123456789012345678901
12345678901234567890
1234567890
123456789012345678901
12345678901234567890
1234567890
t AS
WE\
123456
123456
123456
123456
123456
t CW
1234567
123456789012345
t A H12345678901234567
1234567
12345678901234567
123456789012345
1234567
12345678901234567
123456789012345
1234567
12345678901234567
123456789012345
1234567
12345678901234567
123456789012345
t WP1
tDH
Data Valid
I/O, DATA IN
I/O, DATA OUT
High-Z
High-Z
NOTES:
1.
2.
Chip enable and write enable can initiate and terminate a WRITE cycle.
Output enable (OE\) is inactive (HIGH).
AS5LC512K8
Rev. 2.1 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
SRAM
AS5LC512K8
Austin Semiconductor, Inc.
WRITE CYCLE NO. 31, 2, 3
(WE Controlled)
t WC
ADDRESS
t AW
1234567890123456789012
123456789012345678901
123456789
123456789012345678901
1234567890123456789012
123456789
123456789012345678901
123456789
CE\1234567890123456789012
1234567890123456789012
123456789012345678901
123456789
t AS
WE\
123456
123456
123456
123456
tAH
1234567
12345678901234567
1234567890123456
1234567
12345678901234567
1234567890123456
1234567
12345678901234567
1234567890123456
12345678901234567
1234567890123456
1234567
t CW
t WP2
tDH
t DS
Data Valid
DATA IN
t HZWE
DATA OUT
t LZWE
High-Z
Data Undefined
NOTES:
1. At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE.
2. Chip enable and write enable can initiate and terminate a WRITE cycle.
3. Output enable (OE\) is active (LOW).
AS5LC512K8
Rev. 2.1 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
SRAM
AS5LC512K8
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #307 (Package Designator F)
E
L
Pin 1 identifier area
12345678
12345678
12345678
12345678
12345678
12345678
12345678
12345678
36
1
e
D
b
D1
Bottom View
S
Top View
A
c
Q
E2
SYMBOL
A
b
c
D
D1
E
E2
e
L
Q
ASI SPECIFICATIONS
MIN
MAX
0.096
0.125
0.015
0.022
0.003
0.009
0.910
0.930
0.840
0.860
0.505
0.515
0.385
0.397
0.050 BSC
0.250
0.370
0.020
0.045
*All measurements are in inches.
AS5LC512K8
Rev. 2.1 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
SRAM
Austin Semiconductor, Inc.
AS5LC512K8
MECHANICAL DEFINITIONS*
Package Designator DJ
SYMBOL
A
A1
A2
B
b
C
D
E
E1
E2
e
ASI SPECIFICATIONS
MIN
MAX
0.128
0.148
0.025
--0.082
--0.015
0.020
0.026
0.032
0.007
0.013
0.920
0.930
0.435
0.445
0.395
0.405
0.370 BSC
0.050 BSC
*All measurements are in inches.
AS5LC512K8
Rev. 2.1 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
SRAM
AS5LC512K8
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #210 (Package Designator EC)
P
A
Pin 1 identifier area
1234567
1234567
1234567
1234567
1234567
1234567
1234567
1234567
1234567
1234567
R
L2
1
D
36
L
e
B
D1
E
A1
SYMBOL
A
A1
B
D
D1
E
e
L
L2
P
R
ASI SPECIFICATIONS
MIN
MAX
0.080
0.100
0.054
0.066
0.022
0.028
0.910
0.930
0.840
0.860
0.445
0.460
0.050 BSC
0.100 TYP
0.115
0.135
--0.006
0.009 TYP
*All measurements are in inches.
AS5LC512K8
Rev. 2.1 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11
SRAM
AS5LC512K8
Austin Semiconductor, Inc.
ORDERING INFORMATION
EXAMPLE: AS5LC512K8F-12L/XT
Device Number
AS5LC512K8
AS5LC512K8
AS5LC512K8
AS5LC512K8
Package
Type
F
F
F
F
Speed
ns
-12
-15
-20
-25
Options**
Process
L
L
L
L
/*
/*
/*
/*
Options**
Process
L
L
L
L
/*
/*
/*
/*
Options**
Process
L
L
L
L
/*
/*
/*
/*
EXAMPLE: AS5LC512K8DJ-20L/883C
Device Number
AS5LC512K8
AS5LC512K8
AS5LC512K8
AS5LC512K8
Package
Type
DJ
DJ
DJ
DJ
Speed
ns
-12
-15
-20
-25
EXAMPLE: AS5LC512K8EC-15L/IT
Device Number
AS5LC512K8
AS5LC512K8
AS5LC512K8
AS5LC512K8
Package
Type
EC
EC
EC
EC
Speed
ns
-12
-15
-20
-25
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT = Extended Temperature Range
883C = Full Military Processing1
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
**OPTIONS DEFINITIONS
L = 2V Data Retention / Low Power
NOTES:
AS5LC512K8
Rev. 2.1 08/09
1. 883C process available with ceramic packaging only.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
SRAM
Austin Semiconductor, Inc.
AS5LC512K8
DOCUMENT TITLE
512K x 8 SRAM 3.3 VOLT HIGH SPEED SRAM with CENTER POWER PINOUT
Rev #
2.1
AS5LC512K8
Rev. 2.1 08/09
History
Pg 1: Changed 0.3% to 0.3V
Release Date
August 2009
Status
Release
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13
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