Intersil CA5420AM 0.5mhz, low supply voltage, low input current bimos operational amplifier Datasheet

CA5420A
®
Data Sheet
December 8, 2009
0.5MHz, Low Supply Voltage, Low Input
Current BiMOS Operational Amplifiers
FN1925.6
Features
• CA5420A at 5V Supply Voltage with Full Military
Temperature Range Guaranteed Specifications
The CA5420A is an integrated circuit operational amplifier that
combines PMOS transistors and bipolar transistors on a single
monolithic chip. It is designed and guaranteed to operate in
microprocessor logic systems that use V+ = 5V, V- = GND,
since it can operate down to ±1V supplies. It will also be
suitable for 3.3V logic systems.
• CA5420A Guaranteed to Operate from ±1V to ±10V
Supplies
• 2V Supply at 300µA Supply Current
• 1pA (Typ) Input Current (Essentially Constant to +85°C)
• Rail-to-Rail Output Swing (Drive ±2mA Into 1kΩ Load)
The CA5420A BiMOS operational amplifier features gateprotected PMOS transistors in the input circuit to provide very
high input impedance, very low input currents (less than 1pA).
The internal bootstrapping network features a unique
guardbanding technique for reducing the doubling of leakage
current for every +10°C increase in temperature. The CA5420A
operates at total supply voltages from 2V to 20V either single or
dual supply. This operational amplifier is internally phase
compensated to achieve stable operation in the unity gain
follower configuration. Additionally, it has access terminals for a
supplementary external capacitor if additional frequency roll-off
is desired. Terminals are also provided for use in applications
requiring input offset voltage nulling. The use of PMOS in the
input stage results in common-mode input voltage capability
down to 0.45V below the negative supply terminal, an important
attribute for single supply application. The output stage uses a
feedback OTA type amplifier that can swing essentially from
rail-to-rail. The output driving current of 1.0mA (Min) is provided
by using nonlinear current mirrors.
• Pin Compatible with 741 Op Amp
• Pb-Free Available (RoHS Compliant)
Applications
• pH Probe Amplifiers
• Picoammeters
• Electrometer (High Z) Instruments
• Portable Equipment
• Inaccessible Field Equipment
• Battery Dependent Equipment (Medical and Military)
• 5V Logic Systems
• Microprocessor Interface
This device has guaranteed specifications for 5V operation
over the full military temperature range of -55°C to +125°C.
The CA5420A has the same 8 lead pinout used for the
industry standard 741.
Functional Diagram
X1
-
MOS
BIPOLAR
+
MOS
BIPOLAR
X1
BUFFER AMPS;
BOOTSTRAPPED
INPUT PROTECTION
NETWORK
1
HIGH GAIN
(50k)
OTA BUFFER
(X2)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1998, 2005, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
CA5420A
Ordering Information
PART NUMBER
(Note 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
CA5420AM
5420A
-55 to +125
8 Ld SOIC
M8.15
CA5420AMZ (Notes 1, 2)
5420 AMZ
-55 to +125
8 Ld SOIC
(Tape and Reel)
M8.15
NOTES:
1. Add “96” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020.
3. For Moisture Sensitivity Level (MSL), please see device information page for CA5420A. For more information on MSL please see techbrief
TB363.
Pinout
CA5420A
(8 LD SOIC)
TOP VIEW
OFFSET 1
NULL
INV.
2
INPUT
NON-INV. 3
INPUT
V- 4
8 STROBE
+
7 V+
6 OUTPUT
5 OFFSET
NULL
NOTE: Pin is connected to Case.
2
FN1925.6
December 8, 2009
CA5420A
Absolute Maximun Ratings
Thermal Information
Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . . 22V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . (V+ + 8V) to (V- -0.5V)
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration (Note 4). . . . . . . . . . . . . . . . Indefinite
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Thermal Resistance (Typical, Note 5) θJA (°C/W)
θJC (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . .
157
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . +150°C
Maximum Storage Temperature Range (All Types) . . -65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. Short circuit may be applied to ground or to either supply.
5. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Typical Values Intended Only for Design Guidance. V+ = +5V; V- = GND, TA = +25°C
PARAMETER
SYMBOL
TEST CONDITIONS
CA5420A
UNITS
Input Resistance
RI
150
TΩ
Input Capacitance
CI
4.9
pF
Output Resistance
RO
300
Ω
Equivalent Input
Noise Voltage
eN
62
nV/√Hz
38
nV/√Hz
Short-Circuit Current To
Opposite Supply
f = 1kHz
RS = 100Ω
f = 10kHz
Source
IOM+
2.6
mA
Sink
IOM-
2.4
mA
Gain Bandwidth Product
fT
0.5
MHz
Slew Rate
SR
0.5
V/µs
0.7
µs
Transient Response
Rise Time
tr
Overshoot
OS
15
%
Current from Terminal 8 To V-
I8 +
20
µA
Current from Terminal 8 To V+
I8-
2
mA
Settling Time
+
Electrical Specifications
RL = 2kΩ, CL = 100pF
0.01%
AV = 1
2VP-P Input
8
µs
0.10%
AV = 1
2VP-P Input
4.5
µs
TA = +25°C, V+ = 5V, V- = 0, Unless Otherwise Specified
PARAMETER
TEST
CONDITIONS
SYMBOL
CA5420A
MIN
TYP
MAX
UNITS
Input Offset Voltage
VIO
VO = 2.5V
-
1
5
mV
Input Offset Current
IIO
VO = 2.5V
-
0.02
4
pA
Input Current
II
VO = 2.5V
-
0.02
5
pA
Common Mode Rejection Ratio
CMRR
VCM = 0 to 3.7V, VO = 2.5V
75
83
-
dB
Common Mode Input Voltage Range
VlCR+
VO = 2.5V
3.7
4
-
V
-
-0.3
0
V
75
83
-
dB
VlCRPower Supply Rejection Ratio
PSRR
Large Signal Voltage Gain
AOL
ΔV+ = 1V; ΔV- = 1V
VO = 0.5 to 4V
RL = ∞
85
87
-
dB
VO = 0.5 to 4V
RL = 10kΩ
85
87
-
dB
VO = 0.7 to 3V
RL = 2kΩ
80
85
-
dB
ISOURCE
VO = 0V
1.2
2.7
-
mA
ISINK
VO = 5V
1.2
2.1
-
mA
Source Current
Sink Current
3
FN1925.6
December 8, 2009
CA5420A
Electrical Specifications
TA = +25°C, V+ = 5V, V- = 0, Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
Output Voltage
VOM+
CA5420A
TEST
CONDITIONS
MAX
UNITS
4.94
-
V
0.13
0.15
V
4.7
4.9
-
V
-
0.12
0.15
V
3.5
4.6
-
V
-
0.1
0.15
V
VO = 0V
-
400
500
µA
VO = 2.5V
-
430
550
µA
RL = ∞
VOMVOM+
RL = 10kΩ
VOMVOM+
RL = 2kΩ
VOMSupply Current
ISUPPLY
Electrical Specifications
MIN
TYP
4.85
-
TA = -55°C to +125°C, V+ = 5V, V- = 0, Unless Otherwise Specified
CA5420A
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
Input Offset Voltage
VIO
VO = 2.5V
-
2
10
mV
Input Offset Current
IIO
VO = 2.5V
-
1.5
3
nA
-
2
10
pA
-
2
5
nA
Up to TA = +85°C
|II|
Input Current
VO = 2.5V
Up to TA = +85°C
-
10
15
pA
Common Mode Rejection Ratio
CMRR
VCM = 0 to 3.7V,
VO = 2.5V
70
80
-
dB
Common Mode Input Voltage Range
VlCR+
VO = 2.5V
3.7
4
-
V
-
-0.3
0
V
ΔV+ = 1V;
ΔV- = 1V
70
83
-
dB
VO = 0.5 to 4V
RL = ∞
65
75
-
dB
VO = 0.7 to 4V
RL = 10kΩ
80
87
-
dB
VlCRPower Supply Rejection Ratio
PSRR
Large Signal Voltage Gain
AOL
VO = 0.7 to 2.5V
RL = 2kΩ
75
80
-
dB
ISOURCE
VO = 0V
1
2.7
-
mA
Sink Current
ISINK
VO = 5V
1
2.1
-
mA
Output Voltage
VOM+
RL = ∞
4.8
4.9
-
V
-
0.16
0.2
V
4.7
4.9
-
V
-
0.15
0.2
V
RL = 2kΩ
3
4
-
V
-
0.14
0.2
V
VO = 0V
-
430
550
µA
VO = 2.5V
-
480
600
µA
Source Current
VOMVOM+
RL = 10kΩ
VOMVOM+
VOMSupply Current
ISUPPLY
4
FN1925.6
December 8, 2009
CA5420A
For Equipment Design at VSUPPLY = ±1V, TA = +25°C, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
CA5420A
MIN
TYP
MAX
UNITS
Input Offset Voltage
VIO
-
2
5
mV
Input Offset Current
|IIO|
-
0.01
4
pA
|II|
-
0.02
5
pA
10
100
-
kV/V
80
100
-
dB
-
560
1000
µV/V
60
65
-
dB
VlCR+
0.2
0.5
-
V
VlCR-
-1
-1.3
-
V
PSRR
-
32
320
µV/V
70
90
-
dB
0.9
0.95
-
V
Input Current
Large Signal Voltage Gain
AOL
Common Mode Rejection Ratio
RL = 10kΩ
CMRR
Common Mode Input Voltage Range
Power Supply Rejection Ratio
Maximum Output Voltage
VOM+
Supply Current
Device Dissipation
Input Offset Voltage Temp. Drift
RL = ∞
VOM-
-0.85
-0.91
-
V
ISUPPLY
-
350
650
µA
PD
-
0.7
1.1
mW
ΔVIO/ΔT
-
4
-
µV/°C
For Equipment Design at VSUPPLY = ±10V, TA = +25°C, Unless Otherwise Specified
Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
CA5420A
MIN
TYP
MAX
UNITS
-
2
5
mV
Input Offset Voltage
VIO
Input Offset Current
|IIO|
-
0.03
4
pA
|II|
-
0.05
5
pA
Input Current
Large Signal Voltage Gain
AOL
Common Mode Rejection Ratio
RL = 10kΩ
CMRR
Common Mode Input Voltage Range
Power Supply Rejection Ratio
100
-
kV/V
80
100
-
dB
-
100
320
µV/V
70
80
-
dB
VlCR+
9
9.3
-
V
VlCR-
-10
-10.3
-
V
-
32
320
µV/V
70
90
-
dB
PSRR
VOM+
Maximum Output Voltage
20
RL = ∞
9.7
9.9
-
V
VOM-
-9.7
-9.85
-
V
ISUPPLY
-
450
1000
µA
Device Dissipation
PD
-
9
14
mW
Input Offset Voltage
Temperature Drift
ΔVIO/ΔT
-
4
-
µV/°C
Supply Current
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
5
FN1925.6
December 8, 2009
CA5420A
Typical Applications
High Input Resistance Voltmeter
Picoammeter Circuit
The exceptionally low input current (typically 0.2pA) makes
the CA5420A highly suited for use in a picoammeter circuit.
With only a single 10GΩ resistor, this circuit covers the range
from ±1.5pA. Higher current ranges are possible with suitable
switching techniques and current scaling resistors. Input
transient protection is provided by the 1MΩ resistor in series
with the input. Higher current ranges require that this resistor
be reduced. The 10MΩ resistor connected to pin 2 of the
CA5420A decouples the potentially high input capacitance
often associated with lower current circuits and reduces the
tendency for the circuit to oscillate under these conditions.
10GΩ
1MΩ
10MΩ
-
Supply current in the standby position with the meter
undeflected is 300µA. At full-scale deflection this current
rises to 800µA. Carbon-zinc battery life should be in excess
of 1,000 hours.
+1.5V
500-0-500
µA
7
CA5420A
3
The meter is placed in series with the gain network, thus
eliminating the meter temperature co-efficient error term.
+1.5V
10pF
2
Advantage is taken of the high input impedance of the
CA5420A in a high input resistance DC voltmeter. Only two
1.5V “AA” type penlite batteries power this exceedingly
high-input resistance (>1,000,000MΩ) DC voltmeter. Full-scale
deflection is ±500mV, ±150mV, and ±15mV. Higher voltage
ranges are easily added with external input voltage attenuator
networks.
+
6
BATTERY
RETURNS
1
10kΩ
22MΩ
10MΩ
M
±50pA
4
5
3
CA5420A
100pF
2
1.5kΩ
±15pA
1.5kΩ
1%
±5pA
1kΩ
430Ω
1%
500-0-500
µA
7
+
-
M
±500mV
4
5
1
6
BATTERY
RETURNS
10kΩ
1.5kΩ
1.5kΩ
1%
±150mV
±50mV
1kΩ
430Ω
1%
±15mV
150Ω
1%
1.1kΩ
68Ω
1%
-1.5V
-1.5V
±1.5pA
11kΩ
150Ω
1%
68Ω
1%
FIGURE 2. HIGH INPUT RESISTANCE VOLTMETER
FIGURE 1. PICOAMMETER CIRCUIT
OUTPUT STAGE TRANSISTOR SATURATION
VOLTAGE, Q19 (mV)
INPUT & OUTPUT VOLTAGE EXCURSIONS FROM THE
POSITIVE AND NEGATIVE SUPPLY VOLTAGE (V)
Typical Performance Curves
1.0
TA = +25°C
RL = 100kΩ
0.8
0.6
0.4
0.2
VO-
0
-0.2
VO+
-0.4
VICR-
-0.6
VICR+
-0.8
-1.0
0
1
5
10
SUPPLY VOLTAGE (V)
15
FIGURE 3. OUTPUT VOLTAGE SWING AND COMMON MODE
INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE
6
10
TA = +25°C
V- = 0V
V+ = 2V
100
V+ = 5V
V+ = 10V
V+ = 20V
1000
0.001
0.1
1
LOAD (SOURCING) CURRENT (mA)
10
FIGURE 4. OUTPUT VOLTAGE vs LOAD SOURCING CURRENT
FN1925.6
December 8, 2009
CA5420A
1000
(Continued)
V+ = 5V
V- = GND
TA = +25°C
V+ = 0V
SUPPLY CURRENT (µA)
OUTPUT STAGE TRANSISTOR SATURATION
VOLTAGE, Q17 (mV)
Typical Performance Curves
V- = -20V
V- = -10V
V- = -5V
V- = -2V
100
2000
1600
1200
800
400
10
0.01
0.1
1
LOAD (SINKING) CURRENT (mA)
10
0
FIGURE 5. OUTPUT VOLTAGE vs LOAD SINKING CURRENT
1
2
3
OUTPUT VOLTAGE (V)
4
5
FIGURE 6. SUPPLY CURRENT vs OUTPUT VOLTAGE
800
5.00
TA = +25°C
V+ = 5V
V- = GND
RL TO GND
3.75
V+ = 5V
V- = GND
700
INPUT BIAS CURRENT (pA)
OUTPUT VOLTAGE SWING (V)
2400
2.50
1.25
600
500
400
300
200
100
0
1
10
100
LOAD RESISTANCE (kΩ)
0
25
1000
OPEN LOOP VOLTAGE GAIN (dB)
EQUIVALENT INPUT NOISE VOLTAGE (nV√Hz)
100
101
102
103
55
65
75
85
95
TEMPERATURE (°C)
104
105
FREQUENCY (Hz)
FIGURE 9. INPUT NOISE VOLTAGE vs FREQUENCY
106
105
115
TA =+ 25°C
V+ = +10V, V- = 10V
RL = 10kΩ
CL = 0pF
TA = +25°C
VS = ±10V
VS = ±5V
VS = ±1V
1
101
45
125
FIGURE 8. INPUT BIAS CURRENT DRIFT (ΔIB/ΔT)
FIGURE 7. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
1000
35
100
0
-45
80
-90
60
-135
-180
40
20
0
1
101
102
103
104
105
OPEN LOOP PHASE (DEGREES)
0
106
FREQUENCY (Hz)
FIGURE 10. OPEN LOOP GAIN AND PHASE SHIFT RESPONSE
Small Outline Plastic Packages (SOIC)
7
FN1925.6
December 8, 2009
CA5420A
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010) M
H
B M
INCHES
E
SYMBOL
-B-
1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
α
B S
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
8
0°
8
8°
0°
7
8°
7. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
8. Dimensioning and tolerancing per ANSI Y14.5M-1982.
9. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
10. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
11. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
12. “L” is the length of terminal for soldering to a substrate.
13. “N” is the number of terminal positions.
14. Terminal numbers are shown for reference only.
15. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
16. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
8
FN1925.6
December 8, 2009
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