W163 Spread Aware™, Zero Delay Buffer Features Key Specifications • Spread Aware™—designed to work with SSFTG reference signals • Outputs may be three-stated • Available in 8-pin SOIC package • Extra strength output drive available (-15 version) • Internal feedback maximized the number of outputs available in 8-pin package Operating Voltage: ................................................ 3.3V±10% Operating Range: ................................ 10 < fOUT < 133 MHz Cycle-to-Cycle Jitter: .................................................. 200 ps Output-to-Output Skew: .............................................. 250 ps Device-to-Device Skew:............................................... 700 ps Propagation Delay: ...................................................... 350 ps Block Diagram Pin Configuration SOIC REF PLL REF 1 8 Q0 2 7 QFB Q3 Q1 3 6 VDD GND 4 5 Q2 QFB Q0 Q1 Q2 Q3 Spread Aware is a trademark of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 February 21, 2000, rev. *A W163 Pin Definitions Pin No. Pin Type REF 1 I Reference Input: The output signals Q0:3 will be synchronized to this signal unless the device is programmed to bypass the PLL. Q0:3 2, 3, 5, 7 O Outputs: These signals will be synchronous and of equal frequency to the signal input at pin 1. QFB 8 O Feedback Output: This output signal does not vary from signals Q0:3 in function, but is noted as the signal used to establish the propagation delay of nearly 0. VDD 6 P Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise for optimal jitter performance. GND 4 P Ground Connections: Connect all grounds to the common system ground plane. Pin Name Pin Description Overview the result is a significant amount of tracking skew which may cause problems in systems requiring synchronization. The W163 products are five-output zero delay buffers. A Phase-Locked Loop (PLL) is used to take a time-varying signal and provide five copies of that same signal out. The internal feedback to the PLL provides outputs in phase with the reference inputs. For more details on Spread Spectrum timing technology, please see the Cypress Application note titled, “EMI Suppression Techniques with Spread Spectrum Frequency Timing Generator (SSFTG) ICs.” Schematic REF Spread Aware Q0 Q1 GND Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, 2 QFB Q3 VDD Q2 Ferrite Bead 0.1 µF 10 µF VDD W163 Absolute Maximum Ratings above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . Parameter Description Rating Unit V VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 –65 to +150 °C 0 to +70 °C –55 to +125 °C 0.5 W TSTG Storage Temperature TA Operating Temperature TB Ambient Temperature under Bias PD Power Dissipation DC Electrical Characteristics: TA =0°C to 70°C, VDD = 3.3V ±10% Parameter Description Test Condition Min Typ Max Unit 40 mA 0.8 V IDD Supply Current VIL Input Low Voltage Unloaded, 100 MHz VIH Input High Voltage VOL Output Low Voltage IOL = 12 mA (-15) IOL = 8 mA (-5) VOH Output High Voltage IOL = 12 mA (-15) IOL = 8 mA (-5) IIL Input Low Current VIN = 0V 50 µA IIH Input High Current VIN = VDD 100 µA 2.0 V 0.4 V 2.4 V AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±10% Parameter Description fIN Input Frequency fOUT Output Frequency tR tF tICLKR tICLKF Test Condition 15-pF load Min Typ Max Unit 10 133 MHz 10 133 MHz Output Rise Time (-05)  2.0 to 0.8V, 15-pF load 2.5 ns Output Rise Time (-15)  2.0 to 0.8V, 20-pF load 1.5 ns Output Fall Time (-05) 2.0 to 0.8V, 15-pF load 2.5 ns Output Rise Time (-15) 2.0 to 0.8V, 20-pF load 1.5 ns ? ns ? ns  Input Clock Rise Time Input Clock Fall Time   [2, 3] tPD FBIN to REF Skew Measured at VDD/2 –350 0 350 ps tSK Output to Output Skew All outputs loaded equally –250 0 250 ps tSKDD Device to Device Skew Measured at FBIN pins, VDD/2 –700 0 700 ps tD Duty Cycle 15-pF load 45 50 55 % tLOCK PLL Lock Time Power supply stable and 1.0 ms tJC Jitter, Cycle-to-Cycle 200 ps Notes: 1. Longer input rise and fall time will degrade skew and jitter performance. 2. All AC specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V. 3. Skew is measured at 1.4V on rising edges. 4. Duty cycle is measured at 1.4V. 5. For the higher drive -15, the load is 20 pF. 3 W163 Ordering Information Ordering Code W163 Option Package Name -05, -15 G Package Type 8-pin Plastic SOIC (150-mil) Document #: 38-00787-*A Package Diagram 8-Pin Small Outline Integrated Circuit (SOIC, 150-mil) © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.