Integral IN24LC02B 2k 2.5v cmos serial eeprom Datasheet

TECHNICAL DATA
2K 2.5V CMOS Serial EEPROMs
IN24LC02B
DESCRIPTION
IN24LC02B is a 2K-bit Electrically Erasable PROM. The device is organized as a single
block of 256 x 8 bit memory with a two wire serial interface.
Low voltage design permits operation down to 2.5volts with standby and active currents
of only 5µA and 1mA respectively.
The IN24LC02B also has a page-write capability for up to 8 bytes of data.
The IN24LC02B is available in the standard 8-pin DIP.
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
- 5 µA standby current typical at 3.0V
• Organized as a single block of 256 bytes (256x8)
• Two wire serial interface bus, I2C compatible
PACKAGE
TA = -40 ... +85 °C
• Schmitt trigger, filtered inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
PINNING
Name
Function
Vss
Ground
SDA
Serial Address/Data I/O
SCL
Serial Clock
• Can be operated as a serial ROM
WP
Write Protect Input
• Factory programming (QTP) available
VCC
+2.5V to 5.5V Power Supply
• ESD protection > 3,000V
AO, A1, A2
No Internal Connection
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• 1,000,000 ERASE/WRITE cycles guaranteed*
• Data retention > 200 years
Pin Connection
A0
1
8
Vcc
A1
2
7
WP
A2
3
6
SCL
Vss
4
5
SDA
1
IN24LC02B
Figure 1. Representative Block Diagram
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
Parameter
Value
VCC
All inputs and outputs w.r.t.Vss
Storage temperature
Ambient temp. with power applied
Soldering temperature of leads (10 seconds)
ESD protection on all pins
7.0 V
-0.6V to Vcc + 1.0V
-65oC to +150oC
-40oC to +85oC
+300oC
> 4 kV
DC CHARACTERISTICS
Vcc = +2.5V to +5.5V: Tamb = -40oC to +85oC
Parameter
Symbol
Min
WP, SCL and SDA pins:
0.7VCC
High level input voltage
VlH
VIL
Low level input voltage
VHYS
0.05VCC
Hysteresis of Schmitt trigger inputs
VOL
Low level output voltage
Input leakage current
ILI
-10
Output leakage current
ILO
-10
Pin capacitance (all inputs/outputs)
CIN
COUT
Operating current
ICC WRITE
ICCREAD
Standby current
ICCS
-
Max
Units
0.3VCC
0.40
10
10
V
V
V
V
µA
µA
pF
10
3
1
30
100
mA
mA
µA
µA
Mode
Note 1
IOL = 3.0mA, VCC = 2.5V
VlN=0.1V to VCC
VOUT=0.1V to VCC
VCC = 5.0V (Note 1)
Tamb =25oC,Fclk =1MHz
VCC = 5.5V SCL =400 kHz
SDA=SCL=VCC=3.0V,
SDA=SCL=VCC=5.5V
2
IN24LC02B
Figure 2. Bus timing Start/Stop
AC CHARACTERISTICS
Parameter
Symbol
STANDARD
MODE
Vcc = 4.5 - 5.5V
FAST MODE
Units Remarks
FCLK
THIGH
TLOW
TR
TF
Min
4000
4700
-
Max
100
1000
300
Min
600
1300
-
Max
400
300
300
START condition hold time
THD:STA
4000
-
600
-
ns
START condition setup time
TSU:STA
4700
-
600
-
ns
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
THD:DAT
TSU:DAT
TSU:STO
TAA
0
250
4000
-
3500
0
100
600
-
900
ns
ns
ns
ns
TBUF
4700
-
1300
-
ns
TOF
-
250
20+0.1CB
250
ns
TSP
-
50
-
50
ns
TWR
-
10
-
10
ms
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
Bus free time
Output fall time from VIH min
to VIL max
Input filter spike suppres-sion
(SDA & SCL pins)
Write cycle time
kHz
ns
ns
ns Note 2
ns Note 2
After this period the
first clock pulse is
generated
Only relevant for
repeated START
condition
Note 1
Time the bus must be
free before a new
transmission can start
Note2,
CB≤100pF
Note 3
Byte or Page mode
Note 1: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined
region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or
STOP conditions.
Note 2: Not 100% tested. CB = total capacitance of one bus line in pF.
Note 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide
improved noise and spike suppression. This eliminates the need for a Ti specification for standard
operation.
3
IN24LC02B
Figure 3. Bus timing Data
FUNCTIONAL DESCRIPTION
The IN24LC02B supports a bidirectional two wire bus and data transmission protocol. A device
that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The
bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus
access, and generates the START and STOP conditions, while the IN24LC02B works as slave.
Both, master and slave can operate as transmitter or receiver but the master device determines
which mode is activated.
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is HIGH will be interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been defined (see Figure 4).
Bus not Busy (A)
Both data and clock lines remain HIGH.
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START
condition. All commands must be preceded by a START condition.
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP
condition. All operations must be ended with a STOP condition.
Data Valid (D)
The state of the data line represents valid data when, after a START condition, the data line is stable
for the duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW period of the clock signal. There is one clock
pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of the data bytes transferred between the START and STOP conditions is determined by the
master device and is theoretically unlimited, although only the last sixteen will be stored when
doing a write operation. When an overwrite does occur it will replace data in a first in first out
fashion.
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of
each byte. The master device must generate an extra clock pulse which is associated with this
acknowledge bit.
4
IN24LC02B
Note: The IN24LC02B does not generate any acknowledge bits if an internal programming cycle is in
progress
The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse
in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related
clock pulse. Of course, setup and hold times must be taken into account. A master must signal an
end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked
out of the slave. In this case, the slave must leave the data line HIGH to enable the master to
generate the STOP condition.
Figure 4. Data Transfer Sequence on the serial bus
BUS CHARACTERISTICS
Slave Address
The IN24LC02B are software-compatible with devices such as 24C01A, 24C02A, 24LC01,
and 24LC02B. A single 24LC02B can be used in place of two 24LC01's,
for example, without any modifications to software.
The "chip select" portion of the control byte becomes a don't care.
After generating a START condition, the bus master transmits the slave address consisting
of a 4-bit device code (1010) for the IN24LC02B, followed by three don't care bits.
The eighth bit of slave address determines if the master device wants to read or write to
the IN24LC02B (see Figure 5).
The IN24LC0 monitors the bus for its corresponding slave address all the time.
It generates an acknowledge bit if the slave address was true and it is not in a programming
mode.
Operation
Read
Write
Control Code
1010
1010
Chip Select
XXX
XXX
R/W
1
0
5
IN24LC02B
Figure 5. Control Byte Allocation
5.0 WRITE OPERATION
5.1 Byte Write
Following the start condition from the master, the device code (4 bits), the block address (3 bits),
and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates
to the addressed slave receiver that a byte with a word address will follow after it has generated an
acknowledge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is
the word address and will be written into the address pointer of the IN24LC02B. After receiving
another acknowledge signal from the IN24LC02B the master device will transmit the data word to
be written into the addressed memory location. The IN24LC02B acknowledges again and the
master generates a stop condition. This initiates the internal write cycle, and during this time the
IN24LC02B will not generate acknowledge signals (see Figure 6).
Page Write
The write control byte, word address and the first data byte are transmitted to the IN24LC02B in the
same way as in a byte write. But instead of generating a stop condition the master transmits up to
sixteen data bytes to the IN24LC02B which are temporarily stored in the on-chip page buffer and
will be written into the memory after the master has transmitted a stop condition. After the receipt
of each word, the four lower order address pointer bits are internally incremented by one. The
higher order seven bits of the word address remains constant. If the master should transmit more
than sixteen words prior to generating the stop condition, the address counter will roll over and the
previously received data will be overwritten. As with the byte write operation, once the stop
condition is received an internal write cycle will begin (see Figure 8).
Figure 6. Byte Write
6
IN24LC02B
6.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write cycle, this can be used to determine when the
cycle is complete (this feature can be used to maximize bus throughput). Once
the stop condition for a write command has been
issued from the master, the device initiates the
Figure 7. Acknowledge Polling Flow
internally timed write cycle, ACK polling can be
initiated immediately. This involves the master
sending a start condition followed by the control
byte for a write command (R/W =0). If the
device is still busy with the write cycle, then no
ACK will be returned. If the cycle is complete,
then the device will return the ACK and the
master can then proceed with the next read or
write command. See Figure 7 for flow diagram.
WRITE PROTECTION
The IN24LC02B can be used as a serial ROM
when the WP pin is connected to Vcc.
Programming will be inhibited and the entire
memory will be write-protected.
READ OPERATION
Read operations are initiated in the same way as
write operations with the exception that the R/W
bit of the slave address is set to one. There are
three basic types of read operations: current
address read, random read, and sequential read.
Current Address Read
The IN24LC02B contains an address counter that maintains the address of the last word accessed,
internally incremented by one. Therefore, if the previous access (either a read or write operation)
was to address n, the next current address read operation would access data from address n + 1.
Upon receipt of the slave address with R/W bit set to one, the IN24LC04/08 issues an acknowledge
and transmits the eight bit data word. The master will not acknowledge the transfer but does
generate a stop condition and the IN24LC02B discontinues transmission (see Figure 9).
Random Read
Random read operations allow the master to access any memory location in a random manner. To
perform this type of read operation, first the word address must be set. This is done by sending the
word address to the IN24LC02B as part of a write operation. After the word address is sent, the
master generates a start condition following the acknowledge. This terminates the write operation,
but not before the internal address pointer is set. Then the master issues the control byte again but
with the R/W bit set to a one. The IN24LC02B will then issue an acknowledge and transmits the
eight bit data word. The master will not acknowledge the transfer but does generate a stop condition
and the IN24LC02B discontinues transmission (see Figure 10).
7
IN24LC02B
Figure 8. Page Write
Figure 9. Current Address Read
Figure 10. Random Read
Sequential Read
Sequential reads are initiated in the same way as a random read except that after the IN24LC02B
transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a
random read. This directs the IN24LC02B to transmit the next sequentially addressed 8 bit word
(see Figure 11).
To provide sequential reads the IN24LC02B contains an internal address pointer which is
incremented by one at the completion of each operation. This address pointer allows the entire
memory contents to be serially read during one operation.
Noise Protection
The IN24LC02B employs a Vcc threshold detector circuit which disables the internal erase/write
logic if the Vcc is below 1,5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to
assure proper device operation even on a noisy bus.
8
IN24LC02B
Figure 11. Sequential read
PIN DESCRIPTIONS
SPA Serial Address/Data Input/Output
This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an
open drain terminal, therefore the SDA bus requires a puliup resistor to Vcc (typical 10KΩ for 100
kHz, 1 KΩ for 400 kHz).
For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high
are reserved for indicating the START and STOP conditions.
SCL Serial Clock
This input is used to synchronize the data transfer from and to the device.
WP
This pin must be connected to either Vss or Vcc.
If tied to Vss, normal memory operation is enabled (read/write the entire memory).
If tied to Vcc, WRITE operations are inhibited. The entire memory will be write-protected. Read
operations are not affected.
This feature allows the user to use the IN24LC02B as a serial ROM when WP is enabled (tied to
Vcc).
A0,A1,A2
These pins are not used by the IN24LC02B. They may be left floating or tied to either Vss or Vcc.
9
IN24LC02B
N SUFFIX PLASTIC DIP
(MS – 001BA)
A
Dimension, mm
5
8
B
1
4
MIN
MAX
A
8.51
10.16
B
6.1
7.11
5.33
C
L
F
Symbol
C
D
0.36
0.56
F
1.14
1.78
-T- SEATING
PLANE
N
G
M
K
0.25 (0.010) M
J
H
D
T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
G
2.54
H
7.62
J
0°
10°
K
2.92
3.81
L
7.62
8.26
M
0.2
0.36
N
0.38
D SUFFIX SOIC
(MS - 012AA)
Dimension, mm
A
8
5
B
H
1
G
P
4
D
K
MIN
MAX
A
4.8
5
B
3.8
4
C
1.35
1.75
D
0.33
0.51
F
0.4
1.27
R x 45
C
-T-
Symbol
SEATING
PLANE
J
F
0.25 (0.010) M T C M
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B ‑ 0.25 mm (0.010) per side.
M
G
1.27
H
5.72
J
0°
8°
K
0.1
0.25
M
0.19
0.25
P
5.8
6.2
R
0.25
0.5
10
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