Renesas M64895BGP I2c bus frequency synthesizer for tv/vtr Datasheet

M64895BGP
I2C BUS FREQUENCY SYNTHESIZER FOR TV/VTR
REJ03F0018–0100Z
Rev.1.0
Aug.27.2003
Description
The M64895BGP is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR using I2C
BUS control. It contains the prescaler with operating up to 1.3 GHz, 4 band drivers and tuning. amplifier for direct
tuning.
Features
•
•
•
•
•
•
•
•
•
4 integrated PNP band drivers (Io = 40 mA, Vsat = 0.2 V typ@Vcc 1 to 13.2 V)
Built in tuning Amplifier for direct tuning.
Low power dissipation (Icc = 20 mA, Vcc = 5 V)
Built-in prescaler with input amplifier (fmax = 1.3 GHz)
PLL lock/unlock status display output (Built-in pull up resistor)
I2C bus control (write mode only)
X 3type of tuning steps (Division ratio 1/512, 1/640, 1/1024) with 4 MHz X’tal
Programmable chip address
Small package (16 Pin SSOP)
Application
• TV, VCR tuners
Block Diagram
XIN
ADS
16
15
OSC
S DA
14
S CL
13
LD
Vcc3
12
11
V tu
V in
10
9
I 2 C BUS RELIEVER
2
DIV
10
MA IN COU NTER
LOCK
DE TECTOR
AMP
PHASE
DETECTOR
CHARGE
PUMP
1/ 32,1/ 33
5
SWALLOW COU NTER
4
P.O
RESET
1/ 8
BAND DRIVER
BIAS
AMP
1
2
3
4
5
f IN
GND
V cc1
V cc2
B S4
Rev.1.0, Aug.27 2003, page 1 of 11
6
B S3
7
B S2
8
B S1
M64895BGP
Pin Configuration (TOP VIEW)
PRESCALER INPUT
GND
fin
GND
1
16
Xin
CRYSTAL OSCILLATOR
2
15
ADS
CHIP ADDRESS INPUT
SUPPLY VOLTAGE 1
Vcc1
3
14
SDA
DATAINPUT
SUPPLY VOLTAGE 2
Vcc2
4
13
SCL
CLOCK INPUT
BS4
5
12
LD
Lock OUTPUT
BS3
6
11
Vcc3
SUPPLY VOLTAGE 3
BS2
7
10
Vtu
TUNING OUTPUT
BS1
8
9
Vin
FILTER INPUT
BAND SWITCHING
OUTPUTS
OUTLINE 16P2Z
Pin Description
Symbol
Pin
No.
Pin name
Function
fin
GND
Vcc1
1
2
3
Prescaler input
GND
Power supply voltage 1
Input for the VCO frequency.
Ground to 0 V
Power supply voltage terminal. 5.0 V+/–0.5 V
Vcc2
BS4
BS3
BS2
BS1
4
Power supply voltage 2
Power supply for band switching. Vcc1 to 13.2 V
5
6
7
8
Band switching outputs
PNP open collector method is used.
When the band switching data is “H”, the output is “ON”.
When it is “L”, the output is “OFF”.
Vin
9
Filter input
(Charge pump output)
This is the output terminal for the LPF input and charge pump output.
When the phase of the programmable divider output (f1/N) is ahead
compared to the reference frequency (fref), the “source” current state
becomes active. If it is lag, the “sink” current becomes active.
If the phases are the same, the high impedance state becomes active.
Vtu
Vcc3
LD/ftest
10
11
12
Tuning output
Power supply voltage 3
Lock detect/Test port
This supplies the tuning voltage.
Power supply voltage for tuning voltage 28 to 35 V
Lock detector is output. Programmable freq. Divider output and reference
freq. output is selected by the test mode.
SCL
SDA
13
14
Clock input
Data input
Data is read into the shift register when the clock signal falls.
Input for band SW and programmable frequency. divider set falls.
ADS
X in
15
16
Address switching input
This is connected to
theCrystal oscillator.
Chip address sets it up with the input condition of terminal.
4.0 MHz crystal oscillator connected.
Rev.1.0, Aug.27 2003, page 2 of 11
M64895BGP
Method of setting DATA
The input information of chip address and data of 2 or 4 bytes are received in I2C bus receiver. It shows a de definition
of bus protocol admitted in the following.
1_STA
2_STA
3_STA
4_STA
CA CB BB STO
CA D1 D2 STO
CA CB BB D1 D2 STO
CA D1 D2 CB BB STO
STA: Start condition
STO: Stop condition
CA: Chip address
CB: Control data byte
BB: Band S.W. data byte
D1: Divider data byte
D2: Divider data byte
The information of 5 bytes required for circuit operation are chip address, control data and band S.W.data of 2 bytes
and divider data of 2 bytes. After the chip address input, 2 or 4 bytes can be received. Function bit contained the first
and the third data byte to distinguish between divider data and control data band S.W. data, and ”0” goes ahead of
divider data and “1” goes ahead of control data, band S.W. data,
The timing reading data show in under figure. Divider data uses 15 bits is read in at the rise of the eighth bit clock
signal of the second byte divider data (D2). Control data (CB) and band SW-data (BB) is each read in the rise of eighth
bits clock signal.
SDA
D1
address
D2
1
SCL
STA
8
D1&D2
1
CB
8
Read into
latch
1
Read into
latch
BB
1
8
8
STO
Read into
latch
Write mode format
Byte
MSB
1
Address Byte
1
1
0
0
0
MA1
MA0
0
A
LSB
2
3
4
Divider Byte 1
Divider Byte 2
Control Byte 1
0
N7
1
N14
N6
CP
N13
N5
T2
N12
N4
T1
N11
N3
T0
N10
N2
RSa
N9
N1
RSb
N8
N0
OS
A
A
A
5
Band SW Byte
X
X
X
X
BS4
BS3
BS2
BS1
A
Rev.1.0, Aug.27 2003, page 3 of 11
M64895BGP
Mode data set up method
X: Random, 0 or 1. normal “0”
MA1, MAO: programmable Address Bit
Address input voltage
MA1
0 to 0.1 *Vcc1
0
MA
0
Always valid
0.4*Vcc1 to 0.6*Vcc1
0.9*Vcc1 to Vcc1
0
1
1
1
0
1
N14 to NO: How to set dividing ratio of the programmable the divider
Dividing ratio N = N14 (214 = 16384) +… +N0 (20 = 1)
Therefore, the rage of division N is 1,024 to 32,768
(Example) frvco = fref*8*N
= 3.90625 * 8 * N
= 31.25 * N (kHz)
CP: Setting up the charge pump current of the phase comparator
CP
Charge pump current
Mode
0
70µA
Test
1
270µA
Normal
T2, T1, T0: Setting up for the test mode
T2
T1
T0
Charge pump
12 pin condition
Mode
0
0
1
1
1
1
0
1
1
1
0
0
X
X
0
1
0
1
Normal operation
High impedance
Sink
Source
High impedance
High impedance
Lock output
Lock output
Lock output
Lock output
fref output
f1/N output
Normal operation
Test
Test
Test
Test
Test
Rev.1.0, Aug.27 2003, page 4 of 11
M64895BGP
RSa, RSb: Set up for the reference Frequency division ratio
RSa
RSb
division ratio
1
1
1/512
0
X
1
0
1/1024
1/640
OS: Set up the tuning amplifier
OS
Tuning voltage output
Mode
0
1
ON
OFF
Normal
Test
Power on rest operation (Initial state the power is turned ON)
BS4 to BS1
:OFF
Charge pump
: High impedance
Tuning amplifier
: OFF
Charge pump current
: 270 µA
Frequency division ratio : 1/1024
Lock detector
:H
Rev.1.0, Aug.27 2003, page 5 of 11
M64895BGP
Timing diagram
[START]condition
SDA
tBUF
tLOW
tr
tf
tHDSTA
CL
tHD DAT
tHDSTA
[STOP] condition
t HIGH tSUDAT tSUSTA
[START]condition
Crystal oscillator connection diagram
16
18pF
4MHz
Rev.1.0, Aug.27 2003, page 6 of 11
Crystal oscillator characteristics
Actual resistance :less than300Ω
Load capacitance :20pF
tSUSTO
[STOP] condition
M64895BGP
Absolute maximum ratings
(Ta = –20°C to 75°C unless otherwise noted)
Parameter
Symbols
Max. ratings
Units
Conditions
Standby voltage1
Standby voltage2
Standby voltage3
Vcc1
Vcc2
Vcc3
6.0
14.4
36.0
V
V
V
Pin3
Pin4
Pin11
Input voltage
Output voltage
Voltage applied when
the band output current is OFF
VI
Vo
VBSOFF
6.0
6.0
14.4
V
V
V
Not to exceed Vcc1
Pin 12
Band output current
IBSON
50.0
mA
Per 1 band output circuit
ON the time when the band
output is ON
Power dissipation
Operating temperature
Storage temperature
tBSON
10
sec
Pd
Topr
Tstg
350
–20 to +75
–40 to +125
mW
°C
°C
50 mA per 1 band output circuit
3 circuits are pin at same time,
Ta = 75°C
Recommended operating conditions
(Ta = –20°C to 75°C unless otherwise noted)
Parameter
Symbols
Ratings
Units
Standby voltage1
Standby voltage2
Standby voltage3
Operating frequency (1)
Operating frequency (2)
Band output current 5 to 8
Vcc1
Vcc2
Vcc3
fopr1
fopr2
IBDL
4.5 to 5.5
5.0 to 13.2
30 to 35
4.0
80 to 1300
0 to 40
V
V
V
MHz
MHz
mA
Rev.1.0, Aug.27 2003, page 7 of 11
Conditions
Crystal oscillation circuit
Normally 1 circuit is on. 2 circuits on at
the same time is max. It is prohibited to
have 3 or more circuits turned on at the
same time.
M64895BGP
Electrical Characteristics
(Ta = –20°C to 75°C, Vcc1 = 5.0 V Vcc = 12 V, Vcc3 = 33 V, unless otherwise noted)
Parameters
Input terminals
“H” input voltage
“L” input voltage
“H” input current
“L” input current
SDA output
“L” output voltage
Leak current
Band SW
Output voltage
Leak current
Tuning output
Output voltage “H”
Output voltage “L”
Charge pump
“H” output current
“L” output current
Leak current
Supply current 1
Supply current 2
4circuits OFF
1 circuits ON,
Output open
Output current 40 mA
Supply current 3
Symbol
Test pin
Test conditions
Limits
Unit
Min
Typ
Max
—
—
—
–4/–14
Vcc1+0.3
1.5
10
–10/–30
V
V
µA
µA
VIH
VIL
IIH
IIL
13 to 14
13 to 14
13 to 14
13/14
Vcc1 = 5.5 V, Vi = 4.0 V
Vcc1 = 5.5 V, Vi = 0.4 V
3.0
—
—
—
VOL
ILO
14
14
Vcc1 = 5.5 V, lc = 3 mA
Vcc1 = 5.5 V, lc = 5.5 V
—
—
—
—
0.4
10
V
µΑ
VBS
lOIK1
5 to 8
5 to 8
Vcc2 = 12 V, lo = –40 mA
Vcc2 = 12 V, Band SW is OFF
Vo = 0 V
11.6
—
11.8
—
—
–10
V
µA
VtoH
VtoL
10
10
Vcc3 = 33 V
Vcc3 = 33 V
32.5
—
—
0.2
—
0.4
V
V
—
—
—
—
±270
±70
—
20
±370
±110
±50
30
µA
µA
nA
mA
—
—
0.3
mA
—
—
—
6.0
46.0
3.0
8.0
48.0
4.0
mA
mA
mA
IOH
IOL
IcpLK
ICC1
9
9
9
3
ICC2A
4
Vcc1 = 5.0 V, Vo = 2.5 V
Vcc1 = 5.0 V, Vo = 2.5 V
Vcc1 = 5.0 V, Vo = 2.5 V
Vcc1 = 5.5 V
Vcc2 = 12 V
ICC2B
ICC2C
ICC3
4
4
11
Vcc2 = 12 V
Vcc2 = 12 V, lo = –40 mA
Vcc2 = 33 V, Output ON
Note: The typical values are at Vcc1 = 5.0 V, Vcc 2 = 12 V, Vcc3 = 33 V, Ta = +25°C
Rev.1.0, Aug.27 2003, page 8 of 11
M64895BGP
Switching characteristics
(Ta = –20°C to 75°C, Vcc1 = 5.0 V, Vcc = 12 V, Vcc3 = 33 V, unless otherwise noted)
Parameter
Symbol
Test
pin
Test conditions
Limits
Min
Typ
Max
Prescaler operating
frequency
fopr
1
80
—
1300
MHz
Operating input
voltage
Vin
1
fSCL
13
–24
–27
–30
–27
–18
0
—
—
—
—
—
—
4
4
4
4
4
100
dBm
Clock pulse
frequency
Vcc1 = 4.5 to 5.5 V
Vin = Vinmin to Vinmax
Vcc1 = 4.5 to 5.5 V
80 to 100 MHz
100 to 200 MHz
200 to 800 MHz
800 to 1000 MHz
1000 to 1300 MHz
Vcc1 = 4.5 to 5.5 V
Bus free time
Data hold time
SCL low hold time
SCL high hold time
Set up time
tBUF
tHDSTA
tLOW
tHIGH
tSUSTA
14
13
13
13
13,
14
Vcc1 = 4.5 to 5.5 V
Vcc1 = 4.5 to 5.5 V
Vcc1 = 4.5 to 5.5 V
Vcc1 = 4.5 to 5.5 V
Vcc1 = 4.5 to 5.5 V
4.7
4
4.7
4
4.7
—
—
—
—
—
—
—
—
—
µs
µs
µs
µs
µs
Data hold time
tHDDAT
13,
14
Vcc1 = 4.5 to 5.5 V
0
—
—
s
Data set up time
tSUDAT
13,
14
Vcc1 = 4.5 to 5.5 V
250
—
—
ns
Rise time
tR
13,
14
Vcc1 = 4.5 to 5.5 V
—
—
1000
ns
Fall time
tF
13,
14
Vcc1 = 4.5 to 5.5 V
—
—
300
ns
Set up time
tSUSTO
13,
14
Vcc1 = 4.5 to 5.5 V
4
—
—
µs
Rev.1.0, Aug.27 2003, page 9 of 11
Unit
used
kHz
M64895BGP
Application example
BUILT-IN PLL TUNER
+5 V
+
10µ
-
1nF
Vcc1to 12 V
UHF VHF
3
Vcc1
ADS
15
Vcc2
BS4
BS3
BS2
BS1
M 64895BGP
+B
4
BS3
6
BS2
4-BAND
TUNER
IF
IF
7
BS1
8
1000 pF
f in
MCU
BS4
5
Lo
1
SDA
1nF
14
1nF
13
SCL
Vin
12
LOCK
Xin
Vtu
VT
9
10
GND Vcc3
16
18p
2
11
4MHz
+33 V
BT
Rev.1.0, Aug.27 2003, page 10 of 11
AGC
1.5n
0.1u
56K
56K
2.2n
AFT
* 100P
Note) Filter constant is for reference.
*Touch a capacitance because
Filter circuit is instability.
AGC
HE
G
Z1
e
EIAJ Package Code
SSOP16-P-225-0.65
E
Rev.1.0, Aug.27 2003, page 11 of 11
1
16
z
D
Detail G
y
8
9
b
JEDEC Code
−
MMP
x
F
M
A
Weight(g)
0.08
x
L1
Detail F
A2
c
A1
Lead Material
Cu Alloy
e1
A
A1
A2
b
c
D
E
e
HE
L
L1
z
Z1
x
y
Symbol
b2
e1
I2
b2
Dimension in Millimeters
Min
Nom
Max
1.9
−
−
−
−
0.05
−
1.5
−
0.32
0.22
0.17
0.2
0.15
0.13
5.2
5.0
4.8
4.6
4.4
4.2
−
−
0.65
6.5
6.2
5.9
0.6
0.4
0.2
−
−
0.9
−
0.225
−
−
−
0.375
−
−
0.13
0.1
−
−
0˚
0°
−
−
−
0 35
−
−
5.72
−
−
1.27
Recommended Mount Pad
e
Plastic 16pin 225mil SSOP
I2
16P2Z-A
M64895BGP
Package Dimensions
L
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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