Cypress CY62128ELL-45SXI 1-mbit (128k x 8) static ram Datasheet

CY62128E MoBL®
1-Mbit (128K x 8) Static RAM
Functional Description[1]
Features
The CY62128E is a high performance CMOS static RAM
organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99% when deselected (CE1 HIGH
or CE2 LOW). The eight input and output pins (IO0 through
IO7) are placed in a high impedance state when the device is
deselected (CE1 HIGH or CE2 LOW), the outputs are disabled
(OE HIGH), or a write operation is in progress (CE1 LOW and
CE2 HIGH and WE LOW)
• Very high speed: 45 ns
• Temperature ranges
— Industrial: –40°C to +85°C
— Automotive-A: –40°C to +85°C
— Automotive-E: –40°C to +125°C
• Voltage range: 4.5V–5.5V
• Pin compatible with CY62128B
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 4 µA (Industrial)
• Ultra low active power
•
•
•
•
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight
IO pins (IO0 through IO7) is then written into the location
specified on the address pins (A0 through A16).
— Typical active current: 1.3 mA @ f = 1 MHz
Easy memory expansion with CE1, CE2 and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC,
and 32-pin TSOP I packages
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins appears on
the IO pins.
Logic Block Diagram
IO0
IO1
SENSE AMPS
ROW DECODER
INPUT BUFFER
128K x 8
ARRAY
IO2
IO3
IO4
IO5
IO6
POWER
DOWN
IO7
A16
A12
A13
OE
A14
COLUMN DECODER
WE
A15
CE1
CE2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05485 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 07, 2007
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CY62128E MoBL®
Pin Configuration[2]
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
32-Pin SOIC
Top View
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
IO0
IO1
IO2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
IO7
IO6
IO5
IO4
IO3
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
TSOP I
Top View
(not to scale)
25
26
27
26
28
29
30
31
32
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
STSOP
Top View
(not to scale)
OE
A10
CE1
IO7
IO6
IO5
IO4
IO3
GND
IO2
IO1
IO0
A0
A1
A2
A3
OE
A10
CE1
IO7
IO6
IO5
IO4
IO3
GND
IO2
IO1
IO0
A0
A1
A2
A3
Product Portfolio
Power Dissipation
Product
Range
Speed
(ns)
VCC Range (V)
Operating ICC (mA)
f = 1MHz
Min
Typ[3]
Max
CY62128ELL
Ind’l/Auto-A
4.5
5.0
5.5
CY62128ELL
Auto-E
4.5
5.0
5.5
45
[4]
55
f = fmax
Standby ISB2 (µA)
Typ[3]
Max
Typ[3]
Max
Typ[3]
Max
1.3
2
11
16
1
4
1.3
4
11
35
1
30
Notes
2. NC pins are not connected on the die.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
4. When used with a 100 pF capacitive load and resistive loads as shown on page 4, access times of 55 ns (tAA, tACE) and 25 ns (tDOE) are guaranteed.
Document #: 38-05485 Rev. *E
Page 2 of 11
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CY62128E MoBL®
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Static Discharge Voltage........................................... > 2001V
(MIL-STD-883, Method 3015)
Latch up Current..................................................... > 200 mA
Operating Range
Supply Voltage to Ground
Potential ...............................–0.5V to 6.0V (VCC(max) + 0.5V)
DC Voltage Applied to Outputs
in High-Z State[5, 6] ...............–0.5V to 6.0V (VCC(max) + 0.5V)
Device
Ambient
Temperature
Range
CY62128ELL Ind’l/Auto-A
Auto-E
VCC[7]
–40°C to +85°C 4.5V to 5.5V
–40°C to +125°C
DC Input Voltage[5, 6] ...........–0.5V to 6.0V (VCC(max) + 0.5V)
Electrical Characteristics (Over the Operating Range)
Parameter
Description
Test Conditions
45 ns (Ind’l/Auto-A)
Min
Typ[3]
Max
Typ[3]
Unit
Max
VOH
Output HIGH
Voltage
IOH = –1 mA
VOL
Output LOW
Voltage
IOL = 2.1 mA
VIH
Input HIGH Voltage VCC = 4.5V to 5.5V
2.2
VCC + 0.5
2.2
VCC + 0.5
V
VIL
–0.5
0.8
–0.5
0.8
V
IIX
Input LOW voltage VCC = 4.5V to 5.5V
Input Leakage
GND < VI < VCC
Current
–1
+1
–4
+4
µA
IOZ
Output Leakage
Current
GND < VO < VCC, Output Disabled
–1
+1
–4
+4
µA
ICC
VCC Operating
Supply Current
f = fmax = 1/tRC VCC = VCC(max)
IOUT = 0 mA
f = 1 MHz
CMOS levels
mA
Automatic CE
Power down
Current—CMOS
Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = VCC(max)
ISB2 [8]
2.4
55 ns (Auto-E)
Min
2.4
V
0.4
0.4
11
16
11
35
1.3
2
1.3
4
1
4
1
30
V
µA
Capacitance (For all Packages) [9]
Parameter
CIN
Description
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Max
10
Unit
pF
10
pF
Notes
5. VIL(min) = –2.0V for pulse durations less than 20 ns.
6. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
8. Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05485 Rev. *E
Page 3 of 11
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CY62128E MoBL®
Thermal Resistance[9]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
SOIC
Package
STSOP
Package
TSOP
Package
Unit
48.67
32.56
33.01
°C/W
25.86
3.59
3.42
°C/W
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
AC Test Loads and Waveforms
R1
VCC
OUTPUT
ALL INPUT PULSES
3.0V
30 pF
R2
INCLUDING
JIG AND
SCOPE
90%
10%
90%
10%
GND
Rise Time = 1 V/ns
Equivalent to:
Fall Time = 1 V/ns
THEVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
R1
Value
1800
Unit
Ω
R2
990
Ω
RTH
639
Ω
VTH
1.77
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
VDR
VCC for Data Retention
ICCDR [8]
Data Retention Current
tCDR [9]
Chip Deselect to Data
Retention Time
tR [10]
Operation Recovery
Time
Conditions
Min
Typ[3]
Max
Unit
4
µA
30
µA
2
VCC= VDR, CE1 > VCC − 0.2V or CE2 < 0.2V,
VIN > VCC - 0.2V or VIN < 0.2V
V
Ind’l/Auto-A
Auto-E
0
ns
tRC
ns
Data Retention Waveform[11]
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 2.0V
VCC(min)
tR
CE
Notes
10. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
11. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH.
Document #: 38-05485 Rev. *E
Page 4 of 11
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CY62128E MoBL®
Switching Characteristics (Over the Operating Range)[12]
Parameter
45 ns (Ind’l/Auto-A)
Description
Min
Max
55 ns (Auto-E)
Min
Max
Unit
Read Cycle
tRC
Read Cycle Time
45
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW and CE2 HIGH to Data Valid
45
55
ns
tDOE
OE LOW to Data Valid
22
25
ns
45
10
[13]
tLZOE
OE LOW to Low-Z
tHZOE
OE HIGH to
CE1 HIGH or CE2 LOW to
tPU
CE1 LOW and CE2 HIGH to Power Up
Write
20
ns
ns
0
45
ns
ns
10
0
CE1 HIGH or CE2 LOW to Power Down
ns
20
18
ns
ns
5
10
High-Z[13, 14]
tHZCE
tPD
55
18
CE1 LOW and CE2 HIGH to Low-Z
ns
10
5
High-Z[13, 14]
[13]
tLZCE
55
55
ns
Cycle[15]
tWC
Write Cycle Time
45
55
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
35
40
ns
tAW
Address Setup to Write End
35
40
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Setup to Write Start
0
0
ns
tPWE
WE Pulse Width
35
40
ns
tSD
Data Setup to Write End
25
25
ns
tHD
Data Hold from Write End
0
0
ns
tHZWE
tLZWE
WE LOW to
High-Z[13, 14]
WE HIGH to
Low-Z[13]
18
10
20
10
ns
ns
Notes
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3ns (1V/ns) or less, timing reference levels of 1.5V, input pulse
levels of 0 to 3V, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4.
13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
14. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
15. The internal Write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 38-05485 Rev. *E
Page 5 of 11
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CY62128E MoBL®
Switching Waveforms
Read Cycle 1 (Address Transition Controlled) [16, 17]
tRC
RC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled) [11, 17, 18]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
tHZCE
tLZOE
HIGH IMPEDANCE
DATA OUT
DATA VALID
tLZCE
tPD
tPU
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
50%
50%
ICC
ISB
Write Cycle No. 1 (WE Controlled) [11, 15, 19, 20]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
OE
tSD
DATA IO
NOTE 21
tHD
DATA VALID
tHZOE
Notes:
16. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
17. WE is HIGH for read cycle.
18. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.
19. Data IO is high impedance if OE = VIH.
20. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
21. During this period, the IOs are in output state and input signals must not be applied.
Document #: 38-05485 Rev. *E
Page 6 of 11
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CY62128E MoBL®
Switching Waveforms (continued)
Write Cycle No. 2 (CE1 or CE2 Controlled) [11, 15, 19, 20]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tSD
DATA IO
tHD
DATA VALID
Write Cycle No. 3 (WE Controlled, OE LOW) [11, 20]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tSD
NOTE 21
DATA IO
tHD
DATA VALID
tLZWE
tHZWE
Truth Table
CE1
CE2
WE
OE
H
X
X
X
High-Z
Deselect/Power down
Standby (ISB)
X
L
X
X
High-Z
Deselect/Power down
Standby (ISB)
L
H
H
L
Data Out
Read
Active (ICC)
L
H
L
X
Data In
Write
Active (ICC)
L
H
H
H
High-Z
Selected, Outputs Disabled
Active (ICC)
Document #: 38-05485 Rev. *E
Inputs/Outputs
Mode
Power
Page 7 of 11
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CY62128E MoBL®
Ordering Information
Speed
(ns)
Ordering Code
45
45
55
Package
Diagram
Operating
Range
Package Type
CY62128ELL-45SXI
51-85081 32-pin 450-Mil SOIC (Pb-free)
CY62128ELL-45ZAXI
51-85094 32-pin STSOP (Pb-free)
CY62128ELL-45ZXI
51-85056 32-pin TSOP Type I (Pb-free)
CY62128ELL-45SXA
51-85081 32-pin 450-Mil SOIC (Pb-free)
CY62128ELL-45ZXA
51-85094 32-pin TSOP Type I (Pb-free)
CY62128ELL-55SXE
51-85081 32-pin 450-Mil SOIC (Pb-free)
CY62128ELL-55ZAXE
51-85094 32-pin STSOP (Pb-free)
Industrial
Automotive-A
Automotive-E
Contact your local Cypress sales representative for availability of these parts.
Package Diagrams
Figure 1. 32-pin (450 Mil) Molded SOIC, 51-85081
16
1
0.546[13.868]
0.566[14.376]
0.440[11.176]
0.450[11.430]
17
32
0.793[20.142]
0.817[20.751]
0.006[0.152]
0.012[0.304]
0.101[2.565]
0.111[2.819]
0.118[2.997]
MAX.
0.004[0.102]
0.050[1.270]
BSC.
0.004[0.102]
MIN.
0.014[0.355]
0.020[0.508]
SEATING PLANE
Document #: 38-05485 Rev. *E
0.047[1.193]
0.063[1.600]
0.023[0.584]
0.039[0.990]
51-85081-*B
Page 8 of 11
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CY62128E MoBL®
Package Diagrams (continued)
Figure 2. 32-pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094
51-85094-*D
Document #: 38-05485 Rev. *E
Page 9 of 11
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CY62128E MoBL®
Package Diagrams (continued)
Figure 3. 32-pin Thin Small Outline Package Type I (8 x 20 mm), 51-85056
51-85056-*D
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company
names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05485 Rev. *E
Page 10 of 11
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62128E MoBL®
Document History Page
Document Title: CY62128E MoBL® 1-Mbit (128K x 8) Static RAM
Document Number: 38-05485
REV.
Orig. of
ECN NO. Issue Date Change
Description of Change
**
203120
See ECN
AJU
New data sheet
*A
299472
See ECN
SYT
Converted from Advance Information to Preliminary
Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns, respectively
Changed tDOE from 15 ns to 18 ns for 35 ns speed bin
Changed tHZOE, tHZWE from 12 and 15 ns to 15 and 18 ns for the 35 and 45 ns
speed bins, respectively
Changed tHZCE from 12 and 15 ns to 18 and 22 ns for the 35 and 45 ns speed bins,
respectively
Changed tSCE from 25 and 40 ns to 30 and 35 ns for the 35 and 45 ns speed bins,
respectively
Changed tSD from 15 and 20 ns to 18 and 22 ns for the 35 and 45 ns speed bins,
respectively
Added Pb-free package information
Added footnote #9
Changed operating range for SOIC package from Commercial to Industrial
Modified signal transition time from 5 ns to 3 ns in footnote #11
Changed max of ISB1, ISB2 and ICCDR from 1.0 µA to 1.5 µA
*B
461631
See ECN
NXR
Converted from Preliminary to Final
Included Automotive Range and 55 ns speed bin
Removed 35 ns speed bin
Removed “L” version of CY62128E
Removed Reverse TSOP I package from Product offering
Changed ICC (Typ) from 8 mA to 11 mA and ICC (max) from 12 mA to 16 mA for f = fmax
Changed ICC (max) from 1.5 mA to 2.0 mA for f = 1 MHz
Removed ISB1 DC Specs from Electrical characteristics table
Changed ISB2 (max) from 1.5 µA to 4 µA
Changed ISB2 (Typ) from 0.5 µA to 1 µA
Changed ICCDR (max) from 1.5 µA to 4 µA
Changed the AC Test load Capacitance value from 100 pF to 30 pF
Changed tLZOE from 3 to 5 ns
Changed tLZCE from 6 to 10 ns
Changed tHZCE from 22 to 18 ns
Changed tPWE from 30 to 35 ns
Changed tSD from 22 to 25 ns
Changed tLZWE from 6 to 10 ns
Updated the Ordering Information Table
*C
464721
See ECN
NXR
Updated the Block Diagram on page # 1
*D
563144
See ECN
AJU
Added footnote 4 on page 2
*E
1024520
See ECN
VKN
Added Automotive-A information
Converted Automotive-E specs to final
Added footnote #9 related to ISB2 and ICCDR
Updated Ordering Information table
Document #: 38-05485 Rev. *E
Page 11 of 11
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