Revised April 2005
74LVX374
Low Voltage Octal D-Type Flip-Flop with
3-STATE Outputs
General Description
Features
The LVX374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and
3-STATE outputs for bus-oriented applications. A buffered
Clock (CP) and Output Enable (OE) are common to all flipflops. The inputs tolerate up to 7V allowing interface of 5V
systems to 3V systems.
■ Input voltage translation from 5V to 3V
■ Ideal for low power/low noise 3.3V applications
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX374M
74LVX374SJ
74LVX374MTC
Package Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
© 2005 Fairchild Semiconductor Corporation
DS011612
Description
D0–D7
Data Inputs
CP
Clock Pulse Input
OE
3-STATE Output Enable Input
O0–O7
3-STATE Outputs
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74LVX374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
October 1993
74LVX374
Truth Table
Inputs
Dn
H
L
X
Outputs
CP
OE
On
L
H
L
L
X
H
Z
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
LOW-to-HIGH Transition
Functional Description
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops.
The LVX374 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Recommended Operating
Conditions (Note 2)
0.5V to 7.0V
Supply Voltage (VCC )
DC Input Diode Current (IIK)
VI
Supply Voltage (VCC)
0.5V
20 mA
0.5V to 7V
DC Input Voltage (VI)
VO
0.5V
VCC 0.5V
DC Output Voltage (VO)
0V to 5.5V
Output Voltage (VO)
DC Output Diode Current (IOK)
VO
2.0V to 3.6V
Input Voltage (VI)
0V to VCC
40qC to 85qC
Operating Temperature (TA)
20 mA
20 mA
0.5V to VCC 0.5V
Input Rise and Fall Time ('t/'V)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
DC Output Source
r25 mA
or Sink Current (IO)
DC VCC or Ground Current
r75 mA
65qC to 150qC
(ICC or IGND)
Storage Temperature (TSTG)
Power Dissipation
0 ns/V to 100 ns/V
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
180mW
DC Electrical Characteristics
Symbol
VIH
Parameter
HIGH Level
Input Voltage
VIL
VOH
VOL
IOZ
VCC
2.0
TA
Min
25qC
Typ
TA
Max
40qC to 85qC
Min
1.5
Max
3.0
2.0
2.0
3.6
2.4
2.4
Conditions
V
LOW Level
2.0
0.5
Input Voltage
3.0
0.8
0.8
3.6
0.8
0.8
0.5
HIGH Level
2.0
1.9
2.0
1.9
Output Voltage
3.0
2.9
3.0
2.9
3.0
2.58
V
VIN
V
VIH
or VIL
2.48
LOW Level
2.0
0.0
Output Voltage
3.0
0.0
3-STATE Output
Units
1.5
0.1
0.1
VIN
0.1
0.1
3.0
0.36
0.44
V
3.6
r0.25
r2.5
VIH
or VIL
VIN
IOH
50PA
IOH
50PA
IOH
4mA
IOL
50PA
IOL
50PA
IOL
4mA
VIH or VIL
PA
VOUT
IIN
Input Leakage Current
3.6
r0.1
r1.0
PA
VIN
5.5V or GND
ICC
Quiescent Supply Current
3.6
4.0
40.0
PA
VIN
VCC or GND
Off-State Current
VCC or GND
Noise Characteristics (Note 3)
Symbol
VCC
Parameter
(V)
TA
Typ
25qC
Units
CL (pF)
50
Limit
VOLP
Quiet Output Maximum Dynamic VOL
3.3
0.5
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
3.3
0.5
0.8
V
50
VIHD
Minimum HIGH Level Dynamic Input Voltage
3.3
2.0
V
50
VILD
Maximum LOW Level Dynamic Input Voltage
3.3
0.8
V
50
Note 3: Input tr
tf
3 ns
3
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74LVX374
Absolute Maximum Ratings(Note 1)
74LVX374
AC Electrical Characteristics
Symbol
fMAX
VCC
Parameter
Maximum Clock
Propagation Delay Time
tPHL
CP to On
3-STATE Output
tPZH
Enable Time
2.7
60
115
45
60
40
3.3 r 0.3
100
160
85
60
95
55
2.7
3-STATE Output
tPHZ
Disable Time
tW
CP Pulse
tH
Setup Time
Min
Max
Conditions
MHz
CL
15 pF
CL
50 pF
CL
15 pF
CL
50 pF
1.0
19.5
CL
15 pF
11.0
19.8
1.0
23.0
CL
50 pF
6.7
10.6
1.0
12.5
CL
15 pF
9.2
14.1
1.0
16.0
CL
50 pF
7.6
14.5
1.0
17.5
CL
15 pF, RL
1 k:
10.1
18.0
1.0
21.0
CL
50 pF, RL
1 k:
5.9
9.3
1.0
11.0
CL
15 pF, RL
1 k:
8.4
12.8
1.0
14.5
CL
50 pF, RL
1 k:
2.7
11.5
18.5
1.0
22.0
CL
50 pF, RL
1 k:
3.3 r 0.3
9.6
13.2
1.0
15.0
CL
50 pF, RL
1 k:
CL
50 pF
2.7
7.5
8.0
3.3 r 0.3
5.0
5.5
2.7
6.5
6.5
Dn to CP
3.3 r 0.3
4.5
4.5
Hold Time
2.7
2.0
2.0
Dn to CP
3.3 r 0.3
2.0
ns
ns
ns
ns
2.0
Output to Output
2.7
1.5
1.5
tOSHL
Skew (Note 4)
3.3
1.5
1.5
|tPLHm tPLHn|, tOSHL
ns
ns
tOSLH
Note 4: Parameter guaranteed by design. tOSLH
Units
50
16.3
2.7
Width
tS
Max
8.5
3.3 r 0.3
tPLZ
40qC to 85qC
TA
Typ
3.3 r 0.3
tPZL
25qC
Min
Frequency
tPLH
TA
(V)
ns
|tPHLm tPHLn|
Capacitance
Symbol
TA
Parameter
Min
25qC
TA
Typ
Max
10
40qC to 85qC
Min
Max
10
Units
CIN
Input Capacitance
4
COUT
Output Capacitance
6
pF
CPD
Power Dissipation
32
pF
Capacitance (Note 5)
Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
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4
pF
74LVX374
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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74LVX374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
74LVX374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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