Panasonic AN12979A Stereo btl amplifier ic with built-in agc (i2c bus-control correspondence) Datasheet

DATA SHEET
Part No.
AN12979A
Package Code No.
ULGA020-L-0404
Publication date: October 2008
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AN12979A
Contents
„ Overview
……..……………………………………………………………………………………………………. 3
„ Features
……..……………………………………………………………………………………………………. 3
„ Applications
„ Package
„ Type
………………………………………………………………………………………………………. 3
…………………………………...………………………………………………………………………. 3
…………….………………………………………………………………………………………………… 3
„ Application Circuit Example (Block Diagram) ……….…………………………………………………………. 4
„ Pin Descriptions
…………………..………………………………………………………………………………. 5
„ Absolute Maximum Ratings
……………………..……………..…………………………......………………… 6
„ Operating Supply Voltage Range …………………………………………..……………………………………. 6
„ Electrical Characteristics
………………….………………….…………………………………………………. 7
„ Electrical Characteristics (Reference values for design)
„ Technical Data
„ Usage Notes
……………………………………………………. 9
…………………………………….………….…………………………………………………. 10
……….……………………….………………….…………………………………………………. 21
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AN12979A
AN12979A
Stereo BTL amplifier IC with built-in AGC (I2C bus-control correspondence)
„ Overview
AN12979A is the stereo BTL amplifier which contained the AGC circuit for clip prevention of a speaker output.
This IC performs a mode change by the I2C bus control system. (Standby function ON/OFF change etc.)
„ Features
y Selection by I2C bus control is possible in the on-level of AGC. (3-bit, 8-step)
y Selection by I2C bus control is possible in an attack/recovery time of AGC. (attack: 2-bit, recovery: 3-bit)
y The resistance and the capacitor of a detector circuit which were being used for the conventional AGC are unnecessary.
y In order to realize high efficiency of output power, it adopts CMOS power amplifier circuit .
y Built-in compulsion shutdown terminal.
„ Applications
y Audio amplifier for mobile, such as a cellular phone
„ Package
y 20 pin Fine Pitch Land Grid Array Package (LGA Type)
„ Type
y Bi-CMOS IC
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AN12979A
„ Application Circuit Example (Block Diagram)
VCC
3V
1 μF
1 μF
1 μF
ROUT (Positive)
15
14
13
VREF
12
11
TEST VREFSP
PREOUT-R
16
100 pF
0.1 μF
10
+
-
17
+6 dB
9
AGC
+14 dB
10 kΩ FB-R
IN(R)
GND
IN(L)
10 kΩ
+
FB-L
-
19
10 kΩ
100 pF
VCC_SP
20
+14 dB
I2C-BUS
Control
SD
*
1 μF
AGC
+6 dB
1
VCC_D
3V
8
7
PREOUT-L
ROUT
(Negative)
DET
18
±0 dB
0.1 μF
SPEAKER
8Ω
+14 dB
±0 dB
10 kΩ
GND_SPR
2
0.1 μF
3
SCL
LOUT
(Negative)
6
GND_SPL
SPEAKER
8Ω
+14 dB
4
5
SDA
Operate
LOUT (Positive)
1 μF
2.2 kΩ 2.2 kΩ
Shut-down
1 pin Operate voltage
VCC_D = 1.8 V
VCC_D
Operate
> 1.62 V
VCC_D = 2.6 V
Operate
> 2.34 V
Shut-down
< 0.18 V
Shut-down
< 0.26 V
1.8 V
Note) 1. This circuit and these circuit constants show an example and do not guarantee the design as a mass-production set.
2. *: The threshold voltage at 1pin has the VCC_D dependency.
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AN12979A
„ Pin Descriptions
Pin No.
Pin name
Type
Description
1
S.D
—
2
SCL
Input
SCL
3
SDA
Input / Output
SDA
4
VCC_D
Power Supply
Power supply VCC_D for logic circuit
5
LOUT_POS
Output
SP amp L-ch. output (+)
6
GND_SPL
Ground
Ground for SP L-ch. amp system
7
LOUT_NEG
Output
SP amp L-ch. output (–)
8
VCC_SP
9
ROUT_NEG
Output
SP amp R-ch. output (–)
10
GND_SPR
Ground
Ground for SP R-ch. amp system
11
ROUT_POS
Output
SP amp R-ch. output (+)
12
VREF_SP
13
TEST1
14
VCC
Power Supply
15
VREF
Input
16
PREOUT_R
17
FB_R
Input
18
GND
Ground
19
FB_L
Input
20
PREOUT_L
Power Supply
Input
—
Output
Output
Terminal for shut-down (VCC: operate, GND: shut-down)
Power supply VCC_SP for SP output
Terminal of reference voltage for SP output circuit
Terminal for testing (please connect to Ground)
Power supply VCC
Terminal of reference voltage
First stage amplifier output R-ch.
Negative feedback input stage amplifier R-ch.
Ground
Negative feedback input stage amplifier L-ch.
First stage amplifier output L-ch.
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AN12979A
„ Absolute Maximum Ratings
A No.
1
Parameter
Supply voltage
Symbol
Rating
VCC
3.6
VCC_D
3.6
VCC_SP
5.0
Unit
Note
V
*1
2
Supply current
ICC
—
A
3
Power dissipation
PD
222
mW
4
Operating ambient temperature
Topr
–20 to +70
°C
5
Storage temperature
Tstg
–55 to +150
°C
*2
*3
Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
*2: The power dissipation shown is the value at Ta = 70°C for the independent (unmounted) IC package without a heat sink.
When using this IC, refer to the • PD – Ta diagram in the „ Technical Data and use under the condition not exceeding the allowable value.
*3: Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25°C.
„ Operating Supply Voltage Range
Parameter
Supply voltage range
Symbol
Range
VCC
2.7 to 3.3
VCC_D
VCC_SP
1.7 to 2.6
1.7 to 3.3
Unit
V
Note
*1
*2
2.7 to 4.5
Note) 1. The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
2. *1: The values under FAST- mode.
*2: The values under STANDARD- mode.
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AN12979A
„ Electrical Characteristics at VCC = 3.0 V , VCC_D = 1.8 V , VCC_SP = 3.0 V
Note) Ta = 25°C±2°C unless otherwise specified.
B
No.
Parameter
Symbol
Conditions
Limits
Min
Typ
Max
Unit
No
te
Circuit Current
1
Circuit current 1A at non-signal
(VCC)
IVCC1A
VCC = 3.0 V, Non-signal
STB = OFF, SP = ON, AGC = ON
1.5
3.9
6.0
mA
2
Circuit current 2A at non-signal
(VCC_SP)
IVCC2A
VCC_SP = 3.0 V, Non-signal
STB = OFF, SP = ON, AGC = ON
1.0
13
29
mA
3
Circuit current 3A at non-signal
(VCC_D)
IVCC3A
VCC_D = 1.8V, Non-signal
STB = OFF, SP = ON, AGC = ON
⎯
0.1
10
μA
4
Circuit current 1B at non-signal
(VCC)
IVCC1B
VCC = 3.0 V, Non-signal
STB = ON, SP = OFF, AGC = ON
⎯
0.1
1.0
μA
5
Circuit current 2B at non-signal
(VCC_SP)
IVCC2B
VCC_SP = 3.0 V, Non-signal
STB = ON, SP = OFF, AGC = ON
⎯
0.1
1.0
μA
6
Circuit current 3A at non-signal
(VCC_D)
IVCC3B
VCC_D = 1.8V, Non-signal
STB = ON, SP = OFF, AGC = ON
⎯
0.1
1.0
μA
7
Circuit current 1C at non-signal
(VCC)
IVCC1C
VCC = 3.0 V, Non-signal
STB = OFF, SP = OFF, AGC = ON
1.5
3.7
6.0
mA
8
Circuit current 1C at non-signal
(VCC_SP)
IVCC2C
VCC_SP = 3.0 V, Non-signal
STB = OFF, SP = OFF, AGC = ON
⎯
0.3
1.0
mA
9
Circuit current 1C at non-signal
(VCC_D)
IVCC3C
VCC_D = 1.8 V, Non-signal
STB = OFF, SP = OFF, AGC = ON
⎯
0.1
10
μA
VSPOL
VSPOR
Vin = –34.0 dBV, f = 1 kHz
RL = 8 Ω
–9.5
–8.0
–6.5
dBV
12 SP reference output distortion
THSPOL
THSPOR
Vin = –34.0 dBV, f = 1 kHz
RL = 8 Ω , to THD5th
⎯
0.07
0.5
%
13 SP reference output noise voltage
VNSPOL Non-Signal
VNSPOR using A curve filter
⎯
–75
–68
dBV
14 SP maximum rating output
VMSPOL THD = 10%, f = 1 kHz
VMSPOR RL = 8 Ω , AGC = OFF
300
500
⎯
mW
15 Output level at power save
VSSPOL
VSSPOR
⎯
–114
–90
dBV
Input/output characteristics
11 SP reference output level
Vin = –34.0 dBV, f = 1 kHz
RL = 8 Ω, using A curve filter
16 SP AGC output level 1
VSPOA1L Vin = –19.0 dBV, f = 1 kHz
VSPOA1R RL = 8 Ω, AGC-SELECT = [011]
3.0
4.0
5.0
dBV
17 SP AGC output level 2
VSPOA2L Vin = –12.0 dBV, f = 1 kHz
VSPOA2R RL = 8 Ω, AGC-SELECT = [011]
3.0
4.0
5.0
dBV
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AN12979A
„ Electrical Characteristics at VCC = 3.0 V , VCC_D = 1.8 V , VCC_SP = 3.0 V (continued)
Note) Ta = 25°C±2°C unless otherwise specified.
B
No.
Parameter
Symbol
Conditions
43 SCL,SDA signal input Low Level
VIL
44 SCL,SDA signal input Low Level
VIH
45 SDA output signal Low Level
VOL
46 SCL,SDA Signal Input Current
Ii
Limits
Unit
Min
Typ
Max
⎯
– 0.5
⎯
0.3 ×
VCC_D
V
⎯
0.7 ×
VCC_D
⎯
VCC_D
+ 0.5
V
0
⎯
0.2 ×
VCC_D
V
–10
⎯
10
μA
No
te
I2C interface
SCL maximum frequency of signal
input
Open corrector,
sync current: 3mA
Input voltage: 0.1 V to 1.7 V
fSCL
⎯
0
⎯
400
kHz
48 Shut-down input Low Level
Vsdlth
⎯
⎯
⎯
0.1 ×
VCC_D
V
49 Shut-down input High Level
Vsdhth
⎯
0.9 ×
VCC_D
⎯
⎯
V
47
The threshold voltage at 1-pin
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AN12979A
„ Electrical Characteristics (Reference values for design) at VCC = 3.0 V , VCC_D = 1.8 V, VCC_SP = 3.0 V
Note) Ta = 25°C±2°C unless otherwise specified.
The characteristics listed below are reference values derived from the design of the IC and are not guaranteed by inspection.
If a problem does occur related to these characteristics, we will respond in good faith to user concerns.
B
No.
Parameter
Symbol
Conditions
tBUF
Limits
Unit
No
te
⎯
μs
*1
Min
Typ
Max
⎯
1.3
⎯
I2C interface
66
Bass free time between a condition
of stop and a condition of start
67
Setup time of a condition of start
tSU;STA
⎯
0.6
⎯
⎯
μs
*1
68
Hold time of a condition for satart
tHD;STA
⎯
0.6
⎯
⎯
μs
*1
69
"L" time of SCL clock
tLow
⎯
1.3
⎯
⎯
μs
*1
70
"H" time of SCL clock
tHigh
⎯
0.6
⎯
⎯
μs
*1
71
Rising time of SDA , SCL signal
tR
⎯
⎯
⎯
0.3
μs
*1
72
Fall time of SDA,SCL signal
tF
⎯
⎯
⎯
0.3
μs
*1
73
Data setup time
tSU;DAT
⎯
0.1
⎯
⎯
μs
*1
74
Data hold time
tHD;DAT
⎯
0
⎯
0.9
μs
*1
75
Rising up time of a condition of stop
tSU;STO
⎯
0.6
⎯
⎯
μs
*1
Note) *1: All values are VIHmin (*2) and VILmax (*3) level standard.
*2: VIHmin is the minimum limit of the signal input high level.
*3: VILmax is the maximum limit of the signal input low level.
START
CONDITION
Repeated START
CONDITION
STOP
CONDITION
START
CONDITION
VIHmin
(*2)
SDA
VILmax (*3)
tBUF
tR
tF
tLow
tR
tSU;DAT
tF
tHD;STA
SCL
tHD;STA
tHD;DAT
tHigh
tSU;STA
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AN12979A
„ Technical Data
y I2C-bus Mode
1. Write Mode
SDA
SCL
SLAVE
ADDRESS
START
CONDITION
ACK
1 0 1 1
0 1 1 0
B
6
SUB
ADDRESS
0 0 0 0
DATA
ACK
0 0 0 1
0
1
Example of transmission messages
ACK
1 0 0 0
0 0 0 0
8
0
STOP
CONDITION
Two transmission messages (i.e., the SCL and SDA) are sent in synchronous serial transmission. The SCL is a clock with fixed
frequency. The SDA indicates address data for the control of the reception side, and is sent in parallel in synchronization with the
SCL. The data is transmitted in 8-bit, 3 octets (bytes) in principle, where every octet has an acknowledge bit. The following
description provides information on the structure of the frame.
<Start Conditions>
When the level of the SDA changes to low from high while the level of the SCL is high, the data reception of the receiver
will be enabled.
<Stop Conditions>
When the level of the SDA changes to high from low while the level of the SCL is high, the data reception of the receiver
will be aborted.
<Slave Address>
The slave address is a specified one unique to each device. When the address of another device is sent, the reception will be
aborted.
<Sub Address>
The sub address is a specified one unique to each function.
<Data>
Data is information under control.
<Acknowledge Bit>
The acknowledge bit is used to enable the master to acknowledge the reception of data for each octet. The master
acknowledges the data reception of the receiver by transmitting a high-level signal to the receiver and receiving a low-level
signal returned from the receiver as shown by the dotted lines in Fig.
The communication will be aborted if the low signal is not returned.
The SDA will not change when the level of the SCL is high except start or stop conditions are enabled.
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AN12979A
„ Technical Data (continued)
y I2C-bus Mode (continued)
1. Write Mode (continued)
(a) I2C-bus PROTOCOL
x Slave address: 10110110 (B6Hex)
x Format (normal)
S
Slave address
W A
Start
condition
Sub address
A
Data byte
Acknowledge bit
Write
Mode: 0
A
P
Stop
condition
(b) Auto increment
x Sub-address 0*Hex: Auto increment mode
(When the data is sent in sequence, the sub address will change one by one and the data will be input.)
x Auto increment mode
S
Slave address
W A
Sub address
A
Data 1
A
Data 2
A
Data n
A
P
(c) Initial condition
The initial state of the device is not guaranteed. Therefore, the input of 00Hex resister-D0 (Note.1) will be absolutely 0, when
the power is turned ON.
(d) Sub-address Byte and Data Byte Format
Sub-address
*0Hex
*1Hex
*2Hex
Data byte
MSB
D3
D7
D6
D5
D4
*
*
0
(Note.2)
0
(Note.2)
AGC-ON AGC-ON
data bit3 data bit2
0
(Note.2)
AGC-ON
data bit1
0
(Note.2)
<00Hex Register>
D0, D4, D5, D6, D7: Always set to 0
D1: Standby ON/OFF switch
D2: SP Save ON/OFF switch
D3: AGC ON/OFF switch
<01Hex Register>
D0, D1 : AGC-attack-time selection
D2, D3, D4: AGC-recovery-time selection
D5, D6, D7: AGC-on-level selection
<02Hex Register>
D0 to D7: Always set to 0 (test&adjust mode)
0
(Note.2)
LSB
AGC
0 → OFF
1 → ON
D2
SP Save
0 → ON
1 → OFF
D1
Standby
0 → ON
1 → OFF
D0
0
(Note.1)
AGC-REC AGC-REC AGC-REC AGC-ATT AGC-ATT
data bit3
data bit2
data bit1
data bit2
data bit1
*
0
(Note.2)
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*
0
(Note.2)
0
(Note.2)
0
(Note.2)
Please use these bit only Data = "0“, because they are
used by our company’s final test and fine-tuning
AGC-on level.
Note that Data = "0" is Not shut-down mode.
11
AN12979A
„ Technical Data (continued)
y I2C-bus Mode (continued)
1. Write Mode (continued)
(e) AGC-attack-time selection
Write
01Hex Register
(f) AGC-recovery-time selection
Write
01Hex Register
Attack
time
Recovery
time
D4
D3
D2
0.5 ms
0
0
0
1.0 s
1
1 ms
0
0
1
1.5 s
1
0
2 ms
0
1
0
2.0 s
1
1
4 ms
0
1
1
3.0 s
1
0
0
4.0 s
1
0
1
6.0 s
1
1
0
8.0 s
1
1
1
12.0 s
D1
D0
0
0
0
(g) AGC-on-level selection (at VCC = 3.0 V, VCC_SP = 3.0 V)
Write
01Hex Register
AGC
On
Level
Output
Po ( RL = 8 W )
VCC_SP
(Recommend)
D7
D6
D5
0
0
0
1 dBV
157 mW
2.7 V ≤
0
0
1
2 dBV
198 mW
2.7 V ≤
0
1
0
3 dBV
249 mW
2.7 V ≤
0
1
1
4 dBV
314 mW
3.0 V ≤
1
0
0
5 dBV
395 mW
3.3 V ≤
1
0
1
6 dBV
498 mW
3.7 V ≤
1
1
0
7 dBV
626 mW
4.1 V ≤
1
1
1
8 dBV
789 mW
4.5 V
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AN12979A
„ Technical Data (continued)
y I2C-bus Mode (continued)
2. Read Mode
(a)I2C-bus PROTOCOL
x Slave address 10110111(B7Hex)
x Format
S
Slave address
R
A
Data 0
A
Data 1
A
Data 2
A
P
Read
Mode: 1
Note) At the slave address input, it is sequentially output from data 0.
There is no necessity for inputting the sub-address.
(b) Sub-address Byte and Data Byte Format
MSB
D7
Data byte
D6
D4
D5
LSB
D3
D2
D1
D0
Data 0
Sub address Sub address
*0Hex
*0Hex
Latch data
Latch data
[D6]
[D7]
Sub address
*0Hex
Latch data
[D5]
Sub address Sub address
*0Hex
*0Hex
Latch data
Latch data
[D3]
[D4]
Sub address
*0Hex
Latch data
[D2]
Sub address
*0Hex
Latch data
[D1]
Sub address
*0Hex
Latch data
[D0]
Data 1
Sub address Sub address
*1Hex
*1Hex
Latch data
Latch data
[D6]
[D7]
Sub address
*1Hex
Latch data
[D5]
Sub address Sub address
*1Hex
*1Hex
Latch data
Latch data
[D3]
[D4]
Sub address
*1Hex
Latch data
[D2]
Sub address
*1Hex
Latch data
[D1]
Sub address
*1Hex
Latch data
[D0]
Data 2
Sub address Sub address
*2Hex
*2Hex
Latch data
Latch data
[D6]
[D7]
Sub address
*2Hex
Latch data
[D5]
Sub address Sub address
*2Hex
*2Hex
Latch data
Latch data
[D3]
[D4]
Sub address
*2Hex
Latch data
[D2]
Sub address
*2Hex
Latch data
[D1]
Sub address
*2Hex
Latch data
[D0]
Purchase of Panasonic I2C components conveys a license under the Philips I2C patent right to use these components in an I2C
systems, provided that the system conforms to the I2C standard specification as defined by Philips.
y Operating temperature guarantee of I2C-bus Control
The performance in the ambient temperature of operation is guaranteed theoretically in the design at normal temperature (25°C) by
inspecting it at a speed of the clock that is about 50% earlier regarding the operating temperature guarantee of I2C-bus Control.
But the following characteristics are logical values derived from the design of the IC and are not guaranteed by inspection.
If a problem does occur related to these characteristics, Panasonic will respond in good faith to customer concerns.
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AN12979A
„ Technical Data (continued)
y I/O block circuit diagrams and pin function descriptions
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin
No.
Waveform
and voltage
Internal circuit
Description
VCC_D
Shut-down
1
1
IC is shut down by pin1 being shorted
to GND.(All I2C Data become 0.)
VCC_D to VCCを印加
1.8 V to 3.0 V
VCC_D
SCL
2
I2C-BUS SCL pin
2
Hi-Z
VCC_D
SDA
3
I2C-BUS SDA pin
3
Hi-Z
GND
VCC_D
4
-
Power supply pin for I2C-BUS
1.8 V(typ.)
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AN12979A
„ Technical Data (continued)
y I/O block circuit diagrams and pin function descriptions (continued)
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin
No.
Waveform
and voltage
Internal circuit
Description
VCC_SP
LOUT_POS
5
5
L-ch. positive speaker output pin
DC 1.45 V
400k
GND_SPL
6
GND_SPL
Ground pin for L-ch. speaker output
-
VCC_SP
LOUT_NEG
7
7
L-ch. negative speaker output pin
DC 1.45 V
400k
GND_SPL
VCC_SP
8
-
Power supply pin for speaker output
3.0 V(typ.)
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AN12979A
„ Technical Data (continued)
y I/O block circuit diagrams and pin function descriptions (continued)
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin
No.
Waveform
and voltage
Internal circuit
Description
VCC_SP
ROUT_NEG
9
9
R-ch. negative speaker output pin
DC 1.45 V
400k
GND_SPR
10
GND_SPR
GND pin for R-ch. speaker output
-
VCC_SP
ROUT_POS
11
11
R-ch. positive speaker output pin
DC 1.45 V
400k
GND_SPR
VCC_SP
10k
VREF_SP
12
DC 1.45 V
12
1k
150k
Reference voltage pin for output stage
150k
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AN12979A
„ Technical Data (continued)
y I/O block circuit diagrams and pin function descriptions (continued)
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin
No.
Waveform
and voltage
Internal circuit
Description
13
TEST1
Test mode pin
13
Hi-Z
Please connect to GND.
VCC
14
Power supply pin
-
3.0 V(typ.)
VCC
VREF
10k
15
DC 1.45 V
1k
15
Reference voltage pin
150k
150k
VCC
PREOUT_R
16
DC 1.45 V
10k
1k
SDE00031BEB
16
First stage amplifier R-ch. output pin
17
AN12979A
„ Technical Data (continued)
y I/O block circuit diagrams and pin function descriptions (continued)
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin
No.
Waveform
and voltage
Internal circuit
Description
17
FB_R
17
10k
Negative feedback pin for input stage
amplifier R-ch.
DC 1.45 V
18
GND
Ground pin
-
19
FB_L
19
10k
Negative feedback pin for input stage
amplifier L-ch.
DC 1.45 V
VCC
PREOUT_L
20
DC 1.45 V
10k
1k
SDE00031BEB
20
First stage amplifier L-ch. output pin
18
AN12979A
„ Technical Data (continued)
y Power supply and logic sequence
Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
The timing control of power-ON/OFF and each logic according to the procedure below should be recommended for the best pop
performance caused in switching.
1. The sequence of the power supply and each logic
The basic procedure at the power-on
Please first bring up the power supply,
and then the standby off.
VCC,VCC_SP,
VCC_D, SD
Power supply
Off
On
On
Off
Off
Standby
1. The power OFF condition
Both the standby and the SP_Save are in the ON
condition.
2. Power ON
3. Standby Off
4. SP_Save Off
Off
On
On
Off
Off
SP_Save
The basic procedure at the power-off
On
On
20 ms or more *
After at least 20 ms has passed after the
standby off, please off SP_Save.
0 ms or more
1. The power ON condition
Both the standby and the SP_Save are in the OFF
condition.
2. SP_Save On ( = Standby On)
3. Standby On
4. Power Off
Please control Standby On to simultaneous
with SP_Save On, or the back.
Note) *: This IC contains the pre-charge circuit. It is time until each bias is stabilized from Standby Off.
It depends for this time on the capacity value linked to a reference voltage terminal (VREF and VREFSP), and the capacity value and
resistance linked to an input terminal (IN_R and IN_L).
It is a recommendation value in a constant given in the example of „ Application Circuit Example (Block Diagram).
2.The sequence of VCC and VCC_SP and VCC_D
This IC have not a standup and falling order in VCC and VCC_SP.
A standup and falling time of VCC and VCC_SP recommend 1 or more ms.
VCC
VCC_SP
VCC_D
On
On
Off
Off
1 ms or more
1 ms or more
SDE00031BEB
19
AN12979A
„ Technical Data (continued)
y PD ⎯ Ta diagram
SDE00031BEB
20
AN12979A
„ Usage Notes
1. Please take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs such as SP
output pin (Pin5, Pin7, Pin9, Pin11 ) – power supply pin short, SP output pin(Pin5, Pin7, Pin9, Pin11 ) – GND short, or SP output
(Pin5, Pin7, Pin9, Pin11) -to-SP output-pin short (load short).
2. Please absolutely do not mount the IC in the reverse direction on to the printed-circuit-board.
It damaged when the electricity is turned on.
3. Please do not make it open, because the open SDpin(Pin1) is not fixed.
SDE00031BEB
21
Request for your special attention and precautions in using the technical information and
semiconductors described in this book
(1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and
regulations of the exporting country, especially, those with regard to security export control, must be observed.
(2) The technical information described in this book is intended only to show the main characteristics and application circuit examples
of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any
other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any
other company which may arise as a result of the use of technical information described in this book.
(3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office
equipment, communications equipment, measuring instruments and household appliances).
Consult our sales staff in advance for information on the following applications:
– Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support
systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body.
– Any applications other than the standard applications intended.
(4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product
Standards in advance to make sure that the latest specifications satisfy your requirements.
(5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions
(operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute
maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any
defect which may arise later in your equipment.
Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure
mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire
or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products.
(6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS,
thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which
damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages.
(7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company.
20080805
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