NSC MM74C195 4-bit register Datasheet

MM54C195/MM74C195 4-Bit Registers
General Description
Features
The MM54C195/MM74C195 CMOS 4-bit registers feature
parallel inputs, parallel outputs, J-K serial inputs, shift/load
control input and a direct overriding clear. The following two
modes of operation are possible:
Parallel Load
Shift in direction QA towards QD
Y
Medium speed operation
Y
Parallel loading is accomplished by applying the four bits of
data and taking the shift/load control of input low. The data
is loaded into the associated flip-flops and appears at the
outputs after the positive transition of the clock input. During
parallel loading, serial data flow is inhibited.
Serial shifting is accomplished synchronously when the
shift/load control input is high. Serial data for this mode is
entered at the J-K inputs. These inputs allow the first stage
to perform as a J-K, D, or T-type flip flop as shown in the
truth table.
Y
High noise immunity
Low power
Tenth power TTL compatible
Supply voltage range
Synchronous parallel load
Parallel inputs and outputs from each flip-flop
Direct overriding clear
J and K inputs to first stage
Complementary outputs from last stage
Positive-edge triggered clocking
Diode clamped inputs to protect against static charge
Y
Y
Y
Y
Y
Y
Y
Y
Y
8.5 MHz (typ.) with 10V
supply and 50 pF load
0.45 VCC (typ.)
100 nW (typ.)
Drive 2 LPTTL loads
3V to 15V
Applications
Y
Y
Y
Y
Automotive
Data terminals
Instrumentation
Medical electronics
Y
Y
Y
Y
Alarm systems
Remote metering
Industrial electronics
Computers
Schematic and Connection Diagrams
Pin 8 to GND
Pin 16 to VCC
TL/F/5902 – 1
Dual-In-Line Package
TL/F/5902 – 2
Top View
Order Number MM54C195 or MM74C195
C1995 National Semiconductor Corporation
TL/F/5902
RRD-B30M105/Printed in U. S. A.
MM54C195/MM74C195 4-Bit Registers
February 1988
Absolute Maximum Ratings (Note 1)
Voltage at any Pin
b 0.3V to VCC a 0.3V
Operating Temperature Range
MM54C195
MM74C195
b 65§ C to a 150§ C
Storage Temperature Range
Power Dissipation (PD)
Dual-In-Line
Small Outline
Operating VCC Range
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b 55§ C to a 125§ C
b 40§ C to a 85§ C
700 mW
500 mW
3V to 15V
18V
260§ C
Absolute Maximum VCC
Lead Temperature (Soldering, 10 sec.)
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS TO CMOS
VIN(1)
Logical ‘‘1’’ Input Voltage
VCC e 5V
VCC e 10V
VIN(0)
Logical ‘‘0’’ Input Voltage
VCC e 5V
VCC e 10V
VOUT(1)
Logical ‘‘1’’ Output Voltage
VCC e 5V
VCC e 10V
VOUT(0)
Logical ‘‘0’’ Output Voltage
VCC e 5V
VCC e 10V
IIN(1)
Logical ‘‘1’’ Input Current
VCC e 15V
IIN(0)
Logical ‘‘0’’ Input Current
VCC e 15V
ICC
Supply Current
VCC e 15V
3.5
8.0
V
V
1.5
2.0
4.5
9.0
V
V
0.005
b 1.0
V
V
0.5
1.0
V
V
1.0
mA
b 0.005
0.05
mA
300
mA
CMOS/LPTTL INTERFACE
VIN(1)
Logical ‘‘1’’ Input Voltage
54C VCC e 4.5V
74C VCC e 4.75V
VIN(0)
Logical ‘‘0’’ Input Voltage
54C VCC e 4.5V
74C VCC e 4.75V
VOUT(1)
Logical ‘‘1’’ Output Voltage
54C VCC e 4.5V, IO e b360mA
74C VCC e 4.75V, IO e b360mA
VOUT(0)
Logical ‘‘0’’ Output Voltage
54C VCC e 4.5V, IO e 360mA
74C VCC e 4.75V, IO e 360mA
VCC b 1.5
VCC b 1.5
V
V
0.8
0.8
2.4
2.4
V
V
V
V
0.4
0.4
V
V
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
ISOURCE
Output Source Current
VCC e 5V, VIN(0) e 0V
TA e 25§ C, VOUT e 0V
b 1.75
mA
ISOURCE
Output Source Current
VCC e 10V, VIN(0) e 0V
TA e 25§ C, VOUT e 0V
b 8.0
mA
ISINK
Output Sink Current
VCC e 5V, VIN(1) e 5V
TA e 25§ C, VOUT e VCC
1.75
mA
ISINK
Output Sink Current
VCC e 10V, VIN(1) e 10V
TA e 25§ C, VOUT e VCC
8.0
mA
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
2
AC Electrical Characteristics* TA e 25§ C, CL e 50 pF, unless otherwise noted
Parameter
Conditions
Typ
Max
Units
tpd
Symbol
Propagation Delay Time to a Logical ‘‘0’’ or
Logical ‘‘1’’ from Clock to Q or Q
VCC e 5V
VCC e 10V
Min
150
75
300
130
ns
ns
tpd
Propagation Delay Time to a Logical ‘‘0’’ or
Logical ‘‘1’’ from Clear to Q or Q
VCC e 5V
VCC e 10V
150
50
300
130
ns
ns
tS
Time Prior to Clock Pulse that Data
must be Present
VCC e 5V
VCC e 10V
80
35
200
70
ns
ns
tS
Time Prior to Clock Pulse that Shift/Load
must be Present
VCC e 5V
VCC e 10V
110
60
150
90
ns
ns
tH
Time After Clock Pulse that Data
must be Held
VCC e 5V
VCC e 10V
b 10
b 5.0
0
0
ns
ns
tW
Minimum Clear Pulse Width (tWL e tWH)
VCC e 5V
VCC e 10V
100
50
200
100
ns
ns
tW
Minimum Clear Pulse Width
VCC e 5V
VCC e 10V
90
40
130
60
ns
ns
tr, tf
Maximum Clock Rise and Fall Time
VCC e 5V
VCC e 10V
5.0
2.0
fMAX
Maximum Input Clock Frequency
VCC e 5V
VCC e 10V
2.0
5.5
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
ms
ms
3.0
8.5
MHz
MHz
(Note 2)
5.0
pF
(Note 3)
100
pF
*AC Parameters are guaranteed by DC correlated testing.
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note
AN-90.
Truth Table
Inputs AT tn
Guaranteed Noise Margin
as a Function of VCC
Outputs AT tn a 1
J
K
QA
QB
QC
QD
QD
L
L
H
H
H
L
H
L
QAn
L
H
QAn
QAn
QAn
QAn
QAn
QBn
QBn
QBn
QBn
QCn
QCn
QCn
QCn
QCn
QCn
QCn
QCn
Note: H e High Level, L e Low Level
tn e bit time before clock pulse
tn a 1 e bit time after clock pulse
QAn e State of QA at tn
TL/F/5902 – 3
3
Switching Time Waveforms
CMOS to CMOS
TTL to CMOS
TL/F/5902 – 4
TL/F/5902 – 5
4
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54C195J or MM74C195J
NS Package Number J16A
5
MM54C195/MM74C195 4-Bit Registers
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number MM54C195N or MM74C195N
NS Package Number N16E
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
National Semiconductor
Corporation
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Europe
Fax: (a49) 0-180-530 85 86
Email: cnjwge @ tevm2.nsc.com
Deutsch Tel: (a49) 0-180-530 85 85
English Tel: (a49) 0-180-532 78 32
Fran3ais Tel: (a49) 0-180-532 93 58
Italiano Tel: (a49) 0-180-534 16 80
National Semiconductor
Hong Kong Ltd.
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
National Semiconductor
Japan Ltd.
Tel: 81-043-299-2309
Fax: 81-043-299-2408
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Similar pages