ICST ICS9250YF-11-T Frequency timing generator for pentium ii/iii system Datasheet

Integrated
Circuit
Systems, Inc.
ICS9250-11
Frequency Timing Generator for PENTIUM II/III™ Systems
General Description
Features
The ICS9250-11 is a main clock synthesizer chip for Pentium
II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used
with a Direct Rambus Clock Generator (DRCG) chip such as
the ICS9212-01, 02, 03 and a PCI buffer 9112-17.
•
Spread Spectrum may be enabled by driving the SPREAD#
pin active. Spread spectrum typically reduces system EMI by
8dB to 10dB. This simplifies EMI qualification without
resorting to board design iterations or costly shielding. The
ICS9250-11 employs a proprietary closed loop design, which
tightly controls the percentage of spreading over process and
temperature variations.
The CPU/2 clocks are inputs to the DRCG.
•
•
Generates the following system clocks:
- 6 - CPU Clocks 100/133MHz (2.5V).
- 2 - CPU/2 output for synchronous memory
reference (2.5V).
- 4 - fixed frequency Clocks @ 66.6MHz (3.3V).
- 2 - fixed frequency Clocks @ 33.3MHz (3.3V).
- 6 - IOAPIC Clocks @ ¼ of CPUCLK or 16.667MHz,
synchronous to CPU Clock (2.5V)
- 1 - 48MHz Clock (3.3V)
- 2 - REF Clocks @ 14.31818MHz
0.5% typical down spread modulation on CPU, PCI,
IOAPIC, 3V66 and CPU/2 output clocks.
Uses external 14.318MHz crystal.
Block Diagram
X1
X2
OSC
PLL
Spread
Spectrum
SPREAD#
2
6
REF (0:1)
Pin Configuration
CPUCLK (0:5)
/2
/3
SEL 133/100#
SEL(0:1)
/4
C
o
n
t
r
o
l
6
IOAPIC(0:5)
/2
/2
/3
2
CPU/2 (0:1)
/2
4
3V66 (0:3)
/2
2
PLL2
3V33 (0:1)
48MHz
Power Groups:
VDDREF, GNDREF = REF, X1, X2
VDD66, GND66 = 3V66
VDD33, GND33 = 3V33
VDD48, GND48 = 48MHz
VDDCOR, GNDCOR = PLL Core
VDDLCPU, GNDLCPU = CPUCLK
VDDLCPU/2 , GNDLCPU/2 = CPU/2
VDDLAPIC, GNDAPIC = IOAPIC
9250-11 Rev C 3/20/00
Third party brands and names are the property of their respective owners.
56-pin SSOP
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
ICS9250-11
Pin Descriptions
Pin number
1, 52, 53
Pin name
GNDLAPIC
2, 3, 50, 51, 54, 55 IOAPIC (0:5)
4, 49, 56
5, 11
6
7
Type
PWR
OUT
VDDLAPIC
VDDREF
X1
X2
PWR
PWR
IN
OUT
REF0
OUT
FREQ_APIC#
OUT
REF1
OUT
TEST#
OUT
12, 19
VDD66
PWR
13, 14, 17, 18
3V66[0:3]
OUT
8, 15, 16, 23, 24
21, 22
25
26
27
28
GND
3V33MHz
VDDCOR
GND48
48MHz
VDD48
PWR
OUT
PWR
PWR
OUT
PWR
29
SEL 133/100#
IN
30, 31
SEL[0:1]
IN
32
SPREAD#
IN
33
VDDLCPU/2
PWR
34, 35
CPU/2[0:1]
OUT
9
10
36
GNDLCPU/2
37, 44, 45
GNDLCPU
38, 39, 42, 43, 46,
CPUCLK[0:5]
47
40, 41, 48
VDDLCPU
PWR
PWR
OUT
PWR
Description
Ground pin for the IOAPIC outputs.
2.5V clock outputs running divide synchronous with the CPU
(Host bus) clock frequency. The default APIC is running at ¼ of
CPUCLK frequency.
When FREQ_APIC is strapped low, the APIC is running at fixed
16.67 MHz.
If CPU = 133 MHz, APIC = CPU/8
If CPU = 100 MHz, APIC = CPU/6
Power pin for the IOAPIC outputs. 2.5V.
Power pin for REF clocks
XTAL_IN 14.318MHz crystal input
XTAL_OUT Crystal output
3.3V 14.318 MHz clock output. APIC clock strapping option for
fixed 16.67 MHz APIC clock outputs.
If FREQ_APIC# = 0, APIC Clock = 16.67 MHz
If FREQ_APIC# = Open, APIC Clock = CPU/4
3.3V 14.318MHz clock output.
TEST# is sampled low (external with 10k pulldown). All clock
outputs are Tri-State.
power pin for the 3V66 clocks.
66MHz outputs at 3.3V. These outputs are stopped when
CPU_STOP# is driven active..
Ground pin for 3V outputs.
3.3V Fixed 33MHz clock output.
3.3V power for PLL core.
Ground pin for the 48MHz output
Fixed 48MHz clock output. 3.3V
Power pin for the 48MHz output.
This selects the frequency for the CPU and CPU/2 outputs. High =
133MHz, Low=100MHz
Function select pins. See truth table for details.
Enables spread spectrum when active(Low). modulates all the CPU,
PCI, IOAPIC, 3V66 and CPU/2 clocks. Does not affect the REF and
48MHz clocks. 0.5% down spread modulation.
Power pin for the CPU/2 clocks. 2.5V
2.5V clock outputs at 1/2 CPU frequency. 66MHz or50MHz
depending on the state of the SEL 133/100# input pin.
Ground pin for the CPU/2 clocks.
Ground pin for the CPUCLKs
Host bus clock output at 2.5V. 133MHz or 100MHz depending on
the state of the SEL 133/100MHz.
Power pin for the CPUCLKs. 2.5V
2
ICS9250-11
Frequency Select:
SEL
SEL1
133/100#
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
SEL0
0
1
0
1
0
1
0
1
CPU
MHz
Tristate
N/A
100
100
TCLK/2
N/A
133.3
133.3
CPU/2
MHz
Tristate
N/A
50.00
50.00
TCLK/4
N/A
66.6
66.6
3V66
MHz
Tristate
N/A
66.6
66.6
TCLK/4
N/A
66.6
66.6
3V33
48
REF
MHz
MHz
MHz
Tristate Tristate Tristate
N/A
N/A
N/A
33.3
OFF
14.318
33.3
48
14.318
TCLK/8 TCLK/2 TCLK
N/A
NA
N/A
33.3
OFF
14.318
33.3
48
14.318
Power Management Features:
SEL 133/100#
SEL1
SEL0
Function
0
0
0
All outputs Tri- State
0
00
1
Reserved
0
1
0
Active 100 MHz, 48 MHz PLL inactive
0
1
1
Active 100 MHz, 48 MHz PLL active
1
0
0
Test Mode
1
0
1
Reserved
1
1
0
Active 133 MHz, 48 MHz PLL inactive
1
1
1
Active 133 MHz, 48 MHz PLL active
3
IOAPIC MHz
¼
¼
¼
¼
Tristate
N/A
CPUCLK/16.67
CPUCLK/16.67
TCLK/16
N/A
CPUCLK/16.67
CPUCLK/16.67
ICS9250-11
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Operating Supply
Current
SYMBOL
VIH
VIL
IIH
IIL1
IIL2
IDD3.3OP
IDD.25OP
Powerdown Current
Input Frequency
Pin Inductance
1
Input Capacitance
Transition time
1
Clk Stabilization
Delay
1
1
Skew
1
1
1
IDD3.3P D
IDD.25P D
Fi
CONDITIONS
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = Max loads; Select @ 100 MHz
TYP
MAX
VDD +0.3
0.8
5
-5
200
160
160
75
CL = Max loads; Select @ 133 MHz
CL = Max loads
Input address VDD or GND
VDD = 3.3 V
90
Logic Inputs
Output pin capacitance
X1 & X2 pins
Ttrans
To 1st crossing of target frequency
200
100
14.318
13.5
From VDD = 3.3 V to 1% target frequency
Output enable delay (all outputs)
Output disable delay (all outputs)
CPU @ 1.25V, 3V66 @ 1.5V
3V66 @ 1.5V, 3V33 @ 1.5V
CPU @ 1.25V, IOAPIC @ 1.25V
Guaranteed by design, not 100% tested in production.
4
1
1
0
1.5
1.0
UNITS
V
V
µA
µA
CL = Max loads; Select @ 133 MHz
CL = Max loads; Select @ 100 MHz
Lpin
CIN
COUT
CINX
TSTAB
tP ZH,tP ZL
tP HZ,tP LZ
TCP U-3V66
T3V66-3V33
TCP U-IOAP IC
MIN
2
VSS-0.3
18
mA
mA
µA
MHz
7
5
6
22.5
nH
pF
pF
pF
3
ms
3
8
8
1.5
3.5
3.0
ms
ns
ns
ns
ns
ns
ICS9250-11
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output High Voltage
Output Low Voltage
SYMBOL
VOH2B
VOL2B
Output High Current
IOH2B
Output Low Current
IOL2B
Rise Time
Fall Time
1
1
Duty Cycle
1
1
Skew window
Jitter, cycle-to-cycle
1
1
CONDITIONS
IOH = -12 mA
IOL = 12 mA
VOH @ MIN = 1.0 V
VOH @ MAX = 2.375 V
VOL @ MIN = 1.2 V
VOL @ MAX = 0.3 V
MIN
2
TYP
MAX UNITS
V
0.4
V
-27
-27
27
30
mA
mA
tr2B
VOL = 0.4 V, VOH = 2.0 V
0.4
1.6
ns
tf2B
VOH = 2.0 V, VOL = 0.4 V
0.4
1.6
ns
dt2B
VT = 1.25 V
45
55
%
tsk2B
VT = 1.25 V
175
ps
tjcyc-cyc2B
VT = 1.25 V
150
ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU/2
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output High Voltage
Output Low Voltage
SYMBOL
VOH2B
VOL2B
Output High Current
IOH2B
Output Low Current
IOL2B
Rise Time
Fall Time
1
1
Duty Cycle
1
1
Skew window
Jitter, cycle-to-cycle
1
1
CONDITIONS
IOH = -12 mA
IOL = 12 mA
VOH @ MIN = 1.0 V
VOH @ MAX = 2.375 V
VOL @ MIN = 1.2 V
VOL @ MAX = 0.3 V
MIN
2
TYP
MAX UNITS
V
0.4
V
-27
-27
27
30
mA
mA
tr2B
VOL = 0.4 V, VOH = 2.0 V
0.4
1.6
ns
tf2B
VOH = 2.0 V, VOL = 0.4 V
0.4
1.6
ns
dt2B
VT = 1.25 V
45
55
%
tsk2B
VT = 1.25 V
175
ps
tjcyc-cyc2B
VT = 1.25 V
250
ps
Guaranteed by design, not 100% tested in production.
5
ICS9250-11
Electrical Characteristics - 3V33
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output High Voltage
Output Low Voltage
SYMBOL
VOH1
VOL1
Output High Current
IOH1
Output Low Current
IOL1
Rise Time
Fall Time
1
1
Duty Cycle
1
1
Skew window
Jitter, cycle-to-cycle
1
1
CONDITIONS
IOH = -14.5 mA
IOL = 9.4 mA
VOH @ MIN = 1.0 V
VOH @ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
MIN
2.4
TYP
MAX UNITS
V
0.4
V
-33
-33
30
38
mA
mA
tr1
VOL = 0.4 V, VOH = 2.4 V
0.5
2.0
ns
tf1
VOH = 2.4 V, VOL = 0.4 V
0.5
2.0
ns
d t1
VT = 1.5 V
45
55
%
tsk1
VT = 1.5 V
250
ps
tjcyc-cyc1
VT = 1.5 V
250
ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output High Voltage
Output Low Voltage
SYMBOL
VOH1
VOL1
Output High Current
IOH1
Output Low Current
IOL1
Rise Time
Fall Time
1
1
Duty Cycle
1
1
Skew window
Jitter, cycle-to-cycle
1
1
CONDITIONS
IOH = -14.5 mA
IOL =9 mA
VOH @ MIN = 1.0 V
VOH @ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
MIN
2.4
TYP
MAX UNITS
V
0.4
V
-33
-33
30
38
mA
mA
tr1
VOL = 0.4 V, VOH = 2.4 V
0.5
2.0
ns
tf1
VOH = 2.4 V, VOL = 0.4 V
0.5
2.0
ns
d t1
VT = 1.5 V
45
55
%
tsk1
VT = 1.5 V
250
ps
tjcyc-cyc1
VT = 1.5 V
500
ps
Guaranteed by design, not 100% tested in production.
6
ICS9250-11
Electrical Characteristics - REF, 48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output High Voltage
Output Low Voltage
SYMBOL
VOH5
VOL5
Output High Current
IOH5
Output Low Current
IOL5
Rise Time
Fall Time
1
1
Duty Cycle
1
Jitter, cycle-to-cycle
Jitter, cycle-to-cycle
1
1
1
CONDITIONS
IOH = -16 mA
IOL = 9 mA
VOH @ MIN = 1.0 V
VOH @ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
MIN
2.4
TYP
MAX UNITS
V
0.4
V
-29
-23
29
27
mA
mA
tr5
VOL = 0.4 V, VOH = 2.4 V
1.0
4.0
ns
tf5
VOH = 2.4 V, VOL = 0.4 V
1.0
4.0
ns
d t5
VT = 1.5 V
45
55
%
tjcyc-cyc5
VT = 1.5 V, Fixed clocks
500
ps
tjcyc-cyc5
VT = 1.5 V, Ref clocks
1000
ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output High Voltage
Output Low Voltage
SYMBOL
VOH2B
VOL2B
Output High Current
IOH2B
Output Low Current
IOL2B
Rise Time
Fall Time
1
1
Duty Cycle
1
1
Skew window
Jitter, cycle-to-cycle
1
1
CONDITIONS
IOH = -12 mA
IOL = 12 mA
VOH @ MIN = 1.0 V
VOH @ MAX = 2.375 V
VOL @ MIN = 1.2 V
VOL @ MAX = 0.3 V
MIN
2
TYP
MAX UNITS
V
0.4
V
-27
-27
27
30
mA
mA
tr2B
VOL = 0.4 V, VOH = 2.0 V
0.4
1.6
ns
tf2B
VOH = 2.0 V, VOL = 0.4 V
0.4
1.6
ns
dt2B
VT = 1.25 V
45
55
%
tsk2B
VT = 1.25 V
250
ps
tjcyc-cyc2B
VT = 1.25 V
250
ps
Guaranteed by design, not 100% tested in production.
7
ICS9250-11
Pin 1
Index
Area
.093
DIA. PIN (Optional)
D/2
E/2
PARTING LINE
H
L
DETAIL “A”
TOP VIEW
BOTTOM VIEW
-eA2
B
c
SEE
DETAIL “A”
A
.004 C
-E-
END VIEW
SYMBOL
A
A1
A2
B
c
D
E
e
H
h
L
N
µ
SEATING
PLANE
-D-
COMMON DIMENSIONS
MIN.
NOM.
MAX.
.095
.102
.110
.008
.012
.016
.087
.090
.094
.008
.0135
.005
.010
See Variations
.291
.295
.299
0.025 BSC
.395
.420
.010
.013
.016
.020
.040
See Variations
0°
8°
SIDE VIEW
VARIATIONS
MIN.
.720
AD
-C-
A1
D
NOM.
.725
N
MAX.
.730
56
“For current dimensional specifications, see JEDEC 95.”
Dimensions in inches
56 Pin 300 mil SSOP Package
Ordering Information
ICS9250yF-11-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
8
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
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