Revised January 2003 100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator General Description Features The 100LVELT22 is a LVTTL/LVCMOS to differential LVPECL translator operating from a single +3.3V supply. ■ Typical propagation delay of 350 ps Both outputs of a differential pair should be terminated in 50Ω to VCC - 2.0V even if only one output is being used. If an output pair is unused both outputs can be left open (un-terminated). ■ Max ICC of 28 mA at 25°C The 100 series is temperature compensated. ■ <100 ps skew between outputs ■ When TTL input is left Open Q output defaults HIGH ■ Fairchild MSOP-8 package is a drop-in replacement to ON TSSOP-8 ■ Flow through pinout ■ Meets or exceeds JEDEC specification EIA/JESD78 IC latch-up test ■ Moisture Sensitivity Level 1 ■ ESD Performance: Human Body Model > 2000V Machine Model > 200V Ordering Code: Product Order Number Package Code Package Description Number Top Mark 100LVELT22M M08A KVT22 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 100LVELT22M8 (Preliminary) MA08D KR22 8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Logic Diagram Top View Pin Descriptions Pin Name Description Qn, Qn LVPECL Differential Outputs D0 , D1 LVTTL/LVCMOS Inputs VCC Positive Supply GND Ground © 2003 Fairchild Semiconductor Corporation DS500777 www.fairchildsemi.com 100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator January 2003 100LVELT22 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) 0.0V to +7.0V Input Voltage (VI) VI ≤ VCC 0.0V to +7.0V Recommended Operating Conditions VCC = 3.0V to 3.8V Power Supply Operating DC Output Current (IOUT) LVTTL/LVCMOS Input Voltage Continuous 50 mA Surge 0.0V to VCC −40°C to +85°C Free Air Operating Temperature (TA) 100 mA Storage Temperature (TSTG) −65°C to +150°C Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. LVPECL DC Electrical Characteristics VCC = 3.3V; GND = 0.0V (Note 2) Symbol −40°C Parameter Min 25°C Typ Max Min 85°C Typ Max 28 Min Typ 28 Max Units ICC Power Supply Current 29 mA VOH Output HIGH Voltage (Note 3) 2215 2420 2275 2420 2275 2420 mV VOL Output LOW Voltage (Note 3) 1470 1745 1490 1680 1490 1680 mV Note 2: Output parameters vary 1 to 1 with VCC. VCC can vary ±0.15V. Note 3: Outputs are terminated through a 50Ω resistor to VCC − 2.0V. Note: Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than 500LFPM maintained. LVTTL/LVCMOS DC Electrical Characteristics VCC = 3.3V; GND = 0.0V (Note 4) Symbol IIH TA = −40°C to 85°C Parameter Min Typ Input HIGH Current Units Max 20 µA 100 IIL Input LOW Current VIK Clamp Diode Voltage VIH Input HIGH Voltage VIL Input LOW Voltage −200 µA −1.2 V 2.0 Condition VIN = 2.7V VIN = VCC VIN = 0.5V IIN = −18 mA V 0.8 V Note 4: VCC can vary ±0.15V. Note: Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than 500LFPM maintained. AC Electrical Characteristics VCC = 3.3V; GND = 0.0V (Note 5) Symbol Parameter fMAX Maximum Toggle Frequency tJITTER Cycle-to-Cycle Jitter tPLH / tPHL Propagation Delay (Note 6) tSKEW Skew −40°C Min Typ 600 30 100 200 400 550 Note 5: VCC can vary ±0.15V. Note 6: Specifications for standard LVTTL input signal (see Figure 1). www.fairchildsemi.com 85°C Max Min 2 Max 600 30 100 200 500 Figure Number ps 350 600 30 100 400 200 Units MHz TBD 350 400 200 Typ TBD TBD 350 200 Typ TBD TBD 200 Output-to-Output Output Rise Time Q (20% to 80%) Min TBD Part-to-Part tr, tf 25°C Max 500 ps Figure 1 ps ns Figure 2 100LVELT22 Switching Waveforms FIGURE 1. LVTTL to Differential LVPECL Propagation Delay FIGURE 2. Differential Output Edge Rates 3 www.fairchildsemi.com 100LVELT22 Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M08A www.fairchildsemi.com 4 100LVELT22 3.3V Dual LVTTL/LVCMOS to Differential LVPECL Translator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide Package Number MA08D Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 5 www.fairchildsemi.com