Intersil AD7545AN 12-bit, buffered, multiplying cmos dac Datasheet

AD7545
12-Bit, Buffered, Multiplying CMOS DAC
August 1997
Features
Description
• 12-Bit Resolution
The AD7545 is a low cost monolithic 12-bit, CMOS
multiplying DAC with on-board data latches. Data is loaded
in a single 12-bit wide word which allows interfacing directly
to most 12-bit and 16-bit bus systems. Loading of the input
latches is under the control of the CS and WR inputs. A logic
low on these control inputs makes the input latches transparent allowing direct unbuffered operation of the DAC.
• Low Gain T.C. 2ppm/oC (Typ)
• Fast TTL/CMOS Compatible Data Latches
• Single +5V to +15V Supply
• Low Power
• Low Cost
• /883 Processed Versions Available
Ordering Information
PART NUMBER
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
AD7545JN
0 to 70
20 Ld PDIP
E20.3
AD7545KN
0 to 70
20 Ld PDIP
E20.3
AD7545AN
-40 to 85
20 Ld PDIP
E20.3
AD7545BN
-40 to 85
20 Ld PDIP
E20.3
Pinout
Functional Diagram
AD7545
(PDIP)
TOP VIEW
RFB
20
AD7545
R
OUT 1
1
20 RFB
AGND
2
19 VREF
DGND
3
18 VDD
DB11 (MSB)
4
17 WR
DB10
5
16 CS
DB9
6
15 DB0 (LSB)
DB8
7
14 DB1
DB7
8
13 DB2
DB6
9
12 DB3
DB5 10
11 DB4
VREF 19
12-BIT
MULTIPLYING DAC
1
OUT1
2
AGND
18
VDD
3
DGND
12
WR 17
INPUT DATA LATCHES
CS 16
12
DB11 - DB0
(PINS 4 - 15)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
10-10
File Number
3108.1
AD7545
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VDD to DGND) . . . . . . . . . . . . . . . . . . . -0.3V, +17V
Digital Input Voltage to DGND . . . . . . . . . . . . . . . .-0.3V, VDD +0.3V
VRFB , VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
VPIN1 to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V, VDD +0.3V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V, VDD +0.3V
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
Maximum Junction Temperature (PDIP Package) . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Ranges
Commercial (J, K, Grades) . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
Industrial (A, B, Grades) . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Extended (S Grades) . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
TA = See Note 2, VREF = +10V, VOUT1 = 0V, AGND = DGND, Unless Otherwise Specified
VDD = +5V
PARAMETER
MIN
TEST CONDITIONS
TYP
VDD = +15V
MAX
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
12
12
Bits
J, A, S
-
-
±2
-
-
±2
LSB
K, B
-
-
±1
-
-
±1
LSB
-
-
±4
-
-
±4
LSB
-
-
±1
-
-
±1
LSB
-
-
±20
-
-
±25
LSB
Gain Error is Adjustable
Using the Circuits of
Figures 4 and 5 (Note 3)
-
-
±10
-
-
±15
LSB
Gain Temperature Coefficient
∆Gain/∆Temperature
Typical Value is 2ppm/oC for
VDD = +5V (Note 4)
-
-
±5
-
-
±10
ppm/oC
DC Supply Rejection
∆Gain/∆VDD
∆VDD = ±5%
0.015
-
0.03
0.01
-
0.02
%
-
-
50
-
-
50
nA
-
-
50
-
-
50
nA
-
-
200
-
-
200
nA
-
-
2
-
-
2
µs
-
-
300
-
-
250
ns
Relative Accuracy
Differential Nonlinearity
J, A, S 10-Bit Monotonic TMIN to TMAX
K, B
Gain Error
(Using Internal RFB)
J, A, S DAC Register Loaded with
1111 1111 1111
K, B
Output Leakage Current
at OUT1
12-Bit Monotonic TMIN to TMAX
J, K
A, B
DB0 - DB11 = 0V; WR,
CS = 0V (Note 2)
S
DYNAMIC CHARACTERISTICS
Current Setting Time
To 1/2 LSB, OUT1 LOAD = 100Ω,
DAC Output Measured from
Falling Edge of WR, CS = 0V
(Note 4)
Propagation Delay from Digital Input OUT1 LOAD = 100Ω,
Change to 90% of Final Analog
CEXT = 13pF (Notes 4 and 5)
Output
Digital to Analog Glitch Impulse
VREF = AGND
-
400
-
-
250
-
nV/s
AC Feedthrough at OUT1
VREF = ±10V, 10kHz Sinewave
(Note 6)
-
5
-
-
5
-
mVP-P
DB0 - DB11 = 0V,
WR, CS = 0V (Note 4)
-
-
70
-
-
70
pF
DB0 - DB11 = VDD ,
WR, CS = 0V (Note 4)
-
-
200
-
-
200
pF
ANALOG OUTPUTS
Output Capacitance
COUT1
COUT1
10-11
AD7545
Electrical Specifications
TA = See Note 2, VREF = +10V, VOUT1 = 0V, AGND = DGND, Unless Otherwise Specified (Continued)
VDD = +5V
VDD = +15V
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Input Resistance
TC = -300ppm/oC (Typ)
7
-
-
7
-
-
kΩ
Typical Input Resistance = 11kΩ
-
-
25
-
-
25
kΩ
2.4
-
-
-
-
13.5
V
PARAMETER
TEST CONDITIONS
REFERENCE INPUT
Input Resistance (Pin 19 to GND)
DIGITAL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
-
-
0.8
-
-
1.5
V
±1
-
±10
±1
-
±10
µA (Max)
VIN = 0 (Note 4)
-
-
7
-
-
7
pF
VIN = 0 (Note 4)
-
-
20
-
-
20
pF
380
200
-
200
120
-
ns
-
Input Current, IIN
VIN = 0 or VDD (Note 7)
Input Capacitance
DB0 - DB11
WR, CS
SWITCHING CHARACTERISTICS (Note 4)
Chip Select to Write Setup Time, tCS See Figure 1
Chip Select to Write Hold Time, tCH See Figure 1
0
-
-
0
-
Write Pulse Width, tWR
tCS ≥ tWR , tCH ≥ 0, See Figure 1
400
175
-
240
100
ns
Data Setup Time, tDS
See Figure 1
210
100
-
120
60
-
ns
Data Hold Time, tDH
See Figure 1
10
-
-
10
-
-
ns
All Digital Inputs VIL or VIH
-
-
2
-
-
2
mA
All Digital Inputs 0V or VDD
-
100
500
-
100
500
µA
All Digital Inputs 0V or VDD
-
10
-
-
10
-
µA
ns
POWER SUPPLY CHARACTERISTICS
IDD
NOTES:
2. Temperature Ranges as follows: J, K versions:
0oC to 70oC
A, B versions: -20oC to 85oC
S version:
-55oC to 125oC
o
TA = 25 C for TYP Specifications. MIN and MAX are measured over the specified operating range.
3. This includes the effect of 5ppm maximum gain TC.
4. Parameter not tested. Parameter guaranteed by design, simulation, or characterization.
5. DB0 - DB11 = 0V to VDD or VDD to 0V in plastic and sidebraze package.
6. Feedthrough can be further reduced by connecting the metal lid on the ceramic package to DGND.
7. Logic inputs are MOS gates. Typical input current (25oC) is less than 1nA.
8. Typical values are not guaranteed but reflect mean performance specification.
Specifications subject to change without notice.
Timing Diagrams
tCH
CHIP
SELECT
tCH
VDD
tCS
CHIP
SELECT
VDD
tCS
0
WRITE
tWR
VDD
tDH
tDS
DATA IN
(DB0 - DB11)
0
WRITE
0
VDD
tDH
tDS
VDD
DATA VALID
tWR
DATA IN
(DB0 - DB11)
0
FIGURE 1A. TYPICAL WRITE CYCLE
DATA VALID
FIGURE 1B. PREFERRED WRITE CYCLE
FIGURE 1. WRITE CYCLE TIMING DIAGRAM
10-12
0
VDD
0
AD7545
equal to the value “R”). Since RIN at the VREF pin is constant,
the reference terminal can be driven by a reference voltage or a
reference current, AC or DC, of positive or negative polarity. (If a
current source is used, a low temperature coefficient external
RFB is recommended to define scale factor).
MODE SELECTION
WRITE MODE:
HOLD MODE:
CS and WR low, DAC responds
to data bus (DB0 - DB11) inputs
Either CS or WR high, data bus
(DB0 - DB11) is locked out; DAC
holds last data present when
WR or CS assumed high state.
Circuit Information - Digital Section
Figure 4 shows the digital structure for one bit. The digital
signals CONTROL and CONTROL are generated from CS
and WR.
NOTES:
9. VDD = +5V; tr = tf = 20ns
10. VDD = +15V; tr = tf = 40ns
11. All input signal rise and fall times measured from 10% to 90% of
VDD .
TO AGND SWITCH
TO OUT1 SWITCH
12. Timing measurement reference level is (VIH + VIL)/2.
13. Since input data latches are transparent for CS and WR both
low, it is preferred to have data valid before CS and WR both go
low. This prevents undesirable changes at the analog output
while the data inputs settle.
INPUTS
CONTROL
Circuit Information - D/A Converter Section
Figure 2 shows a simplified circuit of the D/A converter
section of the AD7545. Note that the ladder termination
resistor is connected to AGND. R is typically 11kΩ.
The binary weighted currents are switched between the OUT1
bus line and AGND by N-Channel switches, thus maintaining a
constant current in each ladder leg independent of the switch
state. One of the current switches is shown in Figure 3.
VREF
R
R
R
2R
2R
2R
R
2R
2R
2R
DB1
The input buffers are simple CMOS inverters designed such
that when the AD7545 is operated with VDD = 5V, the buffers
convert TTL input levels (2.4V and 0.8V) into CMOS logic
levels. When VIN is in the region of 2.0V to 3.5V the input
buffers operate in their linear region and draw current from
the power supply. To minimize power supply currents it is
recommended that the digital input voltages be as close to
the supply rails (VDD and DGND) as is practically possible.
Output Offset
AGND
DB9
FIGURE 4. DIGITAL INPUT STRUCTURE
Application
OUT1
DB10
CONTROL
The AD7545 may be operated with any supply voltage in the
range 5V ≤ VDD ≤ 15V. With VDD = +15V the input logic
levels are CMOS compatible only, i.e., 1.5V and 13.5V.
RFB
DB11
(MSB)
BUFFERS
CMOS current-steering D/A converters exhibit a code
dependent output resistance which in turn causes a code
dependent amplifier noise gain. The effect is a code dependent differential nonlinearity term at the amplifier output
which depends on VOS where VOS is the amplifier input
offset voltage. To maintain monotonic operation it is recommended that VOS be no greater than (25 x 10-6) (VREF) over
the temperature range of operation.
DB0
(LSB)
FIGURE 2. SIMPLIFIED D/A CIRCUIT OF AD7545
TO LADDER
FROM
INTERFACE
LOGIC
General Ground Management
AGND
OUT1
FIGURE 3. N-CHANNEL CURRENT STEERING SWITCH
The capacitance at the OUT1 bus line, COUT1, is code
dependent and varies from 70pF (all switches to AGND) to
200pF (all switches to OUT1).
The input resistance at VREF (Figure 2) is always equal to
RLDR (RLDR is the R/2R ladder characteristic resistance and is
AC or transient voltages between AGND and DGND can
cause noise injection into the analog output. The simplest
method of ensuring that voltages at AGND and DGND are
equal is to tie AGND and DGND together at the AD7545. In
more complex systems where the AGND and DGND connection is on the backplane, it is recommended that two
diodes be connected in inverse parallel between the AD7545
AGND and DGND pins (1N914 or equivalent).
Digital Glitches
When WR and CS are both low the latched are transparent
and the D/A converter inputs follow the data inputs. In some
10-13
AD7545
bus systems, data on the data bus is not always valid for the
whole period during which WR is low and as a result invalid
data can briefly occur at the D/A converter inputs during a
write cycle. Such invalid data can cause unwanted glitches
at the output of the D/A converter. The solution to this problem, if it occurs, is to retime the write pulse (WR) so that it
only occurs when data is valid.
The choice of the operational amplifiers in Figure 4 and Figure
5 depends on the application and the trade off between
required precision and speed. Below is a list of operational
amplifiers which are good candidates for many applications.
The main selection criteria for these operational amplifiers is to
have low VOS , low VOS drift, low bias current and low settling
time.
Another cause of digital glitches is capacitive coupling from
the digital lines to the OUT1 and AGND terminals. This
should be minimized by isolating the analog pins of the
AD7545 (pins 1, 2, 19, 20) from the digital pins by a ground
track run between pins 2 and 3 and between pins 18 and 19
of the AD7545. Note how the analog pins are at one end of
the package and separated from the digital pins by VDD and
DGND to aid isolation at the board level. On-chip capacitive
coupling can also give rise to crosstalk from the digital to
analog sections of the AD7545, particularly in circuits with
high currents and fast rise and fall times. This type of
crosstalk is minimized by using VDD = +5V. However, great
care should be taken to ensure that the +5V used to power
the AD7545 is free from digitally induces noise.
These amplifiers need to maintain the low nonlinearity and
monotonic operation of the D/A while providing enough
speed for maximum converter performance.
Operational Amplifiers
HA5127
HA5137
HA5147
HA5170
TABLE 1. RECOMMENDED TRIM RESISTOR VALUES vs
GRADES FOR VDD = +5V
TRIM RESISTOR
J, A, S
K, B
R1
500Ω
200Ω
R2
150Ω
68Ω
Temperature Coefficients
The gain temperature coefficient of the AD7545 has a maximum value of 5ppm/oC and a typical value of 2ppm/oC. This
corresponds to worst case gain shifts of 2 LSBs and
0.8 LSBs respectively over a 100oC temperature range.
When trim resistors R1 and R2 are used to adjust full scale
range, the temperature coefficient of R1 and R2 should also
be taken into account.
Ultra Low Noise, Precision
Ultra Low Noise, Precision, Wide Band
Ultra Low Noise, Precision, High Slew Rate
Precision, JFET Input
TABLE 2. UNIPOLAR BINARY CODE TABLE FOR CIRCUIT OF
FIGURE 4
BINARY NUMBER IN DAC
REGISTER
Basic Applications
Figures 5 and 6 show simple unipolar and bipolar circuits
using the AD7545. Resistor R1 is used to trim for full scale.
Capacitor C1 provides phase compensation and helps prevent overshoot and ringing when using high speed op amps.
Note that the circuits of Figures 5 and 6 have constant input
impedance at the VREF terminal.
1111
1111
1111
1000
0000
0000
0000
0000
0001
The circuit of Figure 4 can either be used as a fixed reference
D/A converter so that it provides an analog output voltage in
the range 0V to -VIN (note the inversion introduced by the op
amp) or VIN can be an AC signal in which case the circuit
behaves as an attenuator (2-Quadrant Multiplier). VIN can be
any voltage in the range -20V ≤ VIN ≤ +20V (provided the op
amp can handle such voltages) since VREF is permitted to
exceed VDD . Table 2 shows the code relationship for the
circuit of Figure 4.
0000
0000
0000
ANALOG OUTPUT
 4095 
– V IN  ------------- 
 4096 
 2048 
1
– V IN  -------------  = – --- V IN
2
 4096 
 1 
– V IN  ------------- 
 4096 
0V
TABLE 3. 2’S COMPLEMENT CODE TABLE FOR CIRCUIT OF
FIGURE 5
Figure 5 and Table 3 illustrate the recommended circuit and
code relationship for bipolar operation. The D/A function itself
uses offset binary code and inverter U1 on the MSB line converts 2’s complement input code to offset binary code. If appropriate, inversion of the MSB may be done in software using an
exclusive -OR instruction and the inverter omitted. R3, R4 and
R5 must be selected to match within 0.01% and they should be
the same type of resistor (preferably wire-wound or metal foil),
so that their temperature coefficients match. Mismatch of R3
value to R4 causes both offset and full scale error. Mismatch of
R5 to R4 and R3 causes full scale error.
10-14
DATA INPUT
ANALOG OUTPUT
0111
1111
1111
0000
0000
0001
0000
0000
0000
1111
1111
1111
1000
0000
0000
 2047 
+V IN •  ------------- 
 2048 
 1 
+V IN •  ------------- 
 2048 
0V
 1 
– V IN •  ------------- 
 2048 
 2048 
– V IN •  ------------- 
 2048 
AD7545
VDD
VIN
18
20
VDD
RFB
19 VREF
R1*
WR
R2 (NOTE)
C1
33pF
OUT 1
AD7545
1
AGND
2
DGND
17
16
-
VOUT
+
3
ANALOG
COMMON
CS
NOTE: REFER TO TABLE 1
DB11 - DB0
(PINS 4 - 15)
FIGURE 5. UNIPOLAR BINARY OPERATION
VDD
VIN
18
20
VDD
RFB
19 VREF
R1 (NOTE)
WR
DB11
17
16
R2 (NOTE)
R4
20K
C1
33pF
OUT 1
AD7545
R3
10K
1
A1
AGND
2
4
R6
5K
DB10 - DB0
R5
20K
A2
+
3
DGND
CS
11
U1
(SEE TEXT)
ANALOG
COMMON
12
NOTE: FOR VALUES OF R1 AND R2
SEE TABLE 1
DATA INPUT
FIGURE 6. BIPOLAR OPERATION (2’S COMPLEMENT CODE)
10-15
VOUT
AD7545
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
121 mils x 123 mils (3073micrms x 3124micrms)
Type: PSG/Nitride
PSG: 7 ±1.4kÅ
Nitride: 8 ±1.2kÅ
METALLIZATION:
Type: Pure Aluminum
Thickness: 10 ±1kÅ
PROCESS:
CMOS Metal Gate
Metallization Mask Layout
AD7545
PIN 7
DB8
PIN 6
DB9
PIN 4
DB11
(MSB)
PIN 5
DB10
PIN 3
DGND
PIN 2
AGND
PIN 1
OUT1
PIN 8
DB7
PIN 9
DB6
PIN 10
DB5
PIN 11
DB4
PIN 20
RFEEDBACK
PIN 19
VREF
PIN 12
DB3
PIN 13
DB2
PIN 18
VDD
PIN 14
DB1
PIN 15
DB0
(LSB)
PIN 16
CS
PIN 17
WR
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
10-16
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