FAIRCHILD 74ACT399SJ

Revised November 1999
74AC399 • 74ACT399
Quad 2-Port Register
General Description
Features
The AC/ACT399 is the logical equivalent of a quad 2-input
multiplexer feeding into four edge-triggered flip-flops. A
common Select input determines which of the two 4-bit
words is accepted. The selected data enters the flip-flop on
the rising edge of the clock.
■ ICC reduced by 50%
■ Select inputs from two data sources
■ Fully positive edge-triggered operation
■ Outputs source/sink 24 mA
■ AC/ACT399 has TTL-compatible inputs
Ordering Code:
Order Number
Package Number
Package Description
74AC399SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74AC399PC
N16E
74ACT399SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
74ACT399SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT399PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
S
Common Select Input
CP
Clock Pulse Input
I0a–I0d
Data Inputs from Source 0
I1a–I1d
Data Inputs from Source 1
Qa–Qd
Register True Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS009789
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74AC399 • 74ACT399 Quad 2-Port Register
June 1988
74AC399 • 74ACT399
Functional Description
Function Table
The AC/ACT399 is a high-speed quad 2-port register. It
selects four bits of data from either of two sources (Ports)
under control of a common Select input (S). The selected
data is transferred to a 4-bit output register synchronous
with the LOW-to-HIGH transition of the Clock input (CP).
The 4-bit D-type output register is fully edge-triggered. The
Data inputs (I0x, I1x) and Select input (S) must be stable
only a setup time prior to and hold time after the LOW-toHIGH transition of the Clock input for predictable operation.
Inputs
S
Outputs
I0
I1
L
L
X
L
H
X
H
X
L
H
X
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
CP
Q
Q
L
H
H
L
L
H
H
L
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Recommended Operating
Conditions
−0.5V to +7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
−20 mA
VI = VCC + 0.5V
+20 mA
DC Input Voltage (VI)
Supply Voltage (VCC)
−0.5V to VCC + 0.5V
VO = VCC + 0.5V
0V to VCC
0V to VCC
−40°C to +85°C
Operating Temperature (TA)
+20 mA
Minimum Input Edge Rate (∆V/∆t)
−0.5V to VCC + 0.5V
AC Devices
VIN from 30% to 70% of VCC
DC Output Source or
VCC @ 3.3V, 4.5V, 5.5V
±50 mA
Sink Current (IO)
125 mV/ns
Minimum Input Edge Rate (∆V/∆t)
DC VCC or Ground Current
ACT Devices
±50 mA
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
4.5V to 5.5V
Output Voltage (VO)
−20 mA
DC Output Voltage (VO)
2.0V to 6.0V
ACT
Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
AC
VIN from 0.8V to 2.0V
−65°C to +150°C
VCC @ 4.5V, 5.5V
Junction Temperature (TJ)
+140°C
PDIP
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. National does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol
VIH
Parameter
Minimum HIGH Level
Input Voltage
VIL
VOH
VCC
TA = +25°C
(V)
Typ
3.0
1.5
TA = −40°C to +85°C
Guaranteed Limits
2.1
Units
4.5
2.25
3.15
3.15
5.5
2.75
3.85
3.85
Maximum LOW Level
3.0
1.5
0.9
0.9
Input Voltage
4.5
2.25
1.35
1.35
5.5
2.75
1.65
1.65
Minimum HIGH Level
3.0
2.99
2.9
2.9
Output Voltage
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
3.0
2.56
2.46
4.5
3.86
3.76
5.5
4.86
4.76
0.1
0.1
Conditions
VOUT = 0.1V
2.1
V
or VCC −0.1V
VOUT = 0.1V
V
or VCC − 0.1V
V
IOUT = −50 µA
VIN = VIL or VIH
VOL
Maximum LOW Level
Output Voltage
3.0
0.002
IOH= −12 mA
V
IOH= −24 mA
IOH= −24 mA (Note 2)
V
IOUT = 50 µA
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
3.0
0.36
0.44
4.5
0.36
0.44
5.5
0.36
0.44
5.5
±0.1
±1.0
µA
VI = VCC, GND
Current
5.5
±0.5
±5.0
µA
VI = VCC, GND
IOLD
Minimum Dynamic
5.5
75
mA
VOLD = 1.65V Max
IOHD
Output Current (Note 3)
5.5
−75
mA
VOHD = 3.85V Min
ICC
Maximum Quiescent Supply Current
5.5
40.0
µA
VIN = VCC or GND
VIN = VIL or VIH
IIN
Maximum Input Leakage Current
IOZ
Maximum 3-STATE
IOL= 12 mA
V
IOL = 24 mA
IOL = 24 mA (Note 2)
VI (OE) = V IL, VIH
VO = VCC, GND
4.0
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
3
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74AC399 • 74ACT399
Absolute Maximum Ratings(Note 1)
74AC399 • 74ACT399
DC Electrical Characteristics for ACT
Symbol
VIH
VIL
VOH
Parameter
Minimum HIGH Level
TA = 25°C
VCC
(V)
Typ
4.5
1.5
TA = −40°C to +85°C
Guaranteed Limits
2.0
2.0
Input Voltage
5.5
1.5
2.0
2.0
Maximum LOW Level
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
Minimum HIGH Level
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
3.86
3.76
Units
V
V
Conditions
VOUT = 0.1V
or VCC −0.1V
VOUT = 0.1V
or VCC − 0.1V
V
IOUT = −50 µA
V
IOH = −24 mA
VIN = VIL or VIH
4.5
5.5
VOL
IOH = −24 mA (Note 5)
4.85
4.76
Maximum LOW Level
4.5
0.001
0.1
0.1
Output Voltage
5.5
0.001
0.1
0.1
4.5
0.36
0.44
5.5
0.36
0.44
±0.1
±1.0
µA
1.5
mA
VI = VCC −2.1V
V
IOUT = 50 µA
V
IOL = 24 mA
VIN = VIL or VIH
IIN
Maximum Input
Leakage Current
5.5
VI = VCC, GND
ICCT
Maximum ICC/Input
5.5
IOLD
Minimum Dynamic (Note 6)
5.5
75
mA
VOLD = 1.65V Max
IOHD
Output Current
5.5
−75
mA
VOHD = 3.85V Min
ICC
Maximum Quiescent
40.0
µA
Supply Current
0.6
IOL = 24 mA (Note 5)
5.5
4.0
VIN = VCC
or Ground
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
Symbol
Parameter
VCC
TA = +25°C
TA = −40°C tp +85°C
(V)
VCC = +5.0V
VCC = 5.0V
(Note 7)
CL = 50 pF
CL = 50 pF
Min
Typ
fMAX
Input Clock Frequency
3.3
140
160
5.0
170
190
tPLH
Propagation Delay
3.3
4.0
7.5
tPHL
Max
Min
Max
130
MHz
165
10.0
3.5
11.0
CP to Q
5.0
2.0
5.0
8.0
1.5
8.5
Propagation Delay
3.3
3.5
7.0
9.5
3.0
10.5
CP to Q
5.0
2.0
5.0
7.5
1.5
8.0
Note 7: Voltage Range 5.0 is 5.0V ± 0.5V
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4
Units
ns
ns
Symbol
tS
tH
tS
tH
tW
VCC
TA = +25°C
(V)
CL = 50 pF
Parameter
TA = −40°C to +85°C
CL = 50 pF
(Note 8)
Typ
Setup Time, HIGH or LOW
3.3
2.0
4.0
4.0
In to CP
5.0
1.5
3.0
3.0
Hold Time, HIGH or LOW
3.3
0.5
1.0
1.0
In to CP
5.0
0.5
1.0
1.0
Setup Time, HIGH or LOW
3.3
3.5
5.5
5.5
S to CP
5.0
2.0
4.0
4.0
Hold Time, HIGH or LOW
3.3
0.5
1.0
1.0
S to CP
5.0
0.5
1.0
1.0
CP Pulse Width,
3.3
3.0
4.5
4.5
HIGH or LOW
5.0
2.0
3.5
3.5
Units
Guaranteed Minimum
ns
ns
ns
ns
ns
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics for ACT
Symbol
Parameter
fMAX
Input Clock Frequency
tPLH
Propagation Delay
CP to Q
Propagation Delay
tPHL
CP to Q
VCC
TA = +25°C
TA = −40°C to +85°C
(V)
VCC = +5.0V
VCC = 5.0V
(Note 9)
CL = 50 pF
CL = 50pF
Max
Min
Units
Min
Typ
5.0
165
180
Max
5.0
1.5
7.0
8.0
1.5
8.5
ns
5.0
2.0
6.0
9.0
2.0
9.5
ns
160
MHz
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements for ACT
Symbol
Parameter
Setup Time, HIGH or LOW
tS
VCC
TA = +25°C
(V)
CL = 50 pF
TA = −40°C to +85°C
CL = 50 pF
Units
(Note 10)
Typ
Guaranteed Minimum
5.0
0.8
2.5
2.5
ns
5.0
0
1.0
1.0
ns
5.0
0.8
4.0
4.0
ns
5.0
−1.0
0.5
0.5
ns
5.0
1.7
3.5
3.5
ns
In to CP
tH
Hold Time, HIGH or LOW
In to CP
Setup Time, HIGH or LOW
tS
S to CP
tH
Hold Time, HIGH or LOW
S to CP
tW
CP Pulse Width,
HIGH or LOW
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Typ
Units
CIN
Symbol
Input Capacitance
Parameter
4.5
pF
VCC = OPEN
CPD
Power Dissipation Capacitance
30
pF
VCC = 5.0V
5
Conditions
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74AC399 • 74ACT399
AC Operating Requirements for AC
74AC399 • 74ACT399
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Package Number M16A
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6
74AC399 • 74ACT399
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7
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74AC399 • 74ACT399 Quad 2-Port Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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