Cypress CY29972AXIT 3.3 v, 125-mhz multi-output zero delay buffer Datasheet

CY29972
3.3 V, 125-MHz Multi-Output
Zero Delay Buffer
3.3 V, 125-MHz Multi-Output Zero Delay Buffer
Features
Table 1. Frequency Table [1]
■
Output frequency up to 125 MHz
■
12 Clock outputs: frequency configurable
■
350 ps max. output-to-output skew
■
Configurable output disable
■
Two reference clock inputs for dynamic toggling
■
Oscillator or crystal reference input
■
Spread-spectrum-compatible
■
Glitch-free output clocks transitioning
■
3.3 V power supply
■
Pin-compatible with MPC972
■
Industrial temperature range: –40 °C to +85 °C
■
52-pin thin quad flat package (TQFP) package
VC0_SEL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FB_SEL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FB_SEL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FB_SEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FVC0
8x
12x
16x
20x
16x
24x
32x
40x
4x
6x
8x
10x
8x
12x
16x
20x
Block Diagram
XIN
XOUT
VCO_SEL
PLL_EN
REF_SEL
D Q
TCLK0
TCLK1
TCLK_SEL
Phase
Detector
0
1
0
1
VCO
Sync
Frz
QA0
QA1
LPF
QA2
QA3
FB_IN
D Q
Sync
Frz
QB0
QB1
QB2
FB_SEL2
QB3
MR#/OE
Power-On
Reset
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
FB_OUT
D Q
Sync
Frz
SYNC
/4, /6, /8, /12
SELA(0,1)
2
SELB(0,1)
2
SELC(0,1)
2
FB_SEL(0,1)
2
QC1
/4, /6, /8, /10
/2, /4, /6, /8
SCLK
QC2
QC3
/4, /6, /8, /10
/2
0
1
Sync Pulse
Data Generator
Output Disable
Circuitry
SDATA
QC0
12
INV_CLK
Note
1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz.
Cypress Semiconductor Corporation
Document #: 38-07290 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 11, 2011
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CY29972
Contents
Pin Configuration ............................................................. 3
Pin Description ................................................................. 4
Description ........................................................................ 5
Glitch-Free Output Frequency Transitions .................... 5
SYNC Output ..................................................................... 6
Power Management .......................................................... 7
Absolute Maximum Ratings ............................................ 7
DC Parameters .................................................................. 8
AC Parameters .................................................................. 8
Ordering Information ........................................................ 9
Ordering Code Definitions ........................................... 9
Document #: 38-07290 Rev. *E
Package Diagram ............................................................ 10
Acronyms ........................................................................ 11
Document Conventions ................................................. 11
Units of Measure ....................................................... 11
Document History Page ................................................. 12
Sales, Solutions, and Legal Information ...................... 13
Worldwide Sales and Design Support ....................... 13
Products .................................................................... 13
PSoC Solutions ......................................................... 13
Page 2 of 13
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CY29972
Pin Configuration
SELB1
SELB0
SELA1
SELA0
QA3
VDDC
QA2
VSS
QA1
VDDC
QA0
VSS
VCO_SEL
52 51 50 49 48 47 46 45 44 43 42 41 40
VSS
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
XIN
XOUT
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
CY29972
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
QB3
FB_IN
VSS
FB_OUT
VDDC
FB_SEL0
14 15 16 17 18 19 20 21 22 23 24 25 26
FB_SEL1
SYNC
VSS
QC0
VDDC
QC1
SELC0
SELC1
QC2
VDDC
QC3
VSS
INV_CLK
Document #: 38-07290 Rev. *E
Page 3 of 13
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CY29972
Pin Description
Pin [2]
Name
PWR
I/O
Type
11
XIN
–
I
–
Oscillator input. Connect to a crystal.
12
XOUT
–
O
–
Oscillator output. Connect to a crystal.
9
TCLK0
–
I
PU
External reference/test clock input.
External reference/test clock input.
Description
10
TCLK1
–
I
PU
44, 46, 48, 50
QA(3:0)
VDDC
O
–
Clock outputs. See Table 2 on page 5 for frequency selections.
32, 34, 36, 38
QB(3:0)
VDDC
O
–
Clock outputs. See Table 2 on page 5 for frequency selections.
16, 18, 21, 23
QC(3:0)
VDDC
O
–
Clock outputs. See Table 2 on page 5 for frequency selections.
29
FB_OUT
VDDC
O
–
Feedback clock output. Connect to FB_IN for normal operation. The divider
ratio for this output is set by FB_SEL(0:2). See Table 1 on page 1. A bypass
delay capacitor at this output will control Input Reference/ Output Banks phase
relationships.
25
SYNC
VDDC
O
–
Synchronous pulse output. This output is used for system synchronization.
The rising edge of the output pulse is in sync with both the rising edges of
QA(0:3) and QC(0:3) output clocks regardless of the divider ratios selected.
42, 43
SELA(1,0)
–
I
PU
Frequency select inputs. These inputs select the divider ratio at QA(0:3)
outputs. See Table 2 on page 5.
40, 41
SELB(1,0)
–
I
PU
Frequency select inputs. These inputs select the divider ratio at QB(0:3)
outputs. See Table 2 on page 5.
19, 20
SELC(1,0)
–
I
PU
Frequency select inputs. These inputs select the divider ratio at QC(0:3)
outputs. See Table 2 on page 5.
5, 26, 27
FB_SEL(2:0)
–
I
PU
Feedback select inputs. These inputs select the divide ratio at FB_OUT
output. See Table 1 on page 1.
52
VCO_SEL
–
I
PU
VCO divider select input. When set LOW, the VCO output is divided by 2.
When set HIGH, the divider is bypassed. See Table 1 on page 1.
31
FB_IN
–
I
PU
Feedback clock input. Connect to FB_OUT for accessing the PLL.
6
PLL_EN
–
I
PU
PLL enable input. When asserted HIGH, PLL is enabled; when LOW, PLL is
bypassed.
7
REF_SEL
–
I
PU
Reference select input. When HIGH, the crystal oscillator is selected; when
LOW, TCLK (0,1) is the reference clock.
8
TCLK_SEL
–
I
PU
TCLK select input. When LOW, TCLK0 is selected and when HIGH TCLK1
is selected.
2
MR#/OE
–
I
PU
Master reset/output enable input. When asserted LOW, resets all of the
internal flip-flops and also disables all of the outputs. When pulled high,
releases the internal flip-flops from reset and enables all of the outputs.
14
INV_CLK
–
I
PU
Inverted clock input. When set HIGH, QC(2,3) outputs are inverted. When
set LOW, the inverter is bypassed.
3
SCLK
–
I
PU
Serial clock input. Clocks data at SDATA into the internal register.
4
SDATA
–
I
PU
Serial data input. Input data is clocked to the internal register to enable/disable
individual outputs. This provides flexibility in power management.
17, 22, 28,
33,37, 45, 49
VDDC
–
–
–
3.3 V power supply for output clock buffers.
13
VDD
–
–
–
3.3 V power supply for PLL.
1, 15, 24, 30,
35, 39, 47, 51
VSS
–
–
–
Common ground.
Note
2. A bypass capacitor (0.1 mF) should be placed as close as possible to each positive power (< 0.2”). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
Document #: 38-07290 Rev. *E
Page 4 of 13
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CY29972
Description
The CY29972 has an integrated PLL that provides low skew and
low jitter clock outputs for high-performance microprocessors.
Three independent banks of four outputs and an independent
PLL feedback output (FB_OUT) provide exceptional flexibility for
possible output configurations. The PLL is ensured stable
operation given that the VCO is configured to run between
200 MHz and 480 MHz. This allows a wide range of output
frequencies up to 125 MHz.
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input (FB_IN) is connected to the feedback output
(FB_OUT). The internal VCO is running at multiples of the input
reference clock set by FB_SEL(0:2) and VCO_SEL select inputs
(refer to Frequency Table). The VCO frequency is then divided to
provide the required output frequencies. These dividers are set
by SELA(0,1), SELB(0,1), SELC(0,1) select inputs (see the
following Table). For situations were the VCO needs to run at
relatively low frequencies and hence might not be stable, assert
VCO_SEL low to divide the VCO frequency by 2. This maintains
the desired output relationships but provides an enhanced PLL
lock range.
The CY29972 is also capable of providing inverted output clocks.
When INV_CLK is asserted HIGH, QC2 and QC3 output clocks
are inverted. These clocks could be used as feedback outputs to
the CY29972 or a second PLL device to generate early or late
clocks for a specific design. This inversion does not affect the
output to output skew.
Glitch-Free Output Frequency Transitions
Customarily, when output buffers have their internal counters
changed “on the fly,” their output clock periods will:
1. contain short or “runt” clock periods. These are clock cycles
in which the cycle(s) are shorter in period than either the old
or new frequencies to which the cycles are being transitioned.
2. contain stretched clock periods. These are clock cycles in
which the cycle(s) are longer in period than either the old or
new frequencies to which the cycles are being transitioned.
This device specifically includes logic to guarantee that runt and
stretched clock pulses do not occur if the device logic levels of
any or all of the following pins changed “on the fly” while it is
operating: SELA, SELB, SELC, and VCO_SEL.
Table 2. Frequency Selection Table
VCO_SEL
SELA1
SELA0
0
0
0
VCO/8
0
0
VCO/8
0
0
VCO/4
0
0
1
VCO/12
0
1
VCO/12
0
1
VCO/8
0
1
0
VCO/16
1
0
VCO/16
1
0
VCO/12
0
1
1
VCO/24
1
1
VCO/20
1
1
VCO/16
1
0
0
VCO/4
0
0
VCO/4
0
0
VCO/2
1
0
1
VCO/6
0
1
VCO/6
0
1
VCO/4
1
1
0
VCO/8
1
0
VCO/8
1
0
VCO/6
1
1
1
VCO/12
1
1
VCO/10
1
1
VCO/8
Document #: 38-07290 Rev. *E
QA
SELB1
SELB0
QB
SELC1
SELC0
QC
Page 5 of 13
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CY29972
SYNC Output
In situations where output frequency relationships are not integer
multiples of each other, the SYNC output provides a signal for
system synchronization. The CY29972 monitors the relationship
between the QA and QC output clocks. It provides a LOW-going
pulse, one period in duration, one period prior to the coincident
rising edges of the QA and QC outputs. The duration and
placement of the pulse depend on the higher of the QA and QC
output frequencies. The following timing diagram illustrates
various waveforms for the SYNC output. Note that the SYNC
output is defined for all possible combinations of QA and QC
outputs, even though under some relationships the lower
frequency clock could be used as a synchronizing signal.
Figure 1. Timing Diagram
VCO
1:1 Mode
QA
QC
SYNC
2:1 Mode
QA
QC
SYNC
3:1 Mode
QC
QA
SYNC
3:2 Mode
QA
QC
SYNC
4:1 Mode
QC
QA
SYNC
4:3 Mode
QA
QC
SYNC
6:1 Mode
QA
QC
SYNC
Document #: 38-07290 Rev. *E
Page 6 of 13
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CY29972
Power Management
The individual output enable/freeze control of the CY29972
allows the user to implement unique power management
schemes into the design. The outputs are stopped in the logic ‘0’
state when the freeze control bits are activated. The serial input
register contains one programmable freeze enable bit for 12 of
the 14 output clocks. The QC0 and FB_OUT outputs can not be
frozen with the serial port, this avoids any potential lock up
situation should an error occur in the loading of the serial data.
Start
Bit
An output is frozen when a logic ‘0’ is programmed and enabled
when a logic ‘1’ is written. The enabling and freezing of individual
outputs is done in such a manner as to eliminate the possibility
of partial “runt” clocks.
The serial input register is programmed through the SDATA input
by writing a logic ‘0’ start bit followed by 12 NRZ freeze enable
bits. The period of each SDATA bit equals the period of the free
running SCLK signal. The SDATA is sampled on the rising edge
of SCLK.
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
Table 3. Suggested Oscillator Crystal Parameters
Min
Typ
Max
Unit
TC
Parameter
Frequency tolerance
Characteristic
–
–
±100
ppm Note 3
TS
Frequency temperature stability
–
–
±100
ppm (TA –10 to +60 °C) [3]
TA
Aging
–
–
5
CL
Load capacitance
–
20
–
RESR
Effective series resistance (ESR)
–
40
80
Absolute Maximum Ratings
Exceeding maximum ratings [5] may shorten the useful life of the
device. User guidelines are not tested.
Maximum input voltage relative to VSS .............. VSS – 0.3 V
Maximum input voltage relative to VDD .............. VDD + 0.3 V
Storage temperature ................................ –65 °C to +150 °C
Operating temperature .............................. –40 °C to +85 °C
Maximum ESD protection .............................................. 2 kV
Conditions
ppm/ (first 3 years at 25 °C) [3]
Yr
pF
The crystal’s rated load [3]
ohms Note 4
Maximum power supply ................................................ 5.5 V
Maximum input current ............................................. ±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, VIN and VOUT should be constrained to the range:
VSS < (VIN or VOUT) < VDD .Unused inputs must always be tied
to an appropriate logic voltage level (either VSS or VDD).
Notes
3. For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meet or exceed these specifications.
4. Larger values may cause this device to exhibit oscillator start-up problems.
5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.
Document #: 38-07290 Rev. *E
Page 7 of 13
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CY29972
DC Parameters
VDD = 2.9 V to 3.6 V, VDDC = 3.3 V ± 10%, TA = –40 °C to +85 °C
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VIL
Input Low voltage
VSS
–
0.8
V
VIH
Input High voltage
2.0
–
VDD
V
[6]
IIL
Input Low current
IIH
Input High current
VOL
Output Low voltage [7]
IOL = 20 mA
VOH
Output High voltage [7]
IOH = –20 mA
–
–
–120
µA
–
–
10
µA
–
–
0.5
V
2.4
–
–
V
IDDQ
Quiescent supply current
IDDA
PLL supply current
VDD only
IDD
Dynamic supply current
QA and QB at 60 MHz, QC at 120 MHz, CL = 30 pF
–
QA and QB at 25 MHz, QC at 50 MHz, CL = 30 pF
–
–
4
–
CIN
Input pin capacitance
–
10
15
mA
–
15
20
mA
225
–
mA
125
–
pF
AC Parameters
VDD = 2.9 V to 3.6 V, VDDC = 3.3 V ±10%, TA = –40 °C to +85 °C
Parameter [8]
Description
Conditions
Min
Typ
Max
Unit
TR / TF
TCLK input rise/fall
FREF
Reference input frequency
FXTAL
Crystal Oscillator Frequency
10
FREFDC
Reference input duty cycle
25
FVCO
PLL VCO lock range
200
tLOCK
Maximum PLL lock time
–
0.8 V to 2.0 V
0.15
–
1.2
ns
Q (³2)
–
–
125
MHz
see Table 3 on page 7
[10]
tR / tF
Output clocks rise / fall time
FOUT
Maximum Output Frequency
3.0
ns
Note 9
MHz
–
25
MHz
–
75
%
–
480
MHz
–
10
ms
–
–
120
Q (³6)
–
–
80
Output duty cycle [10]
[10]
–
–
Q (³4)
Q (³8)
FOUTDC
–
Note 9
–
–
60
TCYCLE/2 – 750
–
TCYCLE/2 + 750
ps
tPZL, tPZH
Output enable time
(all outputs)
2
–
10
ns
tPLZ, tPHZ
Output disable time [10] (all outputs)
2
–
8
ns
–
±
100
–
[10]
TCCJ
Cycle to cycle jitter
TSKEW
Any output to any output skew [10, 11]
TPD
Propagation delay [11, 12]
(peak to peak)
TCLK0
QFB = (³8)
TCLK1
ps
–
250
350
ps
–270
130
530
ps
–330
70
470
Notes
6. Inputs have pull-up/pull-down resistors that effect input current.
7. Driving series or parallel terminated 50  (or 50  to VDD/2) transmission lines.
8. Parameters are guaranteed by design and characterization. Not 100% tested in production.
9. Maximum and minimum input reference is limited by VC0 lock range.
10. Outputs loaded with 30 pF each.
11. 50 transmission line terminated into VDD/2.
12. Tpd is specified for a 50-MHz input reference. Tpd does not include jitter.
Document #: 38-07290 Rev. *E
Page 8 of 13
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CY29972
Ordering Information
Part Number
Package Type
Production Flow
Pb-free
CY29972AXI
52-pin TQFP
Industrial, –40 °C to +85 °C
CY29972AXIT
52-pin TQFP - Tape and Reel
Industrial, –40 °C to +85 °C
Ordering Code Definitions
CY 29972 A
X
X
X
X = T or blank
T = Tape and Reel; blank = Tube
Temperature Range: X = C or I
C = Commercial = 0 °C to +70 °C; I = Industrial = –40 °C to +85 °C
X = Pb-free, blank = leaded
Package Type:
A = 52-pin TQFP
Base Device Part Number
Company ID: CY = Cypress
Document #: 38-07290 Rev. *E
Page 9 of 13
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CY29972
Package Diagram
Figure 2. 52-pin TQFP (10 × 10 × 1.4 mm) A52SA Package Outline, 51-85131
51-85131 *B
Document #: 38-07290 Rev. *E
Page 10 of 13
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CY29972
Acronyms
Acronym
Document Conventions
Description
I/O
input/output
PLL
phase locked loop
TQFP
thin quad flat pack
Document #: 38-07290 Rev. *E
Units of Measure
Symbol
Units of Measure
°C
degree Celsius
MHz
megahertz
µA
microampere
mA
milliampere
ms
millisecond
ns
nanosecond
pF
picofarad
ps
picosecond
V
volt
Page 11 of 13
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CY29972
Document History Page
Document Title: CY29972, 3.3 V, 125-MHz Multi-Output Zero Delay Buffer
Document Number: 38-07290
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
111101
02/07/02
BRK
New data sheet
*A
122882
12/22/02
RBI
Added power up requirements to Maximum Ratings
*B
387764
See ECN
RGL
Changed the package drawing and dimension to Cypress Standard
Added Pb-free devices
*C
404340
See ECN
RGL
Minor Change: corrected the package diagram
*D
3270575
06/03/2011
BASH
Updated as per template
Updated package diagram 51-85131.
Added Acronyms and Units of Measure Table
*E
3402187
10/11/2011
BASH
Updated Ordering Information (Removed prune part numbers CY29972AI
and CY29972AIT).
Updated Package Diagram.
Document #: 38-07290 Rev. *E
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CY29972
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2005-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07290 Rev. *E
Revised October 11, 2011
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