Cypress CY8C20566A-24PVXI 1.8 v capsenseâ® controller with smartsenseâ ¢ auto-tuning Datasheet

CY8C20X36A/46A/66A/96A/46AS/66AS
®
1.8 V CapSense Controller with
SmartSense™ Auto-tuning
1.8 V CapSense® Controller with SmartSense™ Auto-tuning
Dual mode GPIO: All GPIOs support digital I/O and analog
inputs
❐ 25-mA sink current on each GPIO
• 120 mA total sink current on all GPIOs
❐ Pull-up, high Z, open-drain modes on all GPIOs
❐ CMOS drive mode –5 mA source current on ports 0 and 1
and 1 mA on ports 2, 3, and 4
• 20 mA total source current on all GPIOs
Features
❐
■
Wide operating range: 1.71 V to 5.5 V
■
Ultra low deep sleep current: 100 nA
❐ Configurable capacitive sensing elements
❐ 7 μA per sensor at 500 ms scan rate
❐ Supports SmartSense Auto-tuning
❐ Supports a combination of CapSense buttons, sliders,
touchpads, touchscreens, and proximity sensors
❐ SmartSense_EMC offers superior noise immunity for
applications with challenging conducted and radiated noise
conditions
■
Powerful Harvard-architecture processor
❐ M8C CPU – Up to 4 MIPS with 24 MHz Internal clock, external
crystal resonator or clock signal
❐ Low power at high speed
■
Temperature range: –40 °C to +85 °C
■
Flexible on-chip memory
❐ Three program/data storage size options:
• 8 KB flash/1 KB SRAM
• 16 KB flash/2 KB SRAM
• 32 KB flash/2 KB SRAM
❐ 50,000 flash erase/write cycles
❐ Partial flash updates
❐ Flexible protection modes
❐ In-system serial programming (ISSP)
■
Full-speed USB
❐ 12 Mbps USB 2.0 compliant
■
Precision, programmable clocking
❐ Internal main oscillator (IMO): 6/12/24 MHz ± 5%
❐ Internal low speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
❐ Precision 32 kHz oscillator for optional external crystal
■
Programmable pin configurations
❐ Up to 36 general-purpose I/Os (GPIOs) (depending on
package)
■
Versatile analog system
❐ Low-dropout voltage regulator for all analog resources
❐ Common internal analog bus enabling capacitive sensing on
all pins
❐ High power supply rejection ratio (PSRR) comparator
❐ 8 to 10-bit incremental analog-to-digital converter (ADC)
■
Additional system resources
2
❐ I C slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
❐ SPI master and slave: Configurable 46.9 kHz to 12 MHz
❐ Three 16-bit timers
❐ Watchdog and sleep timers
❐ Integrated supervisory circuit
❐ Emulated E2PROM using flash memory
■
Complete development tools
❐ Free development tool (PSoC Designer™)
❐ Full-featured, in-circuit emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
■
Versatile package options
❐ 16-pin 3 × 3 × 0.6 mm QFN
❐ 24-pin 4 × 4 × 0.6 mm QFN
❐ 32-pin 5 × 5 × 0.6 mm QFN
❐ 48-pin SSOP
❐ 48-pin 7 × 7 × 1.0 mm QFN
[1]
❐ 30-ball WLCSP
Note
1. Contact your local sales office for details.
Cypress Semiconductor Corporation
Document Number: 001-54459 Rev. *O
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 15, 2012
CY8C20X36A/46A/66A/96A/46AS/66AS
Logic Block Diagram
Port 4
Port 3
Port 2
Port 1
Port 0
1.8/2.5/3V
LDO
[2]
PWRSYS
(Regulator)
PSoC CORE
SYSTEM BUS
Global Analog Interconnect
1K/2K
SRAM
Supervisory ROM (SROM)
Interrupt
Controller
8K/16K/32K Flash
Nonvolatile Memory
Sleep and
Watchdog
CPU Core (M8C)
6/12/24 MHz Internal Main Oscillator
(IMO)
Internal Low Speed Oscillator (ILO)
Multiple Clock Sources
CAPSENSE
SYSTEM
Two
Comparators
Analog
Reference
CapSense
Module
Analog
Mux
SYSTEM BUS
USB
I2C
Slave
Internal
Voltage
References
System
Resets
POR
and
LVD
SPI
Master/
Slave
Three 16-Bit
Programmable
Timers
Digital
Clocks
SYSTEM RESOURCES
Note
2. Internal voltage regulator for internal circuitry
Document Number: 001-54459 Rev. *O
Page 2 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Contents
PSoC® Functional Overview............................................ 4
PSoC Core .................................................................. 4
CapSense System....................................................... 4
Additional System Resources ..................................... 5
Getting Started.................................................................. 6
CapSense Design Guides ........................................... 6
Silicon Errata ............................................................... 6
Development Kits ........................................................ 6
Training ....................................................................... 6
CYPros Consultants .................................................... 6
Solutions Library.......................................................... 6
Technical Support ....................................................... 6
Development Tools .......................................................... 7
PSoC Designer Software Subsystems........................ 7
Designing with PSoC Designer ....................................... 8
Select User Modules ................................................... 8
Configure User Modules.............................................. 8
Organize and Connect ................................................ 8
Generate, Verify, and Debug....................................... 8
Pinouts .............................................................................. 9
16-pin QFN (12 Sensing Inputs)[4] ............................. 9
24-pin QFN (12 Sensing Inputs)................................ 10
24-pin QFN - 18 Sensing Inputs (With USB)............. 11
30-ball WLCSP (26 Sensing Inputs).......................... 12
32-pin QFN (27 Sensing Inputs)................................ 13
32-pin QFN - 24 Sensing Inputs (With USB)............. 14
48-pin SSOP (33 Sensing Inputs) ............................. 15
48-pin QFN (35 Sensing Inputs)................................ 16
48-pin QFN - 35 Sensing Inputs (With USB)............. 17
48-pin QFN (OCD) .................................................... 18
Electrical Specifications ................................................ 19
Absolute Maximum Ratings....................................... 19
Operating Temperature ............................................. 19
DC Chip-Level Specifications.................................... 20
DC GPIO Specifications ............................................ 21
DC Analog Mux Bus Specifications........................... 23
DC Low Power Comparator Specifications ............... 23
Comparator User Module Electrical Specifications ... 24
Document Number: 001-54459 Rev. *O
ADC Electrical Specifications ....................................
DC POR and LVD Specifications ..............................
DC Programming Specifications ...............................
DC I2C Specifications ...............................................
DC Reference Buffer Specifications..........................
DC IDAC Specifications ............................................
AC Chip-Level Specifications ....................................
AC GPIO Specifications ............................................
AC Comparator Specifications ..................................
AC External Clock Specifications ..............................
AC Programming Specifications................................
AC I2C Specifications................................................
Packaging Information...................................................
Thermal Impedances.................................................
Capacitance on Crystal Pins .....................................
Solder Reflow Specifications.....................................
Development Tool Selection .........................................
Software ....................................................................
Development Kits ......................................................
Evaluation Tools........................................................
Device Programmers.................................................
Accessories (Emulation and Programming) ..............
Third Party Tools .......................................................
Build a PSoC Emulator into Your Board....................
Ordering Information......................................................
Ordering Code Definitions .........................................
Acronyms ........................................................................
Reference Documents....................................................
Document Conventions .................................................
Units of Measure .......................................................
Numeric Naming........................................................
Glossary ..........................................................................
Document History Page .................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC Solutions .........................................................
24
25
25
26
26
26
27
28
29
29
30
31
34
37
37
37
38
38
38
38
38
39
39
39
40
42
43
43
43
43
44
44
45
47
47
47
47
Page 3 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
PSoC® Functional Overview
The PSoC family consists of on-chip controller devices, which
are designed to replace multiple traditional microcontroller unit
(MCU)-based components with one, low cost single-chip
programmable component. A PSoC device includes
configurable analog and digital blocks, and programmable
interconnect. This architecture allows the user to create
customized peripheral configurations, to match the requirements
of each individual application. Additionally, a fast CPU, Flash
program memory, SRAM data memory, and configurable I/O are
included in a range of convenient pinouts.
The architecture for this device family, as shown in the Logic
Block Diagram on page 2, consists of three main areas:
■
The Core
■
CapSense Analog System
■
System Resources (including a full-speed USB port).
A common, versatile bus allows connection between I/O and the
analog system.
required tuning parameters. SmartSense allows engineers to go
from prototyping to mass production without re-tuning for
manufacturing variations in PCB and/or overlay material
properties.
SmartSense_EMC
In addition to the SmartSense auto tuning algorithm to remove
manual tuning of CapSense applications, SmartSense_EMC
user module incorporates a unique algorithm to improve
robustness of capacitive sensing algorithm/circuit against high
frequency conducted and radiated noise. Every electronic device
must comply with specific limits for radiated and conducted
external noise and these limits are specified by regulatory bodies
(for example, FCC, CE, U/L and so on). A very good PCB layout
design, power supply design and system design is a mandatory
for a product to pass the conducted and radiated noise tests. An
ideal PCB layout, power supply design or system design is not
often possible because of cost and form factor limitations of the
product. SmartSense_EMC with superior noise immunity is well
suited and handy for such applications to pass radiated and
conducted noise test.
Figure 1. CapSense System Block Diagram
Each CY8C20X36A/46A/66A/96A/46AS/66AS PSoC device
includes a dedicated CapSense block that provides sensing and
scanning control circuitry for capacitive sensing applications.
Depending on the PSoC package, up to 36 GPIO are also
included. The GPIO provides access to the MCU and analog
mux.
CS1
IDAC
Analog Global Bus
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO and
ILO. The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit
Harvard-architecture microprocessor.
CS2
CSN
Vr
Reference
Buffer
Cinternal
CapSense System
Comparator
The analog system contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. The analog system is composed of the
CapSense PSoC block and an internal 1 V or 1.2 V analog
reference, which together support capacitive sensing of up to
33 inputs [3]. Capacitive sensing is configurable on each GPIO
pin. Scanning of enabled CapSense pins are completed quickly
and easily across multiple ports.
SmartSense
SmartSense is an innovative solution from Cypress that removes
manual tuning of CapSense applications. This solution is easy to
use and provides a robust noise immunity. It is the only
auto-tuning solution that establishes, monitors, and maintains all
Cexternal (P0[1]
or P0[3])
Mux
Mux
Refs
Cap Sense Counters
CSCLK
IMO
CapSense
Clock Select
Oscillator
Note
3. 36 GPIOs = 33 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulator capacitor.
Document Number: 001-54459 Rev. *O
Page 4 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
Complex capacitive sensing interfaces, such as sliders and
touchpads.
communication interface, three 16-bit programmable timers, and
various system resets supported by the M8C.
These system resources provide additional capability useful to
complete systems. Additional resources include low voltage
detection and power on reset. The merits of each system
resource are listed here:
■
The I2C slave/SPI master-slave module provides
50/100/400 kHz communication over two wires. SPI
communication over three or four wires runs at speeds of
46.9 kHz to 3 MHz (lower for a slower system clock).
■
Low-voltage detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced
power-on-reset (POR) circuit eliminates the need for a system
supervisor.
Additional System Resources
■
System resources provide additional capability, such as
configurable USB and I2C slave, SPI master/slave
An internal reference provides an absolute reference for
capacitive sensing.
■
A register-controlled bypass mode allows the user to disable
the LDO regulator.
■
Chip-wide mux that allows analog input from any I/O pin.
■
Crosspoint connection between any I/O pin combinations.
Document Number: 001-54459 Rev. *O
Page 5 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Getting Started
The quickest way to understand PSoC silicon is to read this
datasheet and then use the PSoC Designer Integrated
Development Environment (IDE). This datasheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications.
For in depth information, along with detailed programming
details, see the Technical Reference Manual for the
CY8C20X36A/46A/66A/96A/46AS/66AS PSoC devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web
at www.cypress.com/psoc.
CapSense Design Guides
Design Guides are an excellent introduction to the wide variety
of possible CapSense designs. They are located at
www.cypress.com/go/CapSenseDesignGuides.
Refer Getting Started with CapSense design guide for
information on CapSense design and CY8C20XX6A/H/AS
CapSense® Design Guide for specific information on
CY8C20XX6A/AS CapSense controllers.
Silicon Errata
Errata documents known issues with silicon including errata
trigger conditions, scope of impact, available workarounds and
silicon revision applicability. Refer to Silicon Errata for the PSoC®
CY8C20x36A/46A/66A/96A/46AS/66AS/36H/46H
families
available at http://www.cypress.com/?rID=56239 for errata
information on CY8C20xx6A/AS/H family of device. Compare
Document Number: 001-54459 Rev. *O
errata document with datasheet for a complete functional
description of device.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
CYPros Consultants
Certified PSoC consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC consultant go to the CYPros Consultants web site.
Solutions Library
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Technical Support
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Page 6 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
■
Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■
Extensive user module catalog
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
■
Integrated source-code editor (C and assembly)
Debugger
■
Free C compiler with no size restrictions or time limits
■
Built-in debugger
■
In-circuit emulation
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also lets you to create a trace buffer of registers and memory
locations of interest.
Built-in support for communication interfaces:
2
❐ Hardware and software I C slaves and masters
❐ Full-speed USB 2.0
❐ Up
to
four
full-duplex
universal
asynchronous
receiver/transmitters (UARTs), SPI master and slave, and
wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
■
PSoC Designer Software Subsystems
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an Online Support
Forum to aid the designer.
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), amplifiers, and filters.
Configure the user modules for your chosen application and
connect them to each other and to the proper pins. Then
generate your project. This prepopulates your project with APIs
and libraries that you can use to program your application.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration makes it possible to change configurations at run
time. In essence, this lets you to use more than 100 percent of
PSoC’s resources for an application.
Document Number: 001-54459 Rev. *O
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
Page 7 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed-function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and lowering inventory costs. These
configurable resources, called PSoC blocks, have the ability to
implement a wide variety of user-selectable functions. The PSoC
development process is:
1. Select user modules.
2. Configure user modules.
3. Organize and connect.
4. Generate, verify, and debug.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules”. User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a PWM
User Module configures one or more digital PSoC blocks, one
for each eight bits of resolution. Using these parameters, you can
establish the pulse width and duty cycle. Configure the
parameters and properties to correspond to your chosen
application. Enter values directly or by selecting values from
drop-down menus. All of the user modules are documented in
datasheets that may be viewed directly in PSoC Designer or on
the Cypress website. These user module datasheets explain the
Document Number: 001-54459 Rev. *O
internal operation of the user module and provide performance
specifications. Each datasheet describes the use of each user
module parameter, and other information that you may need to
successfully implement your design.
Organize and Connect
Build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. Perform the selection,
configuration, and routing so that you have complete control over
all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides APIs with high-level functions to control
and respond to hardware events at run time, and interrupt
service routines that you can adapt as needed.
A complete code development environment lets you to develop
and customize your applications in C, assembly language, or
both.
The last step in the development process takes place inside
PSoC Designer’s Debugger (accessed by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full-speed. PSoC Designer debugging
capabilities rival those of systems costing many times more. In
addition to traditional single-step, run-to-breakpoint, and
watch-variable features, the debug interface provides a large
trace buffer. It lets you to define complex breakpoint events that
include monitoring address and data bus values, memory
locations, and external signals.
Page 8 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Pinouts
The CY8C20X36A/46A/66A/96A/46AS/66AS PSoC device is available in a variety of packages, which are listed and illustrated in the
following tables. Every port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, VSS,
VDD, and XRES are not capable of Digital I/O.
16-pin QFN (12 Sensing Inputs)[4]
Table 1. Pin Definitions – CY8C20236A, CY8C20246A, CY8C20246AS PSoC Device
I/O
I
P2[3]
Crystal input (XIn)
IOHR
I
P1[7]
I2C SCL, SPI SS
2
4
IOHR
I
P1[5]
I C SDA, SPI MISO
5
IOHR
I
P1[3]
SPI CLK
6
IOHR
I
P1[1]
ISSP CLK[5], I2C SCL, SPI
MOSI
7
Power
VSS
8
IOHR
I
P1[0]
9
IOHR
I
P1[2]
10
IOHR
I
P1[4]
11
12
13
Input
IOH
AI, XOut, P2[5]
AI , XIn, P2[3]
AI , I2 C SCL, SPI SS, P1[7]
AI , I2 C SDA, SPI MISO, P1[5]
Ground connection
ISSP DATA[5], I2C SDA, SPI
CLK[6]
Optional external clock
(EXTCLK)
XRES Active high external reset with
internal pull-down
I
Power
P0[4]
VDD
Supply voltage
14
IOH
I
P0[7]
15
IOH
I
P0[3]
Integrating input
16
IOH
I
P0[1]
Integrating input
1
2
14
13
Crystal output (XOut)
P0[1], AI
P0[3], AI
P0[7], AI
Vdd
3
P2[5]
16
15
2
I
Figure 2. CY8C20236A, CY8C20246A, CY8C20246AS
12
3
4
QFN
( Top View) 11
10
9
5
6
7
8
Analog
I/O
Description
P0[4] , AI
XRES
P1[4] , EXTCLK, AI
P1[2] , AI
AI, SPI CLK , P1[3]
AI, ISSP CLK, SPI MOSI, P1[1]
Vss
[5,6]
AI, ISSP DATA , I2C SDA, SPI CLK , P1[0]
Digital
1
Name
[5]
Type
Pin
No.
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
4. No Center Pad.
5. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
6. Alternate SPI clock.
Document Number: 001-54459 Rev. *O
Page 9 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
24-pin QFN (12 Sensing Inputs)
Table 2. Pin Definitions – CY8C20336A, CY8C20346A, CY8C20346AS [7]
I C SDA, SPI MISO
P1[3]
SPI CLK
7
IOHR
I
P1[1]
ISSP CLK[8], I2C SCL, SPI
MOSI
8
9
Power
NC
No connection
VSS
Ground connection
10
IOHR
I
P1[0]
11
IOHR
I
P1[2]
12
IOHR
I
P1[4]
13
IOHR
I
P1[6]
14
Input
Optional external clock input
(EXTCLK)
I/O
I
P2[0]
16
IOH
I
P0[0]
17
IOH
I
P0[2]
18
IOH
I
P0[4]
19
IOH
I
P0[6]
Power
VDD
IOH
I
P0[7]
22
IOH
I
P0[5]
23
IOH
I
P0[3]
Integrating input
24
IOH
I
P0[1]
Integrating input
Power
P0[5], AI
P0[7], AI
Vdd
P0[6], AI
22
21
20
19
3
QFN
4
(T o p V ie w )
16
15
5
14
6
13
Supply voltage
21
CP
P 2 [1 ]
P 1 [7 ]
P 1 [5 ]
P 1 [3 ]
P 0 [4 ], A I
P 0 [2 ], A I
P 0 [0 ], A I
P 2 [0 ], A I
XRES
P 1 [6 ], A I
XRES Active high external reset with
internal pull-down
15
20
ISSP DATA[8], I2C SDA, SPI
CLK[9]
A I,
A I, I2 C S C L , S P I S S ,
A I, I2 C S D A , S P I M IS O ,
A I, S P I C L K ,
12
P1[5]
I
AI, EXTCLK, P1[4]
I
IOHR
18
17
2
11
IOHR
6
1
AI, P1[2]
5
A I, X O u t, P 2 [5]
A I, X In , P 2 [3 ]
9
2
10
I2C SCL, SPI SS
Vss
P1[7]
2
P2[1]
I
AI, ISSP DATA , I2C SDA, SPI CLK, P1[0]
I
IOHR
[8, 9]
I/O
4
P0[1], AI
3
P0[3], AI
Crystal input (XIn)
24
Crystal output (XOut)
P2[3]
23
P2[5]
I
8
I
I/O
Figure 3. CY8C20336A, CY8C20346A, CY8C20346AS
7
I/O
2
Description
NC
1
Name
2
Analog
SPI MOSI, P1[1]
Digital
AI, ISSP CLK , I2C SCL
Type
Pin
No.
VSS
Center pad must be
connected to ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
7. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
8. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
9. Alternate SPI clock.
Document Number: 001-54459 Rev. *O
Page 10 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
24-pin QFN - 18 Sensing Inputs (With USB)
Table 3. Pin Definitions – CY8C20396A [10]
2
5
IOHR
I
P1[5]
I C SDA, SPI MISO
6
IOHR
I
P1[3]
SPI CLK
7
IOHR
I
P1[1]
ISSP CLK[11], I2C SCL, SPI
MOSI
8
Power
9
I/O
10
I/O
11
I
I
Power
VSS
Ground
D+
USB D+
D-
USB D-
VDD
Supply
ISSP DATA[11], I2C SDA, SPI
CLK[12]
12
IOHR
I
P1[0]
13
IOHR
I
P1[2]
14
IOHR
I
P1[4]
15
IOHR
I
P1[6]
16
RESET INPUT
XRES Active high external reset with
internal pull-down
17
IOH
I
P0[0]
18
IOH
I
P0[2]
19
IOH
I
P0[4]
20
IOH
I
P0[6]
21
IOH
I
P0[7]
22
IOH
I
P0[5]
23
IOH
I
P0[3]
Integrating input
24
IOH
I
P0[1]
Integrating input
CP
Power
VSS
Optional external clock input
(EXTCLK)
P2[5], AI
P2[3], AI
P2[1], AI
AI, I 2 C SCL, SPI SS,P1[7]
AI, I2C SDA , SPI MISO,P1[5]
AI, SPI CLK ,P1[3]
1
19
P0[1], AI
P0[3], AI
P0[5], AI
P0[7], AI
P0[6], AI
P0[4], AI
I2C SCL, SPI SS
18
17
2
QFN
3
16
4
(Top View) 15
5
14
6
13
P0[2], AI
P0[0], AI
XRES
P1[6], AI
P1[4] , AI, EXTCLK
P1[2 ], AI
AI, ISSP DATA, I2C SDA, SPI CLK, P1[0]
P1[7]
21
P2[1]
I
20
I
IOHR
11
12
I/O
4
[11,
3
22
P2[3]
9
10
P2[5]
I
24
I
I/O
Figure 4. CY8C20396A
23
I/O
2
Description
8
1
Name
7
Analog
AI, ISSP CLK, I2C SCL, SPI MOSI, P1[1]
Vss
D+
DVDD
Digital
[11
Type
Pin
No.
Center pad must be connected
to Ground
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
Notes
10. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
11. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
12. Alternate SPI clock.
Document Number: 001-54459 Rev. *O
Page 11 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
30-ball WLCSP (26 Sensing Inputs)
Table 4. Pin Definitions – CY8C20766A, CY8C20746A 30-ball WLCSP
Type
Pin
No.
Digital
Analog
A1
IOH
I
P0[2]
A2
IOH
I
P0[6]
A3
Power
Name
Description
Figure 5. CY8C20766A 30-ball WLCSP
Bottom View
VDD
Supply voltage
Integrating Input
A4
IOH
I
P0[1]
A5
I/O
I
P2[7]
B1
I/O
I
P2[6]
B2
IOH
I
P0[0]
B3
IOH
I
P0[4]
B4
IOH
I
P0[3]
Integrating Input
B5
I/O
I
P2[5]
Crystal Output (Xout)
C1
I/O
I
P2[2]
C2
I/O
I
P2[4]
C3
IOH
I
P0[7]
C4
IOH
I
P0[5]
C5
I/O
I
P2[3]
D1
I/O
I
P2[0]
D2
I/O
I
P3[0]
D3
I/O
I
P3[1]
D4
I/O
I
P3[3]
D5
I/O
E1
I
Input
2
1
A
D
E
F
Top View
Crystal Input (Xin)
1
2
3
4
5
A
B
P2[1]
C
D
IOHR
I
P1[6]
E3
IOHR
I
P1[4]
Optional external clock input
(EXT CLK)
E4
IOHR
I
P1[7]
I2
E5
IOHR
I
P1[5]
I2C SDA, SPI MISO
F1
IOHR
I
P1[2]
F2
IOHR
I
P1[0]
VSS
3
C
XRES Active high external reset with
internal pull-down
Power
4
B
E2
F3
5
C SCL, SPI SS
E
F
ISSP DATA[13], I2C SDA, SPI
CLK[14]
Supply ground
F4
IOHR
I
P1[1]
ISSP CLK[13], I2C SCL, SPI
MOSI
F5
IOHR
I
P1[3]
SPI CLK
Notes
13. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
14. Alternate SPI clock.
Document Number: 001-54459 Rev. *O
Page 12 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
32-pin QFN (27 Sensing Inputs)
Table 5. Pin Definitions – CY8C20436A, CY8C20446A, CY8C20446AS, CY8C20466A, CY8C20466AS[15]
P2[5]
Crystal output (XOut)
4
I/O
I
P2[3]
Crystal input (XIn)
5
I/O
I
P2[1]
6
I/O
I
P3[3]
7
I/O
I
P3[1]
8
IOHR
I
P1[7]
I C SCL, SPI SS
9
IOHR
I
P1[5]
I2C SDA, SPI MISO
10
IOHR
I
P1[3]
SPI CLK.
11
IOHR
I
P1[1]
ISSP CLK[16], I2C SCL, SPI MOSI.
12
Power
VSS
13
IOHR
I
P1[0]
14
IOHR
I
P1[2]
15
IOHR
I
P1[4]
16
IOHR
17
I
Input
ISSP DATA[16], I2C SDA,
SPI CLK[17]
Optional external clock input
(EXTCLK)
P1[6]
XRES
I/O
I
P3[0]
19
I/O
I
P3[2]
20
I/O
I
P2[0]
21
I/O
I
P2[2]
22
I/O
I
P2[4]
23
I/O
I
P2[6]
24
IOH
I
P0[0]
25
IOH
I
P0[2]
26
IOH
I
P0[4]
27
IOH
I
P0[6]
QFN
(Top View)
24
23
22
21
20
19
18
17
P0[0] , AI
P2[6] , AI
P2[4] , AI
P2[2] , AI
P2[0] , AI
P3[2] , AI
P3[0] , AI
XRES
[16]
18
Active high external reset with
internal pull-down
32
31
Vss
P0 [3], AI
P0 [5], AI
Ground connection.
1
2
3
4
5
6
7
8
9
2
AI , P0[1]
AI , P2[7]
AI, XOut, P2[5]
AI , XIn, P2[3]
AI , P2[1]
AI , P3[3]
AI , P3[1]
AI , I2 C SCL, SPI SS, P1[7]
P0 [4], AI
P0 [2], AI
I
26
25
I/O
15
16
3
Integrating input
AI, E XTCLK, P 1[4]
AI, P 1[6]
P2[7]
P0 [7], AI
Vd d
P0 [6], AI
P0[1]
I
CY8C20466A, CY8C20466AS
28
27
I
I/O
Figure 6. CY8C20436A, CY8C20446A, CY8C20446AS,
13
14
IOH
2
Description
30
29
1
Name
A I,ISSP CLK , I2C SCL, SPI MOSI, P1[1]
Vss
[16]
AI , ISSP DATA , I2C SDA, SPI CLK, P1[0]
AI, P 1[2]
Analog
10
11
12
Digital
AI, I2C SDA, SPI MISO, P 1[5]
AI, SPI CLK, P 1[3]
Type
Pin
No.
28
Power
VDD
29
IOH
I
P0[7]
30
IOH
I
P0[5]
31
IOH
I
P0[3]
Supply voltage
Integrating input
32
Power
VSS
Ground connection
CP
Power
VSS
Center pad must be connected to
ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
15. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
16. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
17. Alternate SPI clock.
Document Number: 001-54459 Rev. *O
Page 13 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
32-pin QFN - 24 Sensing Inputs (With USB)
Table 6. Pin Definitions – CY8C20496A[18]
4
I/O
I
P2[1]
5
IOHR
I
P1[7]
I2C SCL, SPI SS
2
I C SDA, SPI MISO
7
IOHR
I
P1[3]
SPI CLK
8
IOHR
I
P1[1]
ISSP CLK[19], I2C SCL, SPI MOSI
USB D-
I
I
VDD
Power pin
13
IOHR
Power
I
P1[0]
ISSP DATA[19], I2C SDA, SPI
CLKI[20]
14
IOHR
I
P1[2]
15
IOHR
I
P1[4]
16
IOHR
17
I
Input
P1[6]
XRES
18
I/O
I
P3[0]
19
I/O
I
P3[2]
20
I/O
I
P2[0]
21
I/O
I
P2[2]
22
I/O
I
P2[4]
23
I/O
I
P2[6]
24
IOH
I
P0[0]
25
IOH
I
P0[2]
26
IOH
I
P0[4]
27
IOH
I
P0[6]
28
Power
VDD
29
IOH
I
P0[7]
30
IOH
I
P0[5]
31
IOH
I
P0[3]
32
Power
Optional external clock input
(EXTCLK)
VSS
Active high external reset with
internal pull-down
24
23
22
21
20
19
18
17
P0[0] , AI
P2[6] , AI
P2[4] , AI
P2[2] , AI
P2[0] , AI
P3[2] , AI
P3[0] , AI
XRES
[19, 20]
10
Vdd
ISSP
, DATA, I2C SDA, SPI CLK, P1[0]
USB D+
D-
VSS
USB D-
D+
Power
12
Vss
P0 [3], AI
P0 [5], AI
Ground Pin
9
11
SPI CLK , P1 [3]
[19]
ISSP CLK, I2C SCL, SPI MOSI,P1 [ 1 ]
QFN
(Top View)
9
P1[5]
10
11
12
I
Vss
IOHR
XTAL IN , P2 [ 3 ]
AI , P2[ 1 ]
I2C SCL, SPI SS , P 1[ 7]
I2C SDA, SPI MISO , P 1[ 5]
1
2
3
4
5
6
7
8
USB PHY, D+
6
AI , P 0[ 1]
XTAL OUT, P 2 [ 5]
P0 [4], AI
P0 [2], AI
XTAL In
26
25
XTAL Out
P2[3]
15
16
P2[5]
I
AI, P 1[2]
I
I/O
AI, E XTCLK, P 1[4]
AI, P 1[6]
I/O
3
Integrating Input
P0 [7], AI
Vd d
P0 [6], AI
2
P0[1]
29
I
28
27
IOH
Figure 7. CY8C20496A
Description
13
14
1
Name
30
Analog
31
Digital
32
Type
Pin
No.
Power Pin
Integrating Input
Ground Pin
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
18. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
19. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
20. Alternate SPI clock.
Document Number: 001-54459 Rev. *O
Page 14 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
48-pin SSOP (33 Sensing Inputs)
Table 7. Pin Definitions – CY8C20536A, CY8C20546A, and CY8C20566A[21]
Pin
No.
Digital
Analog
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
IOH
IOH
IOH
IOH
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
Name
IOHR
IOHR
IOHR
IOHR
I
I
I
I
IOHR
I
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
NC
NC
P4[3]
P4[1]
NC
P3[7]
P3[5]
P3[3]
P3[1]
NC
NC
P1[7]
P1[5]
P1[3]
P1[1]
VSS
P1[0]
26
27
IOHR
IOHR
I
I
P1[2]
P1[4]
28
29
30
31
32
IOHR
I
P1[6]
NC
NC
NC
NC
I/O
I/O
I
I
I/O
I/O
I/O
I/O
I
I
I
I
33
34
35
36
37
38
39
40
NC
NC
XRES
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
Figure 8. CY8C20536A, CY8C20546A, and CY8C20566A
Description
AI, P0[7]
AI, P0[5]
AI, P0[3]
AI P0[1]
AI , P2[7]
XTALOUT, P2[5]
XTALIN, P2[3]
AI , P2[1]
NC
NC
AI, P4[3]
AI, P4[1]
NC
AI, P3[7]
AI, P3[5]
AI, P3[3]
AI, P3[1]
NC
NC
I2 C SCL, SPI SS, P1[7]
I2 C SDA, SPI MISO, P1[5 ]
SPI CLK, P1[3]
[21]
ISSP CLK, I2 C SCL, SPI MOSI, P1[1 ]
VSS
Integrating Input
Integrating Input
XTAL Out
XTAL In
No connection
No connection
No connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD
P0[6] , AI
P0[4] , AI
P0[2] , AI
P0[0] , AI
P2[6] , AI
P2[4] , AI
P2[2] , AI
P2[0] , AI
P3[6] , AI
P3[4] , AI
P3[2] , AI
P3[0] , AI
XRES
NC
NC
NC
NC
NC
NC
P1[6] , AI
P1[4] , EXT CLK
P1[2] , AI
[21, 22]
P1[0] , ISSP DATA, I2C SDA, SPI CLK
No connection
No connection
I2C SCL, SPI SS
I2C SDA, SPI MISO
SPI CLK
ISSP CLK[21], I2C SCL, SPI MOSI
Ground Pin
ISSP DATA[21], I2C SDA, SPI
CLK[22]
Optional external clock input
(EXT CLK)
No connection
No connection
No connection
No connection
No connection
No connection
Active high external reset with
internal pull-down
P3[0]
P3[2]
P3[4]
P3[6]
P2[0]
Pin
No.
Digital
41
42
43
I/O
I/O
I/O
I
I
I
P2[2]
P2[4]
P2[6]
44
45
46
47
48
IOH
IOH
IOH
IOH
Power
I
I
I
I
P0[0]
P0[2]
P0[4]
P0[6]
VDD
Analog
Name
Description
VREF
Power Pin
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
Notes
21. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
22. Alternate SPI clock.
Document Number: 001-54459 Rev. *O
Page 15 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
48-pin QFN (35 Sensing Inputs)
Table 8. Pin Definitions – CY8C20636A[23, 24]
I
I
I
I
I
I
I
I
I
I
I
I
IOHR
IOHR
I
I
NC
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
NC
NC
P1[3]
P1[1]
18
19
20
21
22
Power
IOHR
I
VSS
DNU
DNU
VDD
P1[0]
23
24
IOHR
IOHR
P1[2]
P1[4]
25
26
IOHR
I
Input
Power
I
I
P1[6]
XRES
27
28
29
I/O
I/O
I/O
I
I
I
P3[0]
P3[2]
P3[4]
30
31
32
33
34
35
36
37
38
39
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOH
IOH
IOH
I
I
I
I
I
I
I
I
I
I
P3[6]
P4[0]
P4[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
No connection
P0[1], AI
Vss
P0[3], AI
P0[5 ], AI
P0[7], AI
NC
NC
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOHR
IOHR
Figure 9. CY8C20636A
Description
Crystal output (XOut)
Crystal input (XIn)
NC
AI ,P2[7]
AI , XOut,P2[5]
AI , XIn ,P2[3]
AI ,P2[1]
AI ,P4[3]
AI ,P4[1]
AI ,P3[7]
AI ,P3[5]
AI ,P3[3]
AI P3[1]
AI ,I2 C SCL, SPI SS,P1[7]
I2C SCL, SPI SS
I2C SDA, SPI MISO
No connection
No connection
SPI CLK
ISSP CLK[23], I2C SCL, SPI
MOSI
Ground connection
48
47
46
45
44
43
42
41
40
39
38
37
Name
1
2
3
4
5
6
7
8
9
10
11
12
QFN
(Top View)
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Digital Analog
36
35
34
33
32
31
30
29
28
27
26
25
P2[6] ,AI
P2[4] AI
,
P2[2] ,AI
P2[0] AI
,
P4[2] ,AI
P4[0] ,AI
P3[6] ,AI
P3[4] , AI
P3[2] ,AI
P3[0] , AI
XRES
P1[6] , AI
I2C SDA, SPI MISO, A I, P1[5]
NC
NC
SPI CLK, AI, P1[3]
[23]
AI, ISSP CLK, I2C SCL, SPI MOSI, P1[1]
Vss
DNU
DNU
[23, 25]
Vdd
AI, ISSP DATA1 , I2C SDA, SPI CLK, P1[0]
AI, P 1[2]
AI, EXTCLK, P1[4]
Pin
No.
Supply voltage
ISSP DATA[23], I2C SDA, SPI
CLK[25]
Optional external clock input
(EXTCLK)
Active high external reset with
internal pull-down
Pin
No.
40
41
42
43
44
45
46
47
48
CP
Digital
IOH
IOH
IOH
IOH
Analog
I
Power
I
I
I
Power
IOH
I
Power
Name
P0[6]
VDD
NC
NC
P0[7]
P0[5]
P0[3]
VSS
P0[1]
VSS
Description
Supply voltage
No connection
No connection
Integrating input
Ground connection
Center pad must be connected to ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Notes
23. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use
alternate pins if you encounter issues.
24. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal
25. Alternate SPI clock.
Document Number: 001-54459 Rev. *O
Page 16 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
48-pin QFN - 35 Sensing Inputs (With USB)
Table 9. Pin Definitions – CY8C20646A, CY8C20646AS, CY8C20666A, CY8C20666AS [26, 27]
Pin
Figure 10. CY8C20646A, CY8C20646AS, CY8C20666A,
Name
Description
No. Digital Analog
CY8C20666AS
25
26
IOHR
I
Input
P1[6]
XRES
27
28
29
I/O
I/O
I/O
I
I
I
P3[0]
P3[2]
P3[4]
30
31
32
33
34
35
36
37
38
39
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOH
IOH
IOH
I
I
I
I
I
I
I
I
I
I
P3[6]
P4[0]
P4[2]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
Crystal output (XOut)
Crystal input (XIn)
NC
AI , P2[7]
AI , XOut, P2[5]
AI , XIn , P2[3]
AI , P2[1]
AI , P4[3]
AI , P4[1]
AI , P3[7]
AI , P3[5]
AI , P3[3]
AI , P3[1]
AI , I2 C SCL, SPI SS, P1[7]
I2C SCL, SPI SS
I2C SDA, SPI MISO
No connection
No connection
SPI CLK
ISSP CLK[26], I2C SCL, SPI MOSI
Ground connection
USB D+
USB DSupply voltage
ISSP DATA[26], I2C SDA, SPI
CLK[28]
Vss
P0[3], AI
P0[5 ], AI
P0[7], AI
NC
NC
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
P1[2]
P1[4]
I
I
P0[1], AI
IOHR
IOHR
No connection
48
47
46
45
44
43
42
41
40
39
38
37
23
24
I
I
I
I
I
I
I
I
I
I
I
I
1
2
3
4
5
6
7
8
9
10
11
12
QFN
(Top View)
13
14
15
16
17
18
19
20
21
22
23
24
IOHR
I
IOHR
I
Power
I/O
I/O
Power
IOHR
I
NC
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
NC
NC
P1[3]
P1[1]
VSS
D+
DVDD
P1[0]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOHR
IOHR
36
35
34
33
32
31
30
29
28
27
26
25
P2[6] , AI
P2[4] ,AI
P2[2] ,AI
P2[0] ,AI
P4[2] ,AI
P4[0] ,AI
P3[6] ,AI
P3[4] , AI
P3[2] ,AI
P3[0] , AI
XRES
P1[6] , AI
I2C SDA, SPI MISO, A I, P1[5]
NC
NC
SPI CLK, A I, P1[3]
[26]
AI,ISSP CLK , I2C SCL, SPI MOSI, P1[1]
Vss
D+
DVdd
[26, 28]
AI,ISSP DATA, I2C SDA, SPI CLK, P1[0]
AI, P1[2]
AI, EXTCLK, P1[4]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Optional external clock input
(EXTCLK)
Active high external reset with
internal pull-down
Pin
No.
40
41
42
43
44
45
46
47
48
CP
Digital
IOH
IOH
IOH
IOH
Analog
I
Power
I
I
I
Power
IOH
I
Power
Name
P0[6]
VDD
NC
NC
P0[7]
P0[5]
P0[3]
VSS
P0[1]
VSS
Description
Supply voltage
No connection
No connection
Integrating input
Ground connection
Center pad must be connected to ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Notes
26. On Power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to High impedance state. On reset, after XRES de- asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance
(5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues.
27. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
28. Alternate SPI clock.
Document Number: 001-54459 Rev. *O
Page 17 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
48-pin QFN (OCD)
18
19
20
21
22
Power
IOHR
I
VSS
D+
DVDD
P1[0]
23
IOHR
I
P1[2]
24
IOHR
I
P1[4]
25
26
IOHR
I
Input
27
28
29
30
31
32
33
34
35
36
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
P1[6]
XRES
Crystal output (XOut)
Crystal input (XIn)
OCDO
A E
, P2[7]
I
AI , XOut, P2[5]
AI , XIn , P2[3]
AI , P2[1]
AI , P4[3]
AI , P4[1]
AI , P3[7]
AI , P3[5]
AI , P3[3]
AI , P3[1]
AI , I2 C SCL, SPI SS, P1[7]
I2C SCL, SPI SS
I2C SDA, SPI MISO
OCD CPU clock output
OCD high speed clock output
SPI CLK.
ISSP CLK[32], I2C SCL, SPI
MOSI
Ground connection
USB D+
USB DSupply voltage
ISSP DATA[32], I2C SDA, SPI
CLK[33]
Optional external clock input
(EXTCLK)
Active high external reset with
internal pull-down
P3[0]
P3[2]
P3[4]
P3[6]
P4[0]
P4[2]
P2[0]
P2[2]
P2[4]
P2[6]
OCDO
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
I
I
OCD mode direction pin
Vss
P0[3], AI
P0[5 ], AI
P0[7], AI
OCDE
IOHR
IOHR
OCDOE
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
CCLK
HCLK
P1[3]
P1[1]
48
47
46
45
44
43
42
41
40
39
38
37
I
I
I
I
I
I
I
I
I
I
I
I
1
2
3
4
5
6
7
8
9
10
11
12
QFN
(Top View)
13
14
15
16
17
18
19
20
21
22
23
24
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IOHR
IOHR
36
35
34
33
32
31
30
29
28
27
26
25
P2[6] , AI
P2[4] , AI
P2[2] , AI
P2[0] , AI
P4[2] , AI
P4[0] , AI
P3[6] , AI
P3[4] , AI
P3[2] , AI
P3[0] , AI
XRES
P1[6] , AI
I2C SDA, SPI MISO, AI, P1[5]
CCLK
HCLK
SPI CLK, A I, P1[3]
[32]
AI,ISSP CLK6, I2C SCL, SPI MOSI, P1[1]
Vss
D+
DVdd
[32, 33]
AI,ISSP DATA1 , I2C SDA, SPI CLK, P1[0]
AI, P1[2]
AI, EXTCLK, P1[4]
No.
1[31]
2
3
4
5
6
7
8
9
10
11
12
13
14[31]
15[31]
16
17
P0[1], AI
The 48-pin QFN part is for the CY8C20066A On-Chip Debug (OCD). Note that this part is only used for in-circuit debugging.
Table 10. Pin Definitions – CY8C20066A [29, 30]
Pin
Figure 11. CY8C20066A
Digital Analog
Name
Description
Pin
No.
37
Digital
Analog
IOH
I
P0[0]
38
39
IOH
IOH
I
I
P0[2]
P0[4]
40
41
42[31]
43[31]
44
45
46
47
48
CP
IOH
I
P0[6]
VDD
OCDO
OCDE
P0[7]
P0[5]
P0[3]
VSS
P0[1]
VSS
Power
IOH
IOH
IOH
I
I
I
Power
IOH
I
Power
Name
Description
Supply voltage
OCD even data I/O
OCD odd data output
Integrating input
Ground connection
Center pad must be connected to
ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Notes
29. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes.
30. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
31. This pin (associated with OCD part only) is required for connecting the device to ICE-Cube In-Circuit Emulator for firmware debugging purpose. To know more about
the usage of ICE-Cube, refer to CY3215-DK PSoC® IN-CIRCUIT EMULATOR KIT GUIDE.
32. On Power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive low for 512 sleep clock cycles and both the pins transition to High impedance state. On reset, after XRES de- asserts, the SDA and the SCL lines drive
resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance
(5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues.
33. Alternate SPI clock.
Document Number: 001-54459 Rev. *O
Page 18 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C20X36A/46A/66A/96A/46AS/66AS PSoC devices. For the
latest electrical specifications, confirm that you have the most recent datasheet by visiting the web at http://www.cypress.com/psoc.
Figure 12. Voltage versus CPU Frequency
5.5V
Vdd Voltage
li d ng
Va rati n
e io
Op Reg
1.71V
750 kHz
3 MHz
CPU
24 MHz
Frequency
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 11. Absolute Maximum Ratings
Conditions
Min
Typ
Max
Units
TSTG
Symbol
Storage temperature
Description
Higher storage temperatures reduce data
retention time. Recommended Storage
Temperature is +25 °C ± 25 °C. Extended
duration storage temperatures above 85 °C
degrades reliability.
–55
+25
+125
°C
VDD
Supply voltage relative to VSS
–
–0.5
–
+6.0
V
VIO
DC input voltage
–
VSS – 0.5
–
VDD + 0.5
V
VIOZ[34]
DC voltage applied to tristate
–
VSS – 0.5
–
VDD + 0.5
V
IMIO
Maximum current into any port pin –
–25
–
+50
mA
ESD
Electrostatic discharge voltage
Human body model ESD
2000
–
–
V
LU
Latch-up current
In accordance with JESD78 standard
–
–
200
mA
Operating Temperature
Table 12. Operating Temperature
Min
Typ
Max
Units
TA
Symbol
Ambient temperature
Description
–
Conditions
–40
–
+85
°C
TC
Commercial temperature range
–
0
70
°C
TJ
Operational die temperature
The temperature rise from ambient to
junction is package specific. Refer the
Thermal Impedances on page 37. The user
must limit the power consumption to comply
with this requirement.
+100
°C
–40
–
Note
34. Port1 pins are hot-swap capable with I/O configured in High-Z mode, and pin input voltage above VDD.
Document Number: 001-54459 Rev. *O
Page 19 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 13. DC Chip-Level Specifications
Symbol
VDD
[35, 36, 37, 38]
Description
Supply voltage
VDDUSB[35, 36, 37, 38] Operating voltage
Conditions
Min
Typ
Max
Units
No USB activity. Refer the table DC POR
and LVD Specifications on page 25
1.71
–
5.50
V
USB activity, USB regulator enabled
4.35
–
5.25
V
USB activity, USB regulator bypassed
3.15
3.3
3.60
V
IDD24
Supply current, IMO = 24 MHz
Conditions are VDD  3.0 V, TA = 25 °C,
CPU = 24 MHz. CapSense running at
12 MHz, no I/O sourcing current
–
2.88
4.00
mA
IDD12
Supply current, IMO = 12 MHz
Conditions are VDD  3.0 V, TA = 25 °C,
CPU = 12 MHz. CapSense running at
12 MHz, no I/O sourcing current
–
1.71
2.60
mA
IDD6
Supply current, IMO = 6 MHz
Conditions are VDD  3.0 V, TA = 25 °C,
CPU = 6 MHz. CapSense running at
6 MHz, no I/O sourcing current
–
1.16
1.80
mA
IDDAVG10
Average supply current per
sensor
One sensor scanned at 10 mS rate
–
250
–
A
IDDAVG100
Average supply current per
sensor
One sensor scanned at 100 mS rate
–
25
–
A
IDDAVG500
Average supply current per
sensor
One sensor scanned at 500 mS rate
–
7
–
A
ISB0
Deep sleep current
VDD  3.0 V, TA = 25 °C, I/O regulator
turned off
–
0.10
1.05
A
ISB1
Standby current with POR, LVD VDD  3.0 V, TA = 25 °C, I/O regulator
and sleep timer
turned off
–
1.07
1.50
A
ISBI2C
Standby current with I2C
enabled
–
1.64
–
A
Conditions are VDD = 3.3 V, TA = 25 °C
and CPU = 24 MHz
Notes
35. When VDD remains in the range from 1.71 V to 1.9 V for more than 50 µs, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be
slower than 1 V/500 µs to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter.
36. If powering down in standby sleep mode, to properly detect and recover from a VDD brown out condition any of the following actions must be taken:
a.Bring the device out of sleep before powering down.
b.Assure that VDD falls below 100 mV before powering back up.
c.Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep.
d.Increase the buzz rate to assure that the falling edge of VDD is captured. The rate is configured through the PSSDC bits in the SLP_CFG register.
For the referenced registers, refer to the CY8C20X36 Technical Reference Manual. In deep sleep mode, additional low power voltage monitoring circuitry allows
VDD brown out conditions to be detected for edge rates slower than 1V/ms.
37. For USB mode, the VDD supply for bus-powered application should be limited to 4.35 V–5.35 V. For self-powered application, VDD should be 3.15 V–3.45 V.
38. For proper CapSense block functionality, if the drop in VDD exceeds 5% of the base VDD, the rate at which VDD drops should not exceed 200 mV/s. Base VDD can
be between 1.8 V and 5.5 V
Document Number: 001-54459 Rev. *O
Page 20 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
DC GPIO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and
–40 °C  TA  85 °C, 2.4 V to 3.0 V and –40 °C  TA  85 °C, or 1.71 V to 2.4 V and –40 °C  TA  85 °C, respectively. Typical
parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only.
Table 14. 3.0 V to 5.5 V DC GPIO Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
RPU
Pull-up resistor
–
4
5.60
8
k
VOH1
High output voltage
Port 2 or 3 or 4 pins
IOH < 10 A, maximum of 10 mA source
current in all I/Os
VDD – 0.20
–
–
V
VOH2
High output voltage
Port 2 or 3 or 4 pins
IOH = 1 mA, maximum of 20 mA source
current in all I/Os
VDD – 0.90
–
–
V
VOH3
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for port 1
IOH < 10 A, maximum of 10 mA source
current in all I/Os
VDD – 0.20
–
–
V
VOH4
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for port 1
IOH = 5 mA, maximum of 20 mA source
current in all I/Os
VDD – 0.90
–
–
V
VOH5
High output voltage
IOH < 10 A, VDD > 3.1 V, maximum of 4 I/Os
Port 1 Pins with LDO Regulator Enabled all sourcing 5 mA
for 3 V out
2.85
3.00
3.30
V
VOH6
High output voltage
IOH = 5 mA, VDD > 3.1 V, maximum of 20 mA
Port 1 pins with LDO regulator enabled for source current in all I/Os
3 V out
2.20
–
–
V
VOH7
High output voltage
IOH < 10 A, VDD > 2.7 V, maximum of 20 mA
Port 1 pins with LDO enabled for 2.5 V out source current in all I/Os
2.35
2.50
2.75
V
VOH8
High output voltage
IOH = 2 mA, VDD > 2.7 V, maximum of 20 mA
Port 1 pins with LDO enabled for 2.5 V out source current in all I/Os
1.90
–
–
V
VOH9
High output voltage
IOH < 10 A, VDD > 2.7 V, maximum of 20 mA
Port 1 pins with LDO enabled for 1.8 V out source current in all I/Os
1.60
1.80
2.10
V
VOH10
High output voltage
IOH = 1 mA, VDD > 2.7 V, maximum of 20 mA
Port 1 pins with LDO enabled for 1.8 V out source current in all I/Os
1.20
–
–
V
VOL
Low output voltage
IOL = 25 mA, VDD > 3.3 V, maximum of
60 mA sink current on even port pins (for
example, P0[2] and P1[4]) and 60 mA sink
current on odd port pins (for example, P0[3]
and P1[5])
–
–
0.75
V
VIL
Input low voltage
–
–
–
0.80
V
VIH
Input high voltage
–
2.00
–
–
V
VH
Input hysteresis voltage
–
–
80
–
mV
IIL
Input leakage (Absolute Value)
–
–
0.001
1
A
CPIN
Pin capacitance
Package and pin dependent
Temp = 25 °C
0.50
1.70
7
pF
VILLVT3.3
Input Low Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input
0.8
V
–
–
VIHLVT3.3
Input High Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input
1.4
–
–
V
VILLVT5.5
Input Low Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input
0.8
V
–
–
VIHLVT5.5
Input High Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input
1.7
–
–
V
Document Number: 001-54459 Rev. *O
Page 21 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Table 15. 2.4 V to 3.0 V DC GPIO Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
4
5.60
8
k
IOH < 10 A, maximum of 10 mA source
current in all I/Os
VDD – 0.20
–
–
V
High output voltage
Port 2 or 3 or 4 pins
IOH = 0.2 mA, maximum of 10 mA source
current in all I/Os
VDD – 0.40
–
–
V
VOH3
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for port 1
IOH < 10 A, maximum of 10 mA source
current in all I/Os
VDD – 0.20
–
–
V
VOH4
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for Port 1
IOH = 2 mA, maximum of 10 mA source
current in all I/Os
VDD – 0.50
–
–
V
VOH5A
High output voltage
IOH < 10 A, VDD > 2.4 V, maximum of
Port 1 pins with LDO enabled for 1.8 V out 20 mA source current in all I/Os
1.50
1.80
2.10
V
VOH6A
High output voltage
IOH = 1 mA, VDD > 2.4 V, maximum of 20 mA
Port 1 pins with LDO enabled for 1.8 V out source current in all I/Os
1.20
–
–
V
VOL
Low output voltage
–
–
0.75
V
VIL
Input low voltage
–
–
–
0.72
VIH
Input high voltage
–
1.40
–
VH
Input hysteresis voltage
–
–
80
–
mV
IIL
Input leakage (absolute value)
–
–
1
1000
nA
CPIN
Capacitive load on pins
Package and pin dependent
Temp = 25 C
0.50
1.70
7
pF
VILLVT2.5
Input Low Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input
0.7
V
–
VIHLVT2.5
Input High Voltage with low threshold
enable set, Enable for Port1
Bit3 of IO_CFG1 set to enable low threshold
voltage of Port1 input
1.2
RPU
Pull-up resistor
–
VOH1
High output voltage
Port 2 or 3 or 4 pins
VOH2
IOL = 10 mA, maximum of 30 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink current on
odd port pins (for example, P0[3] and P1[5])
V
V
–
V
Table 16. 1.71 V to 2.4 V DC GPIO Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
4
RPU
Pull-up resistor
–
5.60
8
k
VOH1
High output voltage
Port 2 or 3 or 4 pins
IOH = 10 A, maximum of 10 mA VDD – 0.20
source current in all I/Os
–
–
V
VOH2
High output voltage
Port 2 or 3 or 4 pins
IOH = 0.5 mA, maximum of 10 mA VDD – 0.50
source current in all I/Os
–
–
V
VOH3
High output voltage
Port 0 or 1 pins with LDO regulator
Disabled for Port 1
IOH = 100 A, maximum of 10 mA VDD – 0.20
source current in all I/Os
–
–
V
VOH4
High output voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH = 2 mA, maximum of 10 mA source VDD – 0.50
current in all I/Os
–
–
V
VOL
Low output voltage
IOL = 5 mA, maximum of 20 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
–
0.40
V
Document Number: 001-54459 Rev. *O
–
Page 22 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Table 16. 1.71 V to 2.4 V DC GPIO Specifications (continued)
Symbol
Description
Conditions
Min
Typ
Max
Units
VIL
Input low voltage
–
–
–
0.30 × VDD
V
VIH
Input high voltage
–
0.65 × VDD
–
–
V
VH
Input hysteresis voltage
–
–
80
–
mV
IIL
Input leakage (absolute value)
–
–
1
1000
nA
CPIN
Capacitive load on pins
Package and pin dependent
temp = 25 °C
0.50
1.70
7
pF
Min
Typ
Max
Units
Table 17. DC Characteristics – USB Interface
Symbol
Description
Conditions
RUSBI
USB D+ pull-up resistance
With idle bus
900
–
1575

RUSBA
USB D+ pull-up resistance
While receiving traffic
1425
–
3090

VOHUSB
Static output high
–
2.8
–
3.6
V
VOLUSB
Static output low
–
–
–
0.3
V
VDI
Differential input sensitivity
–
0.2
–
VCM
Differential input common mode range
–
0.8
–
2.5
V
VSE
Single ended receiver threshold
–
0.8
–
2.0
V
CIN
Transceiver capacitance
–
–
–
50
pF
V
IIO
High Z state data line leakage
On D+ or D- line
–10
–
+10
A
RPS2
PS/2 pull-up resistance
–
3000
5000
7000

REXT
External USB series resistor
In series with each USB pin
21.78
22.0
22.22

DC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 18. DC Analog Mux Bus Specifications
Symbol
RSW
Description
Conditions
Switch resistance to common analog bus –
RGND
Resistance of initialization switch to VSS
The maximum pin voltage for measuring RSW and RGND is 1.8 V
–
Min
Typ
Max
Units
–
–
800

–
–
800

DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 19. DC Comparator Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
0.0
–
1.8
V
VLPC
Low power comparator (LPC) common
mode
Maximum voltage limited to VDD
ILPC
LPC supply current
–
–
10
40
A
VOSLPC
LPC voltage offset
–
–
3
30
mV
Document Number: 001-54459 Rev. *O
Page 23 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Comparator User Module Electrical Specifications
The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the
entire device voltage and temperature operating range: –40 °C  TA  85 °C, 1.71 V  VDD  5.5 V.
Table 20. Comparator User Module Electrical Specifications
Symbol
Min
Typ
Max
Units
50 mV overdrive
–
70
100
ns
Offset
Valid from 0.2 V to VDD – 0.2 V
–
2.5
30
mV
Current
Average DC current, 50 mV
overdrive
–
20
80
µA
Supply voltage > 2 V
Power supply rejection ratio
–
80
–
dB
Supply voltage < 2 V
Power supply rejection ratio
–
40
–
dB
–
0
1.5
V
tCOMP
PSRR
Description
Comparator response time
Input range
Conditions
ADC Electrical Specifications
Table 21. ADC User Module Electrical Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
0
–
VREFADC
V
–
–
5
pF
Input
VIN
Input voltage range
CIIN
Input capacitance
–
RIN
Input resistance
Equivalent switched cap input
resistance for 8-, 9-, or 10-bit
resolution
ADC reference voltage
–
1.14
–
1.26
V
2.25
–
6
MHz
–
1/(500fF × 1/(400fF × 1/(300fF ×
data clock) data clock) data clock)

Reference
VREFADC
Conversion Rate
FCLK
Data clock
Source is chip’s internal main
oscillator. See AC Chip-Level
Specifications for accuracy
S8
8-bit sample rate
Data clock set to 6 MHz. sample
rate = 0.001/ (2^Resolution/Data
Clock)
–
23.43
–
ksps
S10
10-bit sample rate
Data clock set to 6 MHz. sample
rate = 0.001/ (2^resolution/data
clock)
–
5.85
–
ksps
RES
Resolution
Can be set to 8-, 9-, or 10-bit
8
–
10
bits
DC Accuracy
DNL
Differential nonlinearity
–
–1
–
+2
LSB
INL
Integral nonlinearity
–
–2
–
+2
LSB
EOFFSET
Offset error
8-bit resolution
0
3.20
19.20
LSB
10-bit resolution
0
12.80
76.80
LSB
Gain error
For any resolution
–5
–
+5
%FSR
IADC
Operating current
–
–
2.10
2.60
mA
PSRR
Power supply rejection ratio
PSRR (VDD > 3.0 V)
–
24
–
dB
PSRR (VDD < 3.0 V)
–
30
–
dB
EGAIN
Power
Document Number: 001-54459 Rev. *O
Page 24 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 22. DC POR and LVD Specifications
Symbol
Description
Conditions
Min
VPOR0
1.66 V selected in PSoC Designer
2.36 V selected in PSoC Designer
–
VPOR2
2.60 V selected in PSoC Designer
VDD must be greater than or equal
to 1.71 V during startup, reset
from the XRES pin, or reset from
watchdog.
1.61
VPOR1
–
2.60
2.66
VPOR3
2.82 V selected in PSoC Designer
–
2.82
2.95
VLVD0
2.45 V selected in PSoC Designer
2.40
2.45
2.51
VLVD1
2.71 V selected in PSoC Designer
2.64[39]
2.71
2.78
VLVD2
2.92 V selected in PSoC Designer
2.85[40]
2.92
2.99
VLVD3
3.02 V selected in PSoC Designer
2.95[41]
3.02
3.09
VLVD4
3.13 V selected in PSoC Designer
3.06
3.13
3.20
VLVD5
1.90 V selected in PSoC Designer
1.84
1.90
2.32
VLVD6
1.80 V selected in PSoC Designer
1.75[42]
1.80
1.84
VLVD7
4.73 V selected in PSoC Designer
4.62
4.73
4.83
–
Typ
Max
Units
1.66
1.71
V
2.36
2.41
V
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 23. DC Programming Specifications
Symbol
VDDIWRITE
IDDP
VILP
VIHP
IILP
IIHP
VOLP
VOHP
FlashENPB
FlashDR
Description
Supply voltage for flash write
operations
Supply current during
programming or verify
Input low voltage during
programming or verify
Input high voltage during
programming or verify
Input current when Applying VILP
to P1[0] or P1[1] during
programming or verify
Input current when applying VIHP
to P1[0] or P1[1] during
programming or verify
Output low voltage during
programming or verify
Output high voltage during
programming or verify
Flash write endurance
Flash data retention
–
Conditions
Min
1.71
Typ
–
Max
5.25
Units
V
–
–
5
25
mA
See the appropriate DC GPIO
Specifications on page 21
See the appropriate DC GPIO
Specifications on page 21
Driving internal pull-down resistor
–
–
VIL
V
VIH
–
–
V
–
–
0.2
mA
–
–
1.5
mA
–
–
VSS + 0.75
V
VOH
–
VDD
V
50,000
20
–
–
–
–
–
Years
Driving internal pull-down resistor
See
appropriate
DC
GPIO
Specifications on page 21. For
VDD > 3 V use VOH4 in Table 12 on
page 19.
Erase/write cycles per block
Following maximum Flash write
cycles; ambient temperature of 55 °C
Notes
39. Always greater than 50 mV above VPPOR1 voltage for falling supply.
40. Always greater than 50 mV above VPPOR2 voltage for falling supply.
41. Always greater than 50 mV above VPPOR3 voltage for falling supply.
42. Always greater than 50 mV above VPPOR0 voltage for falling supply.
Document Number: 001-54459 Rev. *O
Page 25 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
DC I2C Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and
–40 °C  TA  85 °C, 2.4 V to 3.0 V and –40 °C  TA  85 °C, or 1.71 V to 2.4 V and –40 °C  TA  85 °C, respectively. Typical
parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only.
Table 24. DC I2C Specifications
Symbol
VILI2C
VIHI2C
Description
Input low level
Input high level
Conditions
3.1 V ≤ VDD ≤ 5.5 V
Min
–
Typ
–
Max
Units
0.25 × VDD
V
2.5 V ≤ VDD ≤ 3.0 V
–
–
0.3 × VDD
V
1.71 V ≤ VDD ≤ 2.4 V
–
–
0.3 × VDD
V
1.71 V ≤ VDD ≤ 5.5 V
0.65 × VDD
–
–
V
DC Reference Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and
–40 °C  TA  85 °C, 2.4 V to 3.0 V and –40 °C  TA  85 °C, or 1.71 V to 2.4 V and –40 °C  TA  85 °C, respectively. Typical
parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only.
Table 25. DC Reference Buffer Specifications
Symbol
VRef
Description
Reference buffer output
Conditions
1.7 V ≤ VDD ≤ 5.5 V
Min
1
Typ
–
Max
1.05
Units
V
VRefHi
Reference buffer output
1.7 V ≤ VDD ≤ 5.5 V
1.2
–
1.25
V
DC IDAC Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 26. DC IDAC Specifications
Symbol
IDAC_DNL
IDAC_INL
IDAC_Gain
(Source)
Description
Differential nonlinearity
Integral nonlinearity
Range = 0.5x
Range = 1x
Range = 2x
Range = 4x
Range = 8x
Document Number: 001-54459 Rev. *O
Min
–4.5
–5
6.64
14.5
42.7
91.1
184.5
Typ
–
–
–
–
–
–
–
Max
+4.5
+5
22.46
47.8
92.3
170
426.9
Units
LSB
LSB
µA
µA
µA
µA
µA
Notes
DAC setting = 128 dec.
Not recommended for CapSense
applications.
DAC setting = 128 dec
DAC setting = 128 dec
Page 26 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 27. AC Chip-Level Specifications
Min
Typ
Max
Units
FIMO24
Symbol
IMO frequency at 24 MHz Setting
Description
–
Conditions
22.8
24
25.2
MHz
FIMO12
IMO frequency at 12 MHz setting
–
11.4
12
12.6
MHz
FIMO6
IMO frequency at 6 MHz setting
–
5.7
6.0
6.3
MHz
FCPU
CPU frequency
–
0.75
–
25.20
MHz
F32K1
ILO frequency
–
19
32
50
kHz
F32K_U
ILO untrimmed frequency
–
13
32
82
kHz
DCIMO
Duty cycle of IMO
–
40
50
60
%
DCILO
ILO duty cycle
–
40
50
60
%
SRPOWER_UP
Power supply slew rate
VDD slew rate during power-up
–
–
250
V/ms
tXRST
External reset pulse width at power-up After supply voltage is valid
1
–
–
ms
tXRST2
External reset pulse width after
power-up[43]
Applies after part has booted
10
–
–
s
tOS
Startup time of ECO
–
–
1
–
s
tJIT_IMO[44]
N=32
6 MHz IMO cycle-to-cycle jitter (RMS)
–
0.7
6.7
ns
6 MHz IMO long term N (N = 32)
cycle-to-cycle jitter (RMS)
–
4.3
29.3
ns
6 MHz IMO period jitter (RMS)
–
0.7
3.3
ns
12 MHz IMO cycle-to-cycle jitter (RMS)
–
0.5
5.2
ns
12 MHz IMO long term N (N = 32)
cycle-to-cycle jitter (RMS)
–
2.3
5.6
ns
12 MHz IMO period jitter (RMS)
–
0.4
2.6
ns
24 MHz IMO cycle-to-cycle jitter (RMS)
–
1.0
8.7
ns
24 MHz IMO long term N (N = 32)
cycle-to-cycle jitter (RMS)
–
1.4
6.0
ns
24 MHz IMO period jitter (RMS)
–
0.6
4.0
ns
Notes
43. The minimum required XRES pulse length is longer when programming the device (see Table 33 on page 30).
44. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 001-54459 Rev. *O
Page 27 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
AC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 28. AC GPIO Specifications
Symbol
FGPIO
tRISE23
tRISE23L
tRISE01
tRISE01L
tFALL
tFALLL
Description
GPIO operating frequency
Conditions
Normal strong mode Port 0, 1
Rise time, strong mode, Cload = 50 pF
Port 2 or 3 or 4 pins
Rise time, strong mode low supply,
Cload = 50 pF, Port 2 or 3 or 4 pins
Rise time, strong mode, Cload = 50 pF
Ports 0 or 1
Rise time, strong mode low supply,
Cload = 50 pF, Ports 0 or 1
Fall time, strong mode, Cload = 50 pF
all ports
Fall time, strong mode low supply,
Cload = 50 pF, all ports
Min
0
Typ
–
Max
Units
6 MHz for
MHz
1.71 V <VDD < 2.40 V
MHz
12 MHz for
2.40 V < VDD< 5.50 V
80
ns
0
–
VDD = 3.0 to 3.6 V, 10% to 90%
15
–
VDD = 1.71 to 3.0 V, 10% to 90%
15
–
80
ns
VDD = 3.0 to 3.6 V, 10% to 90%
LDO enabled or disabled
VDD = 1.71 to 3.0 V, 10% to 90%
LDO enabled or disabled
VDD = 3.0 to 3.6 V, 10% to 90%
10
–
50
ns
10
–
80
ns
10
–
50
ns
VDD = 1.71 to 3.0 V, 10% to 90%
10
–
70
ns
Figure 13. GPIO Timing Diagram
90%
GPIO Pin
Output
Voltage
10%
tRISE23
tRISE01
tRISE23L
tRISE01L
Document Number: 001-54459 Rev. *O
tFALL
tFALLL
Page 28 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Table 29. AC Characteristics – USB Data Timings
Min
Typ
tDRATE
Symbol
Full speed data rate
Description
Average bit rate
Conditions
12 – 0.25%
12
Max
Units
tJR1
Receiver jitter tolerance
To next transition
–18.5
–
18.5
ns
tJR2
Receiver jitter tolerance
To pair transition
–9.0
–
9
ns
tDJ1
FS Driver jitter
To next transition
–3.5
–
3.5
ns
tDJ2
FS Driver jitter
To pair transition
–4.0
–
4.0
ns
tFDEOP
Source jitter for differential
transition
To SE0 transition
–2.0
–
5
ns
12 + 0.25% MHz
tFEOPT
Source SE0 interval of EOP
–
160.0
–
175
ns
tFEOPR
Receiver SE0 interval of EOP
–
82.0
–
–
ns
tFST
Width of SE0 interval during
differential transition
–
–
–
14
ns
Min
Typ
Max
Units
Table 30. AC Characteristics – USB Driver
Symbol
Description
Conditions
tFR
Transition rise time
50 pF
4
–
20
ns
tFF
Transition fall time
50 pF
4
–
20
ns
tFRFM[45]
Rise/fall time matching
–
90
–
111
%
VCRS
Output signal crossover voltage
–
1.30
–
2.00
V
AC Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 31. AC Low Power Comparator Specifications
Symbol
tLPC
Description
Comparator response time,
50 mV overdrive
Conditions
50 mV overdrive does not include
offset voltage.
Min
Typ
Max
Units
–
–
100
ns
AC External Clock Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 32. AC External Clock Specifications
Symbol
FOSCEXT
Description
Frequency (external oscillator
frequency)
Conditions
–
Min
Typ
Max
Units
0.75
–
25.20
MHz
High period
–
20.60
–
5300
ns
Low period
–
20.60
–
–
ns
Power-up IMO to switch
–
150
–
–
s
Note
45. TFRFM is not met under all conditions. There is a corner case at lower supply voltages, such as those under 3.3 V. This condition does not affect USB communications.
Signal integrity tests show an excellent eye diagram at 3.15 V.
Document Number: 001-54459 Rev. *O
Page 29 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
AC Programming Specifications
Figure 14. AC Waveform
SCLK (P1[1])
T FSCLK
T RSCLK
SDATA (P1[0])
TSSCLK
T HSCLK
TDSCLK
The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 33. AC Programming Specifications
Symbol
tRSCLK
tFSCLK
tSSCLK
tHSCLK
FSCLK
tERASEB
tWRITE
tDSCLK
tDSCLK3
tDSCLK2
tXRST3
Description
Rise time of SCLK
Fall time of SCLK
Data setup time to falling edge of SCLK
Data hold time from falling edge of SCLK
Frequency of SCLK
Flash erase time (block)
Flash block write time
Data out delay from falling edge of SCLK
Data out delay from falling edge of SCLK
Data out delay from falling edge of SCLK
External reset pulse width after power-up
Conditions
–
–
–
–
–
–
–
3.6  VDD
3.0  VDD  3.6
1.71  VDD  3.0
Required to enter programming
mode when coming out of sleep
Min
1
1
40
40
0
–
–
–
–
–
300
Typ
–
–
–
–
–
–
–
–
–
–
–
Max
20
20
–
–
8
18
25
60
85
130
–
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
ns
s
tXRES
tVDDWAIT[46]
tVDDXRES[46]
tPOLL
tACQ[46]
XRES pulse length
VDD stable to wait-and-poll hold off
VDD stable to XRES assertion delay
SDATA high pulse time
“Key window” time after a VDD ramp
acquire event, based on 256 ILO clocks.
–
–
–
–
–
300
0.1
14.27
0.01
3.20
–
–
–
–
–
–
1
–
200
19.60
s
ms
ms
ms
ms
tXRESINI[46]
“Key window” time after an XRES event,
based on 8 ILO clocks
–
98
–
615
s
Note
46. Valid from 5 to 50 °C. See the spec, CY8C20X66, CY8C20X46, CY8C20X36, CY7C643XX, CY7C604XX, CY8CTST2XX, CY8CTMG2XX, CY8C20X67, CY8C20X47,
CY8C20X37, Programming Spec for more details.
Document Number: 001-54459 Rev. *O
Page 30 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 34. AC Characteristics of the I2C SDA and SCL Pins
Symbol
fSCL
tHD;STA
tLOW
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
tSP
Description
SCL clock frequency
Hold time (repeated) START condition. After this period, the first
clock pulse is generated
LOW period of the SCL clock
HIGH Period of the SCL clock
Setup time for a repeated START condition
Data hold time
Data setup time
Setup time for STOP condition
Bus free time between a STOP and START condition
Pulse width of spikes are suppressed by the input filter
Standard Mode
Min
Max
0
100
4.0
–
4.7
4.0
4.7
0
250
4.0
4.7
–
–
–
–
3.45
–
–
–
–
Fast Mode
Min
Max
0
400
0.6
–
1.3
0.6
0.6
0
100[47]
0.6
1.3
0
–
–
–
0.90
–
–
–
50
Units
kHz
µs
µs
µs
µs
µs
ns
µs
µs
ns
Figure 15. Definition for Timing for Fast/Standard Mode on the I2C Bus
Note
47. A Fast-Mode I2C-bus device can be used in a standard mode I2C-bus system, but the requirement tSU;DAT  250 ns must then be met. This automatically be the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-54459 Rev. *O
Page 31 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Table 35. SPI Master AC Specifications
Min
Typ
Max
Units
FSCLK
Symbol
SCLK clock frequency
Description
VDD 2.4 V
VDD < 2.4 V
Conditions
–
–
–
–
6
3
MHz
MHz
DC
SCLK duty cycle
–
–
50
–
%
tSETUP
MISO to SCLK setup time
VDD  2.4 V
VDD < 2.4 V
60
100
–
–
–
–
ns
ns
tHOLD
SCLK to MISO hold time
–
40
–
–
ns
tOUT_VAL
SCLK to MOSI valid time
–
–
–
40
ns
tOUT_H
MOSI high time
–
40
–
–
ns
Figure 16. SPI Master Mode 0 and 2
SPI Master, modes 0 and 2
1/FSCLK
THIGH
TLOW
SCLK
(mode 0)
SCLK
(mode 2)
TSETUP
MISO
(input)
THOLD
LSB
MSB
TOUT_SU
TOUT_H
MOSI
(output)
Figure 17. SPI Master Mode 1 and 3
SPI Master, modes 1 and 3
1/FSCLK
THIGH
TLOW
SCLK
(mode 1)
SCLK
(mode 3)
TSETUP
MISO
(input)
THOLD
TOUT_SU
MOSI
(output)
Document Number: 001-54459 Rev. *O
LSB
MSB
TOUT_H
MSB
LSB
Page 32 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Table 36. SPI Slave AC Specifications
Symbol
FSCLK
tLOW
tHIGH
tSETUP
tHOLD
tSS_MISO
tSCLK_MISO
tSS_HIGH
tSS_CLK
tCLK_SS
Description
SCLK clock frequency
SCLK low time
SCLK high time
MOSI to SCLK setup time
SCLK to MOSI hold time
SS high to MISO valid
SCLK to MISO valid
SS high time
Time from SS low to first SCLK
Time from last SCLK to SS high
Conditions
Min
–
42
42
30
50
–
–
50
2/SCLK
2/SCLK
–
–
–
–
–
–
–
–
–
–
Typ
–
–
–
–
–
–
–
–
–
–
Max
4
–
–
–
–
153
125
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 18. SPI Slave Mode 0 and 2
SPI Slave, modes 0 and 2
TCLK_SS
TSS_CLK
TSS_HIGH
/SS
1/FSCLK
THIGH
TLOW
SCLK
(mode 0)
SCLK
(mode 2)
TOUT_H
TSS_MISO
MISO
(output)
TSETUP
MOSI
(input)
THOLD
LSB
MSB
Figure 19. SPI Slave Mode 1 and 3
SPI Slave, modes 1 and 3
TSS_CLK
TCLK_SS
/SS
1/FSCLK
THIGH
TLOW
SCLK
(mode 1)
SCLK
(mode 3)
TOUT_H
TSCLK_MISO
TSS_MISO
MISO
(output)
MSB
TSETUP
MOSI
(input)
Document Number: 001-54459 Rev. *O
LSB
THOLD
MSB
LSB
Page 33 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Packaging Information
This section illustrates the packaging specifications for the CY8C20X36A/46A/66A/96A/46AS/66AS PSoC device, along with the
thermal impedances for each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 20. 16-pin QFN (No E-Pad) (3 × 3 × 0.6 mm) LG16A (Sawn) Package Outline, 001-09116
001-09116 *F
Figure 21. 24-pin QFN (4 × 4 × 0.55 mm) LQ24A 2.65 × 2.65 E-Pad (Sawn) Package Outline, 001-13937
001-13937 *D
Document Number: 001-54459 Rev. *O
Page 34 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Figure 22. 32-pin QFN (5 × 5 × 0.55 mm) LQ32 3.5 × 3.5 E-Pad (Sawn) Package Outline, 001-42168
001-42168 *D
Figure 23. 48-pin SSOP (300 Mils) O483 Package Outline, 51-85061
51-85061 *E
Document Number: 001-54459 Rev. *O
Page 35 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Figure 24. 48-pin QFN (7 × 7 × 1.0 mm) LT48A 5.1 × 5.1 E-Pad (Sawn) Package Outline, 001-13191
001-13191 *F
Figure 25. 48-pin QFN (6 × 6 × 0.6 mm) LQ48A 4.6 × 4.6 E-Pad (Sawn) Package Outline, 001-57280
001-57280 *C
Important Notes
For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
■ Pinned vias for thermal conduction are not required for the low power PSoC device.
■
Document Number: 001-54459 Rev. *O
Page 36 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Thermal Impedances
Table 37. Thermal Impedances per Package
Typical JA [48]
Typical JC
16-pin QFN (No Center Pad)
33 C/W
–
24-pin QFN [49]
21 C/W
–
[49]
20 C/W
–
69 C/W
–
Package
32-pin QFN
48-pin SSOP
[49]
25.20 C/W
3.04 C/W
48-pin QFN (7 × 7 × 1.0 mm) [49]
18 C/W
–
30-ball WLCSP
54 C/W
–
48-pin QFN (6 × 6 × 0.6 mm)
Capacitance on Crystal Pins
Table 38. Typical Package Capacitance on Crystal Pins
Package
Package Capacitance
32-pin QFN
3.2 pF
48-pin QFN
3.3 pF
Solder Reflow Specifications
Table 39 shows the solder reflow temperature limits that must not be exceeded.
Table 39. Solder Reflow Specifications
Package
Maximum Peak Temperature (TC)
Maximum Time above TC – 5 °C
16-pin QFN
260 C
30 seconds
24-pin QFN
260 C
30 seconds
32-pin QFN
260 C
30 seconds
48-pin SSOP
260 C
30 seconds
48-pin QFN (6 × 6 × 0.6 mm)
260 C
30 seconds
48-pin QFN (7 × 7 × 1.0 mm)
260 C
30 seconds
30-ball WLCSP
260 C
30 seconds
Notes
48. TJ = TA + Power × JA.
49. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane.
Document Number: 001-54459 Rev. *O
Page 37 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Development Tool Selection
Software
PSoC Designer™
At the core of the PSoC development software suite is PSoC
Designer. Utilized by thousands of PSoC developers, this robust
software has been facilitating PSoC designs for over half a
decade. PSoC Designer is available free of charge at
http://www.cypress.com.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC Programmer is available free of charge
at http://www.cypress.com.
Development Kits
All development kits are sold at the Cypress Online Store.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface enables users to run, halt, and single step the
processor and view the content of specific memory locations.
PSoC Designer supports the advance emulation features also.
The kit includes:
■
28-pin CY8C29466A-24PXI PDIP PSoC Device Sample
■
28-pin CY8C27443A-24PXI PDIP PSoC Device Sample
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of
breadboarding space to meet all of your evaluation needs. The
kit includes:
■
Evaluation Board with LCD Module
■
MiniProg Programming Unit
■
28-Pin CY8C29466A-24PXI PDIP PSoC Device Sample (2)
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
CY3280-20X66 Universal CapSense Controller
The CY3280-20X66 CapSense Controller Kit is designed for
easy prototyping and debug of CY8C20XX6A CapSense Family
designs with pre-defined control circuitry and plug-in hardware.
Programming hardware and an I2C-to-USB bridge are included
for tuning and data acquisition.
■
PSoC Designer Software CD
The kit includes:
■
ICE-Cube In-Circuit Emulator
■
CY3280-20X66 CapSense Controller Board
■
ICE Flex-Pod for CY8C29X66A Family
■
CY3240-I2USB Bridge
■
Cat-5 Adapter
■
CY3210 MiniProg1 Programmer
■
Mini-Eval Programming Board
■
USB 2.0 Retractable Cable
■
110 ~ 240 V Power Supply, Euro-Plug Adapter
■
CY3280-20X66 Kit CD
■
iMAGEcraft C Compiler (Registration Required)
■
ISSP Cable
■
USB 2.0 Cable and Blue Cat-5 Cable
All device programmers are purchased from the Cypress Online
Store.
■
2 CY8C29466A-24PXI 28-PDIP Chip Samples
CY3216 Modular Programmer
Evaluation Tools
All evaluation tools are sold at the Cypress Online Store.
CY3210-MiniProg1
The CY3210-MiniProg1 kit enables the user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
MiniProg Programming Unit
■
MiniEval Socket Programming and Evaluation Board
Document Number: 001-54459 Rev. *O
Device Programmers
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■
Modular Programmer Base
■
Three Programming Module Cards
■
MiniProg Programming Unit
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
Page 38 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production programming environment.
Note that CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
■
CY3207 Programmer Unit
■
PSoC ISSP Software CD
■
110 ~ 240 V Power Supply, Euro-Plug Adapter
■
USB 2.0 Cable
Accessories (Emulation and Programming)
Table 40. Emulation and Programming Accessories
Part Number
Pin Package
Flex-Pod Kit[50]
Foot Kit[51]
Adapter[52]
CY8C20236A-24LKXI
16-pin QFN (No E-Pad) CY3250-20246QFN
CY3250-20246QFN-POD
See note 49
CY8C20246A-24LKXI
16-pin QFN (No E-Pad) CY3250-20246QFN
CY3250-20246QFN-POD
See note 52
CY8C20246AS-24LKXI
16-pin QFN (No E-Pad)
CY8C20336A-24LQXI
24-pin QFN
CY3250-20346QFN
CY3250-20346QFN-POD
See note 49
CY8C20346A-24LQXI
24-pin QFN
CY3250-20346QFN
CY3250-20346QFN-POD
See note 52
CY8C20346AS-24LQXI
24-pin QFN
Not Supported
Not Supported
CY8C20396A-24LQXI
24-pin QFN
CY8C20436A-24LQXI
32-pin QFN
CY3250-20466QFN
CY3250-20466QFN-POD
Not Supported
See note 49
CY8C20446A-24LQXI
32-pin QFN
CY3250-20466QFN
CY3250-20466QFN-POD
See note 52
CY8C20446AS-24LQXI
32-pin QFN
Not Supported
CY8C20466A-24LQXI
32-pin QFN
CY8C20466AS-24LQXI
32-pin QFN
CY3250-20466QFN
CY3250-20466QFN-POD
See note 52
CY8C20496A-24LQXI
32-pin QFN
CY8C20536A-24PVXI
48-pin SSOP
CY3250-20566
CY3250-20566-POD
See note 52
CY8C20546A-24PVXI
48-pin SSOP
CY3250-20566
CY3250-20566-POD
See note 52
CY8C20566A-24PVXI
48-pin SSOP
CY3250-20566
CY3250-20566-POD
See note 52
Not Supported
Not Supported
Third Party Tools
Several tools have been specially designed by third-party vendors to accompany PSoC devices during development and production.
Specific details for each of these tools can be found at http://www.cypress.com under Documentation > Evaluation Boards.
Build a PSoC Emulator into Your Board
For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC
device, refer Application Note Debugging - Build a PSoC Emulator into Your Board – AN2323.
Notes
50. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
51. Foot kit includes surface mount feet that can be soldered to the target PCB.
52. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
Document Number: 001-54459 Rev. *O
Page 39 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Ordering Information
The following table lists the CY8C20X36A/46A/66A/96A/46AS/66AS PSoC devices' key package features and ordering codes.
Table 41. PSoC Device Key Features and Ordering Information
Package
Ordering Code
Flash SRAM CapSense Digital
Analog XRES USB ADC
(Bytes) (Bytes) Blocks I/O Pins Inputs [53] Pin
16-pin (3 × 3 × 0.6 mm) QFN
(no E-Pad)
CY8C20236A-24LKXI
8K
1K
1
13
13
Yes
No
Yes
16-pin (3 × 3 × 0.6 mm) QFN
(no E-Pad) (Tape and Reel)
CY8C20236A-24LKXIT
8K
1K
1
13
13
Yes
No
Yes
16-pin (3 × 3 × 0.6 mm) QFN
(no E-Pad)
CY8C20246A-24LKXI
16 K
2K
1
13
13
Yes
No
Yes
16-pin (3 × 3 × 0.6 mm) QFN
(no E-Pad)
CY8C20246AS-24LKXI
16 K
2K
1
13
13
Yes
No
Yes
16-pin (3 × 3 × 0.6 mm) QFN
(no E-Pad) (Tape and Reel)
CY8C20246A-24LKXIT
16 K
2K
1
13
13
Yes
No
Yes
16-pin (3 × 3 × 0.6 mm) QFN
(no E-Pad) (Tape and Reel)
CY8C20246AS-24LKXIT
16 K
2K
1
13
13
Yes
No
Yes
24-pin (4 × 4 × 0.6 mm) QFN
CY8C20336A-24LQXI
8K
1K
1
20
20
Yes
No
Yes
24-pin (4 × 4 × 0.6 mm) QFN
(Tape and Reel)
CY8C20336A-24LQXIT
8K
1K
1
20
20
Yes
No
Yes
24-pin (4 × 4 × 0.6 mm) QFN
CY8C20346A-24LQXI
16 K
2K
1
20
20
Yes
No
Yes
24-pin (4 × 4 × 0.6 mm) QFN
CY8C20346AS-24LQXI
16 K
2K
1
20
20
Yes
No
Yes
24-pin (4 × 4 × 0.6 mm) QFN
(Tape and Reel)
CY8C20346A-24LQXIT
16 K
2K
1
20
20
Yes
No
Yes
24-pin (4 × 4 × 0.6 mm) QFN
(Tape and Reel)
CY8C20346AS-24LQXIT
16 K
2K
1
20
20
Yes
No
Yes
24-pin (4 × 4 × 0.6 mm) QFN
CY8C20396A-24LQXI
16 K
2K
1
19
19
Yes
Yes Yes
24-pin (4 × 4 × 0.6 mm) QFN
(Tape and Reel)
CY8C20396A-24LQXIT
16 K
2K
1
19
19
Yes
Yes Yes
32-pin (5 × 5 × 0.6 mm) QFN
CY8C20436A-24LQXI
8K
1K
1
28
28
Yes
No
Yes
32-pin (5 × 5 × 0.6 mm) QFN
(Tape and Reel)
CY8C20436A-24LQXIT
8K
1K
1
28
28
Yes
No
Yes
32-pin (5 × 5 × 0.6 mm) QFN
CY8C20446A-24LQXI
16 K
2K
1
28
28
Yes
No
Yes
32-pin (5 × 5 × 0.6 mm) QFN
CY8C20446AS-24LQXI
16 K
2K
1
28
28
Yes
No
Yes
32-pin (5 × 5 × 0.6 mm) QFN
(Tape and Reel)
CY8C20446A-24LQXIT
16 K
2K
1
28
28
Yes
No
Yes
32-pin (5 × 5 × 0.6 mm) QFN
(Tape and Reel)
CY8C20446AS-24LQXIT
16 K
2K
1
28
28
Yes
No
Yes
32-pin (5 × 5 × 0.6 mm) QFN
CY8C20466A-24LQXI
32 K
2K
1
28
28
Yes
No
Yes
32-pin (5 × 5 × 0.6 mm) QFN
CY8C20466AS-24LQXI
32 K
2K
1
28
28
Yes
No
Yes
32-pin (5 × 5 × 0.6 mm) QFN
(Tape and Reel)
CY8C20466A-24LQXIT
32 K
2K
1
28
28
Yes
No
Yes
32-pin (5 × 5 × 0.6 mm) QFN
(Tape and Reel)
CY8C20466AS-24LQXIT
32 K
2K
1
28
28
Yes
No
Yes
32-pin (5 × 5 × 0.6 mm) QFN
CY8C20496A-24LQXI
16 K
2K
1
25
25
Yes
Yes Yes
32-pin (5 × 5 × 0.6 mm) QFN
(Tape and Reel)
CY8C20496A-24LQXIT
16 K
2K
1
25
25
Yes
Yes Yes
Document Number: 001-54459 Rev. *O
Page 40 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Table 41. PSoC Device Key Features and Ordering Information (continued)
Package
48-pin SSOP [54]
CY8C20536A-24PVXI [54]
48-pin SSOP (Tape and Reel) [54]
48-pin SSOP
[54]
[54]
[54]
CY8C20536A-24PVXIT
CY8C20546A-24PVXI
48-pin SSOP (Tape and Reel) [54]
48-pin SSOP
Flash SRAM CapSense Digital
Analog XRES USB ADC
(Bytes) (Bytes) Blocks I/O Pins Inputs [53] Pin
Ordering Code
[54]
[54]
CY8C20546A-24PVXIT
CY8C20566A-24PVXI
[54]
[54]
8K
1K
1
34
34
Yes
No
Yes
8K
1K
1
34
34
Yes
No
Yes
16 K
2K
1
34
34
Yes
No
Yes
16 K
2K
1
34
34
Yes
No
Yes
32 K
2K
1
34
34
Yes
No
Yes
32 K
2K
1
34
34
Yes
No
Yes
48-pin SSOP (Tape and Reel) [54]
CY8C20566A-24PVXIT
48-pin (6 × 6 × 0.6 mm) QFN
CY8C20636A-24LQXI
8K
1K
1
36
36
Yes
No
Yes
48-pin (6 × 6 × 0.6 mm) QFN
(Tape and Reel)
CY8C20636A-24LQXIT
8K
1K
1
36
36
Yes
No
Yes
8K
1K
1
36
36
Yes
No
Yes
8K
1K
1
36
36
Yes
No
Yes
48-pin (7 × 7 × 1.0 mm) QFN [54] CY8C20636A-24LTXI [54]
[54]
48-pin (7 × 7 × 1.0 mm) QFN
(Tape and Reel) [54]
CY8C20636A-24LTXIT
48-pin (6 × 6 × 0.6 mm) QFN
CY8C20646A-24LQXI
16 K
2K
1
36
36
Yes
Yes Yes
48-pin (6 × 6 × 0.6 mm) QFN
(Tape and Reel)
CY8C20646A-24LQXIT
16 K
2K
1
36
36
Yes
Yes Yes
16 K
2K
1
36
36
Yes
Yes Yes
16 K
2K
1
36
36
Yes
Yes Yes
48-pin (7 × 7 × 1.0 mm) QFN [54] CY8C20646A-24LTXI [54]
[54]
48-pin (7 × 7 × 1.0 mm) QFN
(Tape and Reel) [54]
CY8C20646A-24LTXIT
48-pin (6 × 6 × 0.6 mm) QFN
CY8C20666A-24LQXI
32 K
2K
1
36
36
Yes
Yes Yes
48-pin (6 × 6 × 0.6 mm) QFN
(Tape and Reel)
CY8C20666A-24LQXIT
32 K
2K
1
36
36
Yes
Yes Yes
48-pin (7 × 7 × 1.0 mm) QFN [54] CY8C20666A-24LTXI [54]
32 K
2K
1
36
36
Yes
Yes Yes
CY8C20666AS-24LTXI
[54]
32 K
2K
1
36
36
Yes
Yes Yes
48-pin (7 × 7 × 1.0 mm) QFN
(Tape and Reel) [54]
CY8C20666A-24LTXIT
[54]
32 K
2K
1
36
36
Yes
Yes Yes
48-pin (7 × 7 × 1.0 mm) QFN
(Tape and Reel) [54]
CY8C20666AS-24LTXIT [54]
32 K
2K
1
36
36
Yes
Yes Yes
48-pin (7 × 7 × 1.0 mm) QFN
(OCD) [53]
CY8C20066A-24LTXI [53]
32 K
2K
1
36
36
Yes
Yes Yes
30-ball WLCSP
CY8C20746A-24FDXC
16 K
1K
1
27
27
Yes
No
Yes
30-ball WLCSP (Tape and Reel) CY8C20746A-24FDXCT
16 K
1K
1
27
27
Yes
No
Yes
30-ball WLCSP
32 K
2K
1
27
27
Yes
No
Yes
30-ball WLCSP (Tape and Reel) CY8C20766A-24FDXCT
32 K
2K
1
27
27
Yes
No
Yes
24-pin (4 × 4 × 0.6 mm) QFN
CY8C20336AN-24LQXI
8K
1K
1
20
20
Yes
No
No
24-pin (4 × 4 × 0.6 mm) QFN
(Tape and Reel)
CY8C20336AN-24LQXIT
8K
1K
1
20
20
Yes
No
No
32-pin (5 × 5 × 0.6 mm) QFN
CY8C20436AN-24LQXI
8K
1K
1
28
28
Yes
No
No
32-pin (5 × 5 × 0.6 mm) QFN
(Tape and Reel)
CY8C20436AN-24LQXIT
8K
1K
1
28
28
Yes
No
No
8K
1K
1
36
36
Yes
No
No
8K
1K
1
36
36
Yes
No
No
48-pin (7 × 7 × 1.0 mm) QFN
[54]
CY8C20766A-24FDXC
48-pin (7 × 7 × 1.0 mm) QFN [54] CY8C20636AN-24LTXI [54]
48-pin (7 × 7 × 1.0 mm) QFN
(Tape and Reel) [54]
CY8C20636AN-24LTXIT
Document Number: 001-54459 Rev. *O
[54]
Page 41 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Table 41. PSoC Device Key Features and Ordering Information (continued)
Package
Flash SRAM CapSense Digital
Analog XRES USB ADC
(Bytes) (Bytes) Blocks I/O Pins Inputs [53] Pin
Ordering Code
16-pin (3 × 3 × 0.6 mm) QFN
(no E-Pad)
CY8C20246AS-24LKXI
16 K
2K
1
13
13
Yes
No
Yes
16-pin (3 × 3 × 0.6 mm) QFN
(no E-Pad, Tape and Reel)
CY8C20246AS-24LKXIT
16 K
2K
1
13
13
Yes
No
Yes
24-pin (4 × 4 × 0.6 mm) QFN
CY8C20346AS-24LQXI
16 K
2K
1
20
20
Yes
No
Yes
24-pin (4 × 4 × 0.6 mm) QFN
(Tape and Reel)
CY8C20346AS-24LQXIT
16 K
2K
1
20
20
Yes
No
Yes
32-pin (5 × 5 × 0.6 mm) QFN
CY8C20446AS-24LQXI
16 K
2K
1
28
28
Yes
No
Yes
32-pin (5 × 5 × 0.6 mm) QFN
(Tape and Reel)
CY8C20446AS-24LQXIT
16 K
2K
1
28
28
Yes
No
Yes
32-pin (5 × 5 × 0.6 mm) QFN
CY8C20466AS-24LQXI
32 K
2K
1
28
28
Yes
No
Yes
32-pin (5 × 5 × 0.6 mm) QFN
(Tape and Reel)
CY8C20466AS-24LQXIT
32 K
2K
1
28
28
Yes
No
Yes
48-pin (6 × 6 × 0.6 mm) QFN
CY8C20666AS-24LQXI
32 K
2K
1
36
36
Yes
Yes Yes
48-pin (6 × 6 × 0.6 mm) QFN
(Tape and Reel)
CY8C20666AS-24LQXIT
32 K
2K
1
36
36
Yes
Yes Yes
48-pin (7 × 7 × 1.0 mm) QFN [54] CY8C20666AS-24LTXI [54]
32 K
2K
1
36
36
Yes
Yes Yes
48-pin (7 × 7 × 1.0 mm) QFN
(Tape and Reel) [54]
CY8C20666AS-24LTXIT [54]
32 K
2K
1
36
36
Yes
Yes Yes
48-pin (6 × 6 × 0.6 mm) QFN
CY8C20646AS-24LQXI
16 K
2K
1
36
36
Yes
Yes Yes
48-pin (6 × 6 × 0.6 mm) QFN
(Tape and Reel)
CY8C20646AS-24LQXIT
16 K
2K
1
36
36
Yes
Yes Yes
16 K
2K
1
36
36
Yes
Yes Yes
16 K
2K
1
36
36
Yes
Yes Yes
48-pin (7 × 7 × 1.0 mm) QFN [54] CY8C20646AS-24LTXI [54]
48-pin (7 × 7 × 1.0 mm) QFN
(Tape and Reel) [54]
CY8C20646AS-24LTXIT
[54]
Ordering Code Definitions
CY
8
C
20 XX6AX - 24
XX
X
X
T
Tape and Reel
Temperature range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: XX = LK or LQ or PV or LT or FD
LK = 16-pin QFN (no E-Pad)
LQ = 24-pin QFN, 32-pin QFN, 48-pin (6 × 6 × 0.6 mm) QFN
PV = 48-pin SSOP
LT = 48-pin (7 × 7 × 1.0 mm) QFN
FD = 30-ball WLCSP
Speed Grade: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
Notes
53. Dual-function Digital I/O Pins also connect to the common analog mux.
54. Not Recommended for New Designs.
Document Number: 001-54459 Rev. *O
Page 42 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Acronyms
Reference Documents
Table 42. Acronyms Used in this Document
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CMOS
complementary metal oxide semiconductor
CPU
central processing unit
DAC
digital-to-analog converter
DC
direct current
EOP
end of packet
FSR
full scale range
GPIO
general purpose input/output
GUI
graphical user interface
I 2C
inter-integrated circuit
ICE
in-circuit emulator
IDAC
digital analog converter current
ILO
internal low speed oscillator
IMO
internal main oscillator
I/O
input/output
ISSP
in-system serial programming
LCD
liquid crystal display
LDO
low dropout (regulator)
LSB
least-significant bit
LVD
low voltage detect
MCU
micro-controller unit
MIPS
mega instructions per second
MISO
master in slave out
MOSI
master out slave in
MSB
most-significant bit
OCD
on-chip debugger
POR
power on reset
PPOR
precision power on reset
PSRR
power supply rejection ratio
PWRSYS power system
PSoC®
Programmable System-on-Chip
SLIMO
slow internal main oscillator
SRAM
static random access memory
SNR
signal to noise ratio
QFN
quad flat no-lead
SCL
serial I2C clock
SDA
serial I2C data
SDATA
serial ISSP data
SPI
serial peripheral interface
SS
slave select
SSOP
shrink small outline package
TC
test controller
USB
universal serial bus
USB D+
USB Data+
USB D–
USB Data–
WLCSP
wafer level chip scale package
XTAL
crystal
■
Technical reference manual for CY8C20xx6 devices
■
In-system Serial Programming (ISSP) protocol for 20xx6
(AN2026C)
■
Host Sourced Serial Programming for 20xx6 devices
(AN59389)
Document Number: 001-54459 Rev. *O
Document Conventions
Units of Measure
Table 43. Units of Measure
Symbol
°C
dB
fF
g
Hz
KB
Kbit
KHz
Ksps
k
MHz
M
A
F
H
s
W
mA
ms
mV
nA
nF
ns
nV
W
pA
pF
pp
ppm
ps
sps
s
V
W
Unit of Measure
degree Celsius
decibels
femtofarad
gram
hertz
1024 bytes
1024 bits
kilohertz
kilo samples per second
kilohm
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microwatt
milliampere
millisecond
millivolt
nanoampere
nanofarad
nanosecond
nanovolt
ohm
picoampere
picofarad
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volt
watt
Page 43 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Numeric Naming
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.
Glossary
Crosspoint connection
Connection between any GPIO combination via analog multiplexer bus.
Differential non-linearity
Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly
one LSB apart. Differential non-linearity is a measure of the worst case deviation from the
ideal 1 LSB step.
Hold time
Hold time is the time following a clock event during which the data input to a latch or flip-flop
must remain stable in order to guarantee that the latched data is correct.
I2C
It is a serial multi-master bus used to connect low speed peripherals to MCU.
Integral nonlinearity
It is a term describing the maximum deviation between the ideal output of a DAC/ADC and
the actual output level.
Latch-up current
Current at which the latch-up test is conducted according to JESD78 standard (at 125
degree Celsius)
Power supply rejection ratio (PSRR)
The PSRR is defined as the ratio of the change in supply voltage to the corresponding
change in output voltage of the device.
Scan
The conversion of all sensor capacitances to digital values.
Setup time
Period required to prepare a device, machine, process, or system for it to be ready to
function.
Signal-to-noise ratio
The ratio between a capacitive finger signal and system noise.
SPI
Serial peripheral interface is a synchronous serial data link standard.
Document Number: 001-54459 Rev. *O
Page 44 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Document History Page
Document Title: CY8C20X36A/46A/66A/96A/46AS/66AS, 1.8 V CapSense® Controller with SmartSense™ Auto-tuning
Document Number: 001-54459
Rev.
ECN
Orig. of
Change
Submission
Date
Description of Change
**
2737924
SNV
07/14/09
*A
2764528
MATT
09/16/2009
*B
2803229
VZD
11/10/09
*C
2846083
DST /
KEJO
01/12/2010
Updated AC Programming Specifications on page 30 per CDT 56531.
Updated Idd typical values in DC Chip-Level Specifications on page 20.
Added 30-pin WLCSP pin and package details.
Added Contents on page 2.
*D
2935141
KEJO /
ISW /
SSHH
03/05/2010
Updated Features on page 1. Added SmartSense on page 4.
Updated PSoC® Functional Overview on page 4.
Removed SNR statement regarding on page 4 (Analog Multiplexer section).
Updated on page 7 with the I2C enhanced slave interface point.
Removed references to “system level” in Designing with PSoC Designer on
page 8.
Changed TC CLK and TC DATA to ISSP CLK and ISSP DATA respectively in
all the pinouts.
Modified notes in Pinouts.
Updated 30-ball pin diagram.
Removed IMO frequency trim options diagram in Electrical Specifications on
page 19.
Updated and formatted values in DC and AC specifications.
Updated Ordering information table.
Updated 48-pin SSOP package diagram. Added 30-Ball WLCSP package spec
001-50669.
Removed AC Analog Mux Bus Specifications section.
Added SPI Master and Slave mode diagrams.
Modified Definition for Timing for Fast/Standard Mode on the I2C Bus on page
28.
Updated Thermal Impedances on page 37.
Combined Development Tools with Development Tool Selection on page 38.
Removed references to “system level”.
Updated Evaluation Tools on page 38.
Added Ordering Code Definitions on page 42.
Updated Acronyms on page 43.
Added Glossary and Reference Documents on page 43.
Changed datasheet status from Preliminary to Final
*E
3043291
SAAC
09/30/10
Change: Added the line “Supports SmartSense” in the “Low power CapSense®
block” bullet in the Features section.
Impact: Helps to know that this part has the feature of Auto Tuning.
Change: Replaced pod MPNs.
Areas affected: Foot kit column of table 37.
Change: Template and Styles update.
Areas affected: Entire datasheet.
Impact: Datasheet adheres to Cypress standards.
*F
3071632
JPX
10/26/10
In Table 36 on page 33, modified tLOW and tHIGH min values to 42. Updated
tSS_HIGH min value to 50; removed max value.
Document Number: 001-54459 Rev. *O
New silicon and document
Updated AC Chip Level Specifications
Updated ADC User Module Electrical Specifications table
Added Note 5.
Added SRPOWER_UP parameter.
Updated Ordering information.
Updated Capacitance on Crystal Pins
Added Contents on page 3. Added Note 6 on page 20. Edited Features section
to include reference to Incremental ADC.
Page 45 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Document History Page (continued)
Document Title: CY8C20X36A/46A/66A/96A/46AS/66AS, 1.8 V CapSense® Controller with SmartSense™ Auto-tuning
Document Number: 001-54459
Rev.
ECN
Orig. of
Change
Submission
Date
Description of Change
*G
3247491
TTO / JPM /
ARVM / BVI
06/16/11
Add 4 new parameters to Table 14 on page 21, and 2 new parameters to Table
15 on page 22.
Changed Typ values for the following parameters: IDD24, IDD12, IDD6, VOSLPC.
Added footnote # 31 and referred it to pin numbers 1, 14, 15, 42, and 43 under
Table 10 on page 18.
Added footnote # 34 and referred it to parameter VIOZ under Table 11 on page
19.
Added “tJIT_IMO” parameter to Table 27 on page 27.
Included footnote # 44 and added reference to tJIT_IMO specification under
Table 27 on page 27.
Updated Solder Reflow Specifications on page 37 as per specs 25-00090 and
25-00103.
ISB0 Max value changed from 0.5 µA to 1.1 µA in Table 13 on page 20.
Added Table 26 on page 26.
Updated part numbers for “SmartSense_EMC” enabled CapSense controller.
*H
3367332
BTK /
SSHH /
JPM / TTO /
VMAD
09/09/11
Added parameter “tOS” to Table 27 on page 27.
Added parameter “ISBI2C” to Table 13 on page 20.
Added Table 24 on page 26.
Added Table 25 on page 26.
Replaced text “Port 2 or 3 pins” with “Port 2 or 3 or 4 pins” in Table 14, Table 15,
Table 16, and Table 28.
*I
3371807
MATT
09/30/2011
Updated Packaging Information (Updated the next revision package outline for
Figure 20, Figure 23 and included a new package outline Figure 25).
Updated Ordering Information (Added new part numbers
CY8C20636A-24LQXI, CY8C20636A-24LQXIT, CY8C20646A-24LQXI,
CY8C20646A-24LQXIT, CY8C20666A-24LQXI, CY8C20666A-24LQXIT,
CY8C20666AS-24LQXI, CY8C20666AS-24LQXIT, CY8C20646AS-24LQXI
and CY8C20646AS-24LQXIT).
Updated in new template.
*J
3401666
MATT
10/11/2011
No technical updates.
*K
3414479
KPOL
10/19/2011
Removed clock stretching feature on page 1.
Removed I2C enhanced slave interface point from Additional System
Resources.
*L
3452591
BVI /
UDYG
12/01/2011
Changed document title.
Updated DC Chip-Level Specifications table.
Updated Solder Reflow Specifications section.
Updated Getting Started and Designing with PSoC Designer sections.
Included Development Tools section.
Updated Software under Development Tool Selection section.
*M
3473330
ANBA
12/22/2011
Updated DC Chip-Level Specifications under Electrical Specifications
(updated maximum value of ISB0 parameter from 1.1 µA to 1.05 µA).
*N
3587003
DST
04/16/2012
Added note for WLCSP package on page 1.
Added Sensing inputs to pin table captions.
Updated Conditions for DC Reference Buffer Specifications.
Updated tJIT_IMO description in AC Chip-Level Specifications.
Added note for tVDDWAIT, tVDDXRES, tACQ, and tXRESINI specs.
Removed WLCSP package outline.
*O
3638569
BVI
06/06/2012
Updated FSCLK parameter in the Table 36, “SPI Slave AC Specifications,” on
page 33.
Changed tOUT_HIGH to tOUT_H in Table 35, “SPI Master AC Specifications,” on
page 32.
Updated package diagram 001-57280 to *C revision.
Document Number: 001-54459 Rev. *O
Page 46 of 47
CY8C20X36A/46A/66A/96A/46AS/66AS
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
Optical & Image Sensing
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
cypress.com/go/USB
Wireless/RF
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2009-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-54459 Rev. *O
®
Revised June 15, 2012
®
Page 47 of 47
PSoC Designer™ is a trademark and PSoC and CapSense are registered trademarks of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
All products and company names mentioned in this document may be the trademarks of their respective holders.
Similar pages