ICSI IC61SP12836-166TQ 128k x 32 pipelined syncburst sram Datasheet

IC61SP12832
IC61SP12836
Document Title
128K x 32 Pipelined SyncBurst SRAM
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
September 17,2001
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
SSR019-0A 09/17/2001
1
IC61SP12832
IC61SP12836
128K x 32, 128K x 36 SYNCHRONOUS
PIPELINED STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• 100-Pin TQFP (JEDEC LQFP) and
119-pin PBGA package
• Single +3.3V, +10%, –5% power supply
• Power-down snooze mode
DESCRIPTION
The ICSI IC61SP12832,IC61SP12836 are high-speed, lowpower synchronous static RAM designed to provide a burstable,
high-performance, secondary cache for the Pentium™, 680X0™,
and PowerPC™ microprocessors. It is organized as 131,072
words by 32 bits, fabricated with ICSI's advanced CMOS
technology. The device integrates a 2-bit burst counter, highspeed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQa, BW2 controls DQb, BW3 controls DQc,
BW4 controls DQd, conditioned by BWE being LOW. A LOW
on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IC61SP12832,IC61SP12836 and controlled by the ADV
(burst address advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frenquency
-166
3.5
6
166
-150
3.8
6.7
150
-133
4
7.5
133
-117
4
8.5
117
-5
5
10
100
Units
ns
ns
MHz
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
SSR019-0A 09/17/2001
IC61SP12832
IC61SP12836
BLOCK DIAGRAM
MODE
Q0
CLK
CLK
A0’
A0
BINARY
COUNTER
ADSC
ADSP
A16-A0
Q1
CE
ADV
A1’
A1
128K x 32, 128K x 36
MEMORY
ARRAY
CLR
17
D
Q
15
17
ADDRESS
REGISTER
CE
CLK
32
GW
BWE
BW4
D
32
Q
DQd
BYTE WRITE
REGISTERS
CLK
BW3
D
DQc Q
BYTE WRITE
REGISTERS
CLK
D
BW2
Q
DQb
BYTE WRITE
REGISTERS
CLK
BW1
D
DQa Q
BYTE WRITE
REGISTERS
CLK
CE
4
Q
CE2
D
CE2
ENABLE
REGISTER
INPUT
REGISTERS
CLK
32
OUTPUT
REGISTERS
CLK
DQ[31:0]
OE
CE
CLK
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
Integrated Circuit Solution Inc.
SSR019-0A 09/17/2001
3
IC61SP12832
IC61SP12836
PIN CONFIGURATION
1
2
3
4
5
6
7
VCCQ
A6
A4
ADSP
A8
A16
VCCQ
NC
CE2
A3
ADSC
A9
CE2
NC
NC
A7
A2
VCC
A12
A15
NC
DQc1
NC
GND
NC
GND
NC
DQb8
DQc2
DQc3
GND
CE
GND
DQb6
DQb7
VCCQ
DQc4
GND
OE
GND
DQb5
VCCQ
DQc5
DQc6
BW3
ADV
BW2
DQb4
DQb3
DQc7
DQc8
GND
GW
GND
DQb2
DQb1
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
DQd1
DQd2
GND
CLK
GND
DQa7
DQa8
DQd4
DQd3
BW4
NC
BW1
DQa5
DQa6
VCCQ
DQd5
GND
BWE
GND
DQa4
VCCQ
DQd6
DQd7
GND
A1
GND
DQa3
DQa2
DQd8
NC
GND
A0
GND
NC
DQa1
NC
A5
MODE
VCC
NC
A13
NC
NC
NC
A10
A11
A14
NC
ZZ
VCCQ
NC
NC
NC
NC
NC
VCCQ
A6
A7
CE
CE2
BW4
BW3
BW2
BW1
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
119-pin PBGA (Top View) and 100-Pin LQFP
A
NC
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
NC
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCC
DQa2
DQa1
NC
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
U
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
128K x 32
PIN DESCRIPTIONS
A0, A1
4
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A16
Synchronous Address Inputs
CLK
Synchronous Clock
ADSP
Synchronous Processor Address
Status
GW
Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
VCC
+3.3V Power Supply
GND
Ground
VCCQ
Isolated Output Buffer Supply:
+3.3V
ADSC
Synchronous Controller Address
Status
ADV
Synchronous Burst Address Advance
BW1-BW4
Synchronous Byte Write Enable
ZZ
Snooze Enable
BWE
Synchronous Byte Write Enable
GNDQ
Isolated Output Buffer Ground
Integrated Circuit Solution Inc.
SSR019-0A 09/17/2001
IC61SP12832
IC61SP12836
PIN CONFIGURATION
1
2
3
4
5
6
7
VCCQ
A6
A4
ADSP
A8
A16
VCCQ
NC
CE2
A3
ADSC
A9
CE2
NC
NC
A7
A2
VCC
A12
A15
NC
DQc1
NC
GND
NC
GND
NC
DQb8
DQc2
DQc3
GND
CE
GND
DQb6
DQb7
VCCQ
DQc4
GND
OE
GND
DQb5
VCCQ
DQc5
DQc6
BW3
ADV
BW2
DQb4
DQb3
DQc7
DQc8
GND
GW
GND
DQb2
DQb1
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
DQd1
DQd2
GND
CLK
GND
DQa7
DQa8
DQd4
DQd3
BW4
NC
BW1
DQa5
DQa6
VCCQ
DQd5
GND
BWE
GND
DQa4
VCCQ
DQd6
DQd7
GND
A1
GND
DQa3
DQa2
DQd8
NC
GND
A0
GND
NC
DQa1
NC
A5
MODE
VCC
NC
A13
NC
NC
NC
A10
A11
A14
NC
ZZ
VCCQ
NC
NC
NC
NC
NC
VCCQ
A6
A7
CE
CE2
BW4
BW3
BW2
BW1
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
119-pin PBGA (Top View) and 100-Pin LQFP
A
DQPc
DQc1
DQc2
VCCQ
GND
DQc3
DQc4
DQc5
DQc6
GND
VCCQ
DQc7
DQc8
NC
VCC
NC
GND
DQd1
DQd2
VCCQ
GND
DQd3
DQd4
DQd5
DQd6
GND
VCCQ
DQd7
DQd8
DQPd
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCC
DQa2
DQa1
DQPa
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
U
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
128K x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A16
Synchronous Address Inputs
CLK
Synchronous Clock
ADSP
Synchronous Processor Address
Status
GW
Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
VCC
+3.3V Power Supply
ADSC
Synchronous Controller Address
Status
GND
Ground
VCCQ
Isolated Output Buffer Supply: +3.3V
ADV
Synchronous Burst Address Advance
ZZ
Snooze Enable
BW1-BW4
Synchronous Byte Write Enable
GNDQ
Isolated Output Buffer Ground
BWE
Synchronous Byte Write Enable
DQPa-DQPd
Parity Data I/O
Integrated Circuit Solution Inc.
SSR019-0A 09/17/2001
5
IC61SP12832
IC61SP12836
TRUTH TABLE
Operation
Address
Used
CE
CE2
CE2
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
None
None
None
None
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
H
L
L
X
X
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
X
X
L
X
0
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
H
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
ADSP ADSC
X
L
L
H
H
L
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
L
L
X
0
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV WRITE
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
X
X
X
Read
Write
Read
Read
Read
Read
Write
Write
Read
Read
Read
Read
Write
Write
OE
DQ
X
X
X
X
X
X
X
X
L
H
L
H
X
X
L
H
L
H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
Q
High-Z
High-Z
High-Z
Q
High-Z
Q
High-Z
High-Z
High-Z
PARTIAL TRUTH TABLE
Function
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
6
GW
BWE
BW1
BW2
H
H
H
H
L
H
L
L
L
X
X
H
L
L
X
X
H
H
L
X
BW3 BW4
X
H
H
L
X
X
H
H
L
X
Integrated Circuit Solution Inc.
SSR019-0A 09/17/2001
IC61SP12832
IC61SP12836
INTERLEAVED BURST ADDRESS TABLE (MODE = VCCQ or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GNDQ)
0,0
A1’, A0’ = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
TBIAS
TSTG
PD
IOUT
VIN, VOUT
VIN
Parameter
Temperature Under Bias
Storage Temperature
Power Dissipation
Output Current (per I/O)
Voltage Relative to GND for I/O Pins
Voltage Relative to GND for
for Address and Control Inputs
VCC
Voltage on Vcc Supply Relatiive to GND
Value
–40 to +85
–55 to +150
1.6
100
–0.5 to VCCQ + 0.3
–0.5 to VCC + 0.5
Unit
°C
°C
W
mA
V
V
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage
higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
Integrated Circuit Solution Inc.
SSR019-0A 09/17/2001
7
IC61SP12832
IC61SP12836
OPERATING RANGE
Range
Commercial
Ambient Temperature
0°C to +70°C
3.3V, +10%, –5%
–40°C to +85°C
3.3V, +10%, –5%
Industrial
VCC
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
IOH = –4.0 mA
2.4
—
V
VOL
Output LOW Voltage
IOL = 8.0 mA
—
0.4
V
VIH
Input HIGH Voltage
2.0
VCCQ + 0.3
V
VIL
Input LOW Voltage
–0.3
0.8
V
ILI
Input Leakage Current
GND ≤ VIN ≤ VCCQ(2)
Com.
Ind.
–2
–5
2
5
µA
ILO
Output Leakage Current
GND ≤ VOUT ≤ VCCQ, OE = VIH Com.
Ind.
–2
–5
2
5
µA
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
-166
Typ. Max.
-150
Typ. Max.
-133
Typ. Max.
-117
Typ. Max
-5
Typ. Max.
Unit
Com.
Ind.
200 230
— —
190 220
200 230
180 210
190 220
175 205
185 215
170 200
180 210
mA
mA
Device Deselected,
VCC = Max.,
All Inputs = VIH or VIL
CLK Cycle Time ≥ tKC min.
Com.
Ind.
45
—
70
—
45
50
70
80
45
50
70
80
45
50
65
75
45
50
65
75
mA
mA
ZZ = VCCQ
Clock Running
All Inputs ≤ GND + 0.2V
or ≥ Vcc – 0.2V
Com.
Ind.
—
—
5
15
—
—
5
15
—
—
5
15
—
—
5
15
—
—
5
15
mA
mA
Symbol Parameter
Test Conditions
ICC
AC Operating
Supply Current
Device Selected,
All Inputs = VIL or VIH
OE = VIH, Vcc = Max.
Cycle Time ≥ tKC min.
ISB
Standby Current
IZZ
Power-down Mode
Current
Notes:
1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to VCCQ.
2. The MODE pin should be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current when tied to ≤ GND + 0.2V
or ≥ Vcc – 0.2V.
8
Integrated Circuit Solution Inc.
SSR019-0A 09/17/2001
IC61SP12832
IC61SP12836
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
5
pF
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
1.5 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
317 Ω
3.3V
ZO = 50Ω
OUTPUT
Output
Buffer
30 pF
50Ω
1.5V
Figure 1
Integrated Circuit Solution Inc.
SSR019-0A 09/17/2001
5 pF
Including
jig and
scope
351 Ω
Figure 2
9
IC61SP12832
IC61SP12836
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166
Symbol Parameter
Min.
Max.
-150
Min. Max.
-133
Min. Max.
-117
Min. Max.
-5
Min.
Max.
Unit
fMAX
Clock Frequency
—
166
—
150
—
133
—
117
—
100
MHz
tKC
Cycle Time
6
—
6.7
—
7.5
—
8.5
—
10
—
ns
tKH
Clock High Time
2.4
—
2.6
—
2.8
—
3.4
—
4
—
ns
tKL
Clock Low Time
2.4
—
2.6
—
2.8
—
3.4
—
4
—
ns
Clock Access Time
—
3.5
—
3.8
—
4
—
4
—
5
ns
Clock High to Output Invalid
1.5
—
1.5
—
1.5
—
1.5
—
2.5
—
ns
tKQLZ(1,2) Clock High to Output Low-Z
0
—
0
—
0
—
0
—
0
—
ns
tKQHZ(1,2) Clock High to Output High-Z
1.5
6
1.5
6.7
1.5
7.5
1.5
8.5
1.5
10
ns
tOEQ
Output Enable to Output Valid
—
3.5
—
3.5
—
3.8
—
4
—
5
ns
Output Disable to Output Invalid
0
—
0
—
0
—
0
—
0
—
ns
tOELZ(1,2) Output Enable to Output Low-Z
0
—
0
—
0
—
0
—
0
—
ns
tOEHZ(1,2) Output Disable to Output High-Z
2
3.5
2
3.5
2
3.8
2
4
2
5
ns
tKQ
tKQX
(1)
(1)
tOEQX
tAS
Address Setup Time
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
tSS
Address Status Setup Time
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
tWS
Write Setup Time
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
tCES
Chip Enable Setup Time
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
tAVS
Address Advance Setup Time
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
tAH
Address Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
tSH
Address Status Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
tWH
Write Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
tCEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
tAVH
Address Advance Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
10
Integrated Circuit Solution Inc.
SSR019-0A 09/17/2001
IC61SP12832
IC61SP12836
READ/WRITE CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
tSS
tSH
ADSC
ADV
tAS
A16-A0
tAH
RD1
WR1
tWS
tWH
tWS
tWH
RD2
RD3
GW
BWE
tWS
tWH
WR1
BW4-BW1
tCES
tCEH
tCES
tCEH
tCES
tCEH
CE Masks ADSP
CE
CE2 and CE2 only sampled with ADSP or ADSC
CE2
Unselected with CE2
CE2
tOEHZ
tOEQ
OE
DATAOUT
High-Z
2a
1a
tKQLZ
tKQ
DATAIN
tKQX
tOEQX
tOELZ
2c
2d
tKQHZ
tKQX
tKQHZ
High-Z
1a
tDS
Single Read
Integrated Circuit Solution Inc.
SSR019-0A 09/17/2001
2b
tDH
Single Write
Burst Read
Unselected
11
IC61SP12832
IC61SP12836
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166
Symbol Parameter
-150
Min. Max.
-133
Min. Max.
-117
Min. Max.
—
6.7
—
7.5
—
8.5
Min.
Max.
6
-5
Min.
Max.
Unit
—
10
—
ns
tKC
Cycle Time
tKH
Clock High Time
2.4
—
2.6
—
2.8
—
3.4
—
4
—
ns
tKL
Clock Low Time
2.4
—
2.6
—
2.8
—
3.4
—
4
—
ns
tAS
Address Setup Time
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
tSS
Address Status Setup Time
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
tWS
Write Setup Time
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
tDS
Data In Setup Time
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
tCES
Chip Enable Setup Time
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
tAVS
Address Advance Setup Time
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
tAH
Address Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
tSH
Address Status Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
tDH
Data In Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
tWH
Write Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
tCEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
tAVH
Address Advance Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
12
Integrated Circuit Solution Inc.
SSR019-0A 09/17/2001
IC61SP12832
IC61SP12836
WRITE CYCLE TIMING
tKC
CLK
tSS
tSH
tKH
tKL
ADSP is blocked by CE inactive
ADSP
ADSC initiate Write
ADSC
ADV must be inactive for ADSP Write tAVS
tAVH
ADV
tAS
A16-A0
tAH
WR1
WR2
tWS
tWH
tWS
tWH
tWS
tWH
WR3
GW
BWE
BW4-BW1
WR1
tCES
tCEH
tCES
tCEH
tCES
tCEH
tWS
tWH
WR2
WR3
CE Masks ADSP
CE
Unselected with CE2
CE2 and CE2 only sampled with ADSP or ADSC
CE2
CE2
OE
DATAOUT
High-Z
tDS
DATAIN
High-Z
Single Write
Integrated Circuit Solution Inc.
SSR019-0A 09/17/2001
tDH
1a
BW4-BW1 only are applied to first cycle of WR2
2a
2b
2c
2d
Burst Write
3a
Write
Unselected
13
IC61SP12832
IC61SP12836
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166
Symbol Parameter
-150
Min. Max.
-133
Min. Max.
-117
Min. Max.
—
6.7
—
7.5
—
8.5
Min.
Max.
6
-5
Min.
Max.
Unit
—
10
—
ns
tKC
Cycle Time
tKH
Clock High Time
2.4
—
2.6
—
2.8
—
3.4
—
4
—
ns
tKL
Clock Low Time
2.4
—
2.6
—
2.8
—
3.4
—
4
—
ns
Clock Access Time
—
3.5
—
3.8
—
4
—
4
—
5
ns
Clock High to Output Invalid
1.5
—
1.5
—
1.5
—
2
—
2.5
—
ns
Clock High to Output Low-Z
0
—
0
—
0
—
0
—
0
—
ns
tKQHZ(1,2) Clock High to Output High-Z
1.5
3.6
1.5
6.7
1.5
7.5
1.5
8.5
1.5
10
ns
tOEQ
tKQ
tKQX
(1)
(1,2)
tKQLZ
Output Enable to Output Valid
—
3.5
—
3.5
—
3.9
—
4
—
5
ns
(1)
Output Disable to Output Invalid
0
—
0
—
0
—
0
—
0
—
ns
(1,2)
Output Enable to Output Low-Z
0
—
0
—
0
—
0
—
0
—
ns
2
3.5
2
3.5
2
3.8
2
4
2
5
ns
tOEQX
tOELZ
tOEHZ(1,2) Output Disable to Output High-Z
tAS
Address Setup Time
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
tSS
Address Status Setup Time
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
tCES
Chip Enable Setup Time
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
tAH
Address Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
tSH
Address Status Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
tCEH
Chip Enable Hold Time
0.5
—
0.5
—
0.5
—
0.5
—
0.5
—
ns
tZZS
ZZ Standby
2
—
2
—
2
—
2
—
2
—
cyc
tZZREC
ZZ Recovery
2
—
2
—
2
—
2
—
2
—
cyc
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
14
Integrated Circuit Solution Inc.
SSR019-0A 09/17/2001
IC61SP12832
IC61SP12836
SNOOZE AND RECOVERY CYCLE TIMING
tKC
CLK
tSS
tSH
tAS
tAH
tKH
tKL
ADSP
ADSC
ADV
A16-A0
RD2
RD1
GW
BWE
BW4-BW1
tCES
tCEH
tCES
tCEH
tCES
tCEH
CE
CE2
CE2
tOEHZ
tOEQ
OE
tOEQX
tOELZ
DATAOUT
High-Z
1a
tKQLZ
tKQ
DATAIN
tKQX
tKQHZ
High-Z
tZZS
tZZREC
ZZ
Single Read
Integrated Circuit Solution Inc.
SSR019-0A 09/17/2001
Snooze with Data Retention
Read
15
IC61SP12832
IC61SP12836
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
Order Part Number
Package
166 MHz
IC61SP12832-166TQ
IC61SP12832-166B
14x20x1.4mm LQFP
14*22mm PBGA
150 MHz
IC61SP12832-150TQ
IC61SP12832-150B
14*20*1.4mm LQFP
14*22mm PBGA
133 MHz
IC61SP12832-133TQ
IC61SP12832-133B
14*20*1.4mm LQFP
14*22mm PBGA
117 MHz
IC61SP12832-117TQ
IC61SP12832-117B
14*20*1.4mm LQFP
14*22mm PBGA
100 MHz
IC61SP12832-5TQ
IC61SP12832-5B
14*20*1.4mm LQFP
14*22mm PBGA
Speed
Order Part Number
Package
166 MHz
IC61SP12836-166TQ
IC61SP12836-166B
14x20x1.4mm LQFP
14*22mm PBGA
150 MHz
IC61SP12836-150TQ
IC61SP12836-150B
14*20*1.4mm LQFP
14*22mm PBGA
133 MHz
IC61SP12836-133TQ
IC61SP12836-133B
14*20*1.4mm LQFP
14*22mm PBGA
117 MHz
IC61SP12836-117TQ
IC61SP12836-117B
14*20*1.4mm LQFP
14*22mm PBGA
100 MHz
IC61SP12836-5TQ
IC61SP12836-5B
14*20*1.4mm LQFP
14*22mm PBGA
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
16
Integrated Circuit Solution Inc.
SSR019-0A 09/17/2001
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