AD AD8230YRZ-REEL7 16 v rail-to-rail, zero-drift, precision instrumentation amplifier Datasheet

16 V Rail-to-Rail, Zero-Drift,
Precision Instrumentation Amplifier
AD8230
2.0
Resistor programmable gain range: 101 to 1000
Supply voltage range: ±4 V to ±8 V, +8 V to +16 V
Rail-to-rail input and output
Maintains performance over −40°C to +125°C
1.5
OFFSET VOLTAGE (µV RTI)
FEATURES
EXCELLENT AC AND DC PERFORMANCE
110 dB minimum CMR @ 60 Hz, G = 10 to 1000
10 µV max offset voltage (RTI, ±5 V)
50 nV/°C max offset drift
20 ppm max gain nonlinearity
1.0
0.5
0
–0.5
–1.0
–2.0
–50
05063-107
–1.5
–30
–10
10
30
50
70
90
110
130
150
TEMPERATURE (°C)
APPLICATIONS
Figure 1. Relative Offset Voltage vs. Temperature
Pressure measurements
Temperature measurements
Strain measurements
Automotive diagnostics
+5V
–5V
0.1µF
0.1µF
2
4
GENERAL DESCRIPTION
Two external resistors are used to program the gain. By using
matched external resistors, the gain stability of the AD8230 is
much higher than instrumentation amplifiers that use a single
resistor to set the gain. In addition to allowing users to program
the gain between 101 and 1000, users may adjust the output
offset voltage.
8
VOUT
7
5
6
3
34.8kΩ
284Ω
05063-002
The AD8230 is a low drift, differential sampling, precision
instrumentation amplifier. Auto-zeroing reduces offset voltage
drift to less than 50 nV/°C. The AD8230 is well-suited for
thermocouple and bridge transducer applications. The
AD8230’s high CMR of 110 dB (min) rejects line noise in
measurements where the sensor is far from the instrumentation.
The 16 V rail-to-rail, common-mode input range is useful for
noisy environments where ground potentials vary by several
volts. Low frequency noise is kept to a minimal 3 µV p-p
making the AD8230 perfect for applications requiring the
utmost dc precision. Moreover, the AD8230 maintains its high
performance over the extended industrial temperature range of
−40°C to +125°C.
1
AD8230
TYPE K THERMOCOUPLE
Figure 2. Thermocouple Measurement
The AD8230 is versatile yet simple to use. Its auto-zeroing
topology significantly minimizes the input and output
transients typical of commutating or chopper instrumentation
amplifiers. The AD8230 operates on ±4 V to ±8 V (+8 V to +16 V)
supplies and is available in an 8-lead SOIC.
1
The AD8230 can be programmed for a gain as low as 2, but the maximum
input voltage is limited to approximately 750 mV.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD8230
TABLE OF CONTENTS
Specifications..................................................................................... 3
Input Voltage Range ................................................................... 11
Absolute Maximum Ratings............................................................ 5
Input Protection ......................................................................... 11
ESD Caution.................................................................................. 5
Power Supply Bypassing ............................................................ 11
Typical Performance Characteristics ............................................. 6
Power Supply Bypassing for Multiple Channel Systems ....... 11
Theory of Operation ...................................................................... 10
Layout .......................................................................................... 12
Setting the Gain .......................................................................... 10
Applications ................................................................................ 12
Level-Shifting the Output.......................................................... 11
Outline Dimensions ....................................................................... 13
Source Impedance and Input Settling Time ........................... 11
Ordering Guide .......................................................................... 13
REVISION HISTORY
10/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD8230
SPECIFICATIONS
VS = ±5 V, VREF = 0 V, RF = 100 kΩ, RG = 1 kΩ (@ TA = 25°C, G = 202, RL = 10 kΩ, unless otherwise noted).
Table 1.
Parameter
VOLTAGE OFFSET
RTI Offset, VOSI
Offset Drift
COMMON-MODE REJECTION (CMR)
CMR to 60 Hz with 1 kΩ Source Imbalance
VOLTAGE OFFSET RTI vs. SUPPLY (PSR)
G=2
G = 202
GAIN
Gain Range
Gain Error
G=2
G = 10
G = 100
G = 1000
Gain Nonlinearity
INPUT
Input Common-Mode Operating Voltage Range
Over Temperature
Input Differential Operating Voltage Range
Average Input Offset Current2
OUTPUT
Output Swing
Over Temperature
Short-Circuit Current
REFERENCE INPUT
Voltage Range
NOISE
Voltage Noise Density, 1 kHz, RTI
Voltage Noise
SLEW RATE
INTERNAL SAMPLE RATE
POWER SUPPLY
Operating Range (Dual Supplies)
Operating Range (Single Supply)
Quiescent Current
TEMPERATURE RANGE
Specified Performance
Conditions
Min
Typ
V+IN = V−IN = 0 V
V+IN = V−IN = 0 V,
TA = −40°C to +125°C
VCM = −5 V to +5 V
Max
Unit
10
50
µV
nV/°C
110
120
dB
120
120
120
140
dB
dB
G = 2(1 + RF/RG)
101
1000
V/V
20
%
%
%
%
ppm
0.01
0.01
0.01
0.02
T = −40°C to +125°C
−VS
−VS
V
V
mV
pA
+VS − 0.2
+VS − 0.2
V
V
mA
+1
V
750
33
VCM = 0V
T = −40°C to +125°C
+VS
+VS
−VS + 0.1
−VS + 0.1
15
−1
VIN+, VIN−, VREF = 0
f = 0.1 Hz to 10 Hz
VIN = 500 mV, G = 10
240
3
2
6
±4
+8
T = −40°C to +125°C
2.7
−40
1
nV/√Hz
µV p-p
V/µs
kHz
±8
+16
3.5
V
V
mA
+125
°C
The AD8230 can operate as low as G = 2. However, since the differential input range is limited to approximately 750 mV, the AD8230 configured at G < 10 does not
make use of the full output voltage range.
2
Differential source resistance less than 10 kΩ does not result in voltage offset due to input bias current or mismatched series resistors.
Rev. 0 | Page 3 of 16
AD8230
VS = ±8 V, VREF = 0 V, RF = 100 kΩ, RG = 1 kΩ (@ TA = 25°C, G = 202, RL = 10 kΩ, unless otherwise noted).
Table 2.
Parameter
VOLTAGE OFFSET
RTI Offset, VOSI
Offset Drift
COMMON-MODE REJECTION (CMR)
CMR to 60 Hz with 1 kΩ Source Imbalance
VOLTAGE OFFSET RTI vs. SUPPLY (PSR)
G=2
G = 202
GAIN
Gain Range
Gain Error
G=2
G = 10
G = 100
G = 1000
Gain Nonlinearity
INPUT
Input Common-Mode Operating Voltage Range
Over Temperature
Input Differential Operating Voltage Range
Average Input Offset Current2
OUTPUT
Output Swing
Over Temperature
Short-Circuit Current
REFERENCE INPUT
Voltage Range
NOISE
Voltage Noise Density, 1 kHz, RTI
Voltage Noise
SLEW RATE
INTERNAL SAMPLE RATE
POWER SUPPLY
Operating Range (Dual Supplies)
Operating Range (Single Supply)
Quiescent Current
TEMPERATURE RANGE
Specified Performance
Conditions
Min
Typ
V+IN = V−IN = 0 V
V+IN = V−IN = 0 V,
T = −40°C to +125°C
VCM = −8 V to +8 V
Max
Unit
20
50
µV
nV/°C
110
120
dB
120
120
120
140
dB
dB
G = 2(1 + RF/RG)
101
1000
V/V
20
%
%
%
%
ppm
0.01
0.01
0.01
0.02
T = −40°C to +125°C
−VS
−VS
V
V
mV
pA
+VS − 0.2
+VS − 0.4
V
V
mA
+1
V
750
33
VCM = 0V
T = −40°C to +125°C
+VS
+VS
−VS + 0.1
−VS + 0.1
15
−1
VIN+, VIN−, VREF = 0
f = 0.1 Hz to 10 Hz
VIN = 500 mV, G = 10
240
3
2
6
±4
+8
T = −40°C to +125°C
3.2
−40
1
nV/√Hz
µV p-p
V/µs
kHz
±8
+16
4
V
V
mA
+125
°C
The AD8230 can operate as low as G = 2. However, since the differential input range is limited to approximately 750 mV, the AD8230 configured at G < 10 does not
make use of the full output voltage range.
2
Differential source resistance less than 10 kΩ does not result in voltage offset due to input bias current or mismatched series resistors.
Rev. 0 | Page 4 of 16
AD8230
ABSOLUTE MAXIMUM RATINGS
Table 3.
CONNECTION DIAGRAM
Rating
±8 V, +16 V
304 mW
20 mA
±VS
±VS
−65°C to +150°C
−40°C to +125°C
–VS 1
8 VOUT
+VS 2
7 RG
VREF1 3
6 VREF2
5 –IN
+IN 4
AD8230
TOP VIEW
(Not to Scale)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions may affect device reliability.
Specification is for device in free air: SOIC: θJA (4-layer JEDEC
board) = 121°C/W.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
this product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 5 of 16
Figure 3.
05063-001
Parameter
Supply Voltage
Internal Power Dissipation
Output Short-Circuit Current
Input Voltage (Common-Mode)
Differential Input Voltage
Storage Temperature
Operational Temperature Range
AD8230
TYPICAL PERFORMANCE CHARACTERISTICS
20
TOTAL NUMBER OF
SAMPLES = 2839 FROM 3 LOTS
NORMALIZED FOR VCM = 0V
500
OFFSET VOLTAGE (µV RTI)
15
SAMPLES
400
300
200
10
5
0
–5
–10
05063-100
100
–9
–6
–3
0
3
6
05063-007
0
–15
–20
9
–6
–4
OFFSET VOLTAGE (µV RTI)
Figure 4. Offset Voltage (RTI) Distribution at ±5 V, CM = 0 V, TA = +25°C
40
0
2
4
6
Figure 7. Offset Voltage (RTI) vs. Common-Mode Voltage, VS = ±5 V
20
TOTAL NUMBER OF SAMPLES = 300 FROM 3 LOTS
NORMALIZED FOR VCM = 0V
35
15
OFFSET VOLTAGE (µV RTI)
30
25
20
15
10
0
–50
–30
–10
10
30
5
0
–5
–10
–15
05063-108
5
10
–20
–10
50
05063-008
SAMPLES
–2
COMMON-MODE VOLTAGE (V)
–8
–6
OFFSET VOLTAGE DRIFT (nV/°C)
–4
–2
0
2
4
6
8
10
COMMON-MODE VOLTAGE (V)
Figure 5. Offset Voltage (RTI) Drift Distribution
Figure 8. Offset Voltage (RTI) vs. Common-Mode Voltage, VS = ±8 V
0
0
–2
–1
OFFSET VOLTAGE (µV)
VS = ±5V
–6
–8
–10
VS = ±8V
–12
–14
–2
–3
–4
–5
±5V SUPPLY
–6
–16
–30
–10
10
30
50
70
90
110
130
–8
0
150
1
2
3
4
5
6
SOURCE IMPEDANCE (kΩ)
TEMPERATURE (°C)
Figure 6. Offset Voltage (RTI) vs. Temperature
±8V SUPPLY
05063-009
–18
–20
–50
–7
05063-005
OFFSET VOLTAGE (µV RTI)
–4
Figure 9. Offset Voltage (RTI) vs. Source Impedance, 1 µF Across Input Pins
Rev. 0 | Page 6 of 16
AD8230
40
6.8k
NORMALIZED FOR VREF = 0V
6.6k
20
CLOCK FREQUENCY (Hz)
10
0
–10
–20
–40
–1.5
–1.0
–0.5
0
0.5
1.0
±8V
6.2k
6.0k
±5V
5.8k
5.6k
05063-010
–30
6.4k
5.4k
–50
1.5
05063-013
OFFSET VOLTAGE (µV RTI)
30
–30
–10
10
30
50
70
90
130
1.0
CMR WITH NO SOURCE IMBALANCE
120
+85°C
100
90
80
70
CMR WITH 1k SOURCE IMBALANCE
60
05063-011
50
40
10
100
1k
+125°C
0.6
–40°C
0.4
0.2
0
–0.2
–0.4
0°C
–0.6
+25°C
–0.8
–1.0
10k
–6
–4
–2
FREQUENCY (Hz)
128
3.4
126
124
122
±5V SUPPLY
118
±8V SUPPLY
114
110
4
6
6
8
10
±8V
3.3
3.2
3.1
3.0
±5V
2.9
2.8
2.7
2.6
05063-012
112
2
4
05063-018
POSITIVE SUPPLY CURRENT (mA)
3.5
0
2
Figure 14. Average Input Bias Current vs. Common-Mode Voltage
−40°C, +25°C, +85°C, +125°C
130
116
0
COMMON-MODE VOLTAGE (V)
Figure 11. Common-Mode Rejection vs. Frequency
120
05063-020
AVERAGE INPUT BIAS CURRENT (µA)
0.8
110
CMR (dB)
130
Figure 13. Clock Frequency vs. Temperature
Figure 10. Offset Voltage (RTI) vs. Reference Voltage
CMR (dB)
110
TEMPERATURE (°C)
VREF (V)
2.5
–50
12
0
50
100
TEMPERATURE (°C)
SOURCE IMPEDANCE (kΩ)
Figure 15. Supply Current vs. Temperature
Figure 12. Common-Mode Rejection vs.
Source Impedance, 1.1 µF Across Input Pins
Rev. 0 | Page 7 of 16
150
90
80
80
70
70
60
60
50
50
40
30
40
30
20
20
10
10
0
–10
10
100
1k
10k
05063-016
GAIN (dB)
90
05063-014
GAIN (dB)
AD8230
0
–10
10
100k
100
80
80
70
70
60
60
50
50
100k
40
30
40
30
20
20
10
10
0
–10
1k
10k
05063-017
GAIN (dB)
90
05063-015
GAIN (dB)
90
100
10k
Figure 19. Gain vs. Frequency, G = 100
Figure 16. Gain vs. Frequency, G = 2
10
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
0
–10
100k
10
100
FREQUENCY (Hz)
1k
10k
100k
FREQUENCY (Hz)
Figure 17. Gain vs. Frequency, G = 10
Figure 20. Gain vs. Frequency, G = 1000
0.010
40
G = +20
0.008
30
0.006
GAIN ERROR (%)
0.004
10
0
–10
0.002
0
–0.002
–0.004
–20
–40
–5
–4
–3
–2
–1
0
1
2
3
4
05063-036
–0.006
–30
05063-019
NONLINEARITY (ppm)
20
–0.008
–0.010
0
5
5
10
15
SOURCE IMPEDANCE (kΩ)
VOUT (V)
Figure 18. Gain Nonlinearity, G = 20
Figure 21. Gain Error vs. Differential Source Impedance
Rev. 0 | Page 8 of 16
20
AD8230
140
0.30
120
0.25
100
PSR (dB)
0.35
µV/ Hz
0.20
0.15
G = +100
G = +1000
80
G = +10
60
40
0.05
20
05063-024
0.10
0
1
10
100
1k
10k
05063-035
G = +2
0
0.1
100k
1
Figure 25. Negative PSR vs. Frequency, RTI
Figure 22. Voltage Noise Spectral Density
10
3.90
VS = ±8V
3.70
–40°C
3.50
3.30
3.10
2.90
2.70
2.50
2µV/DIV
–50
–30
–10
10
30
50
70
90
+25°C
2
+125°C
+25°C
0
+25°C
–2
+125°C
VS = ±5V
–4
+25°C
–40°C
–6
+125°C
–8
VS = ±8V
0
1s/DIV
110
130
–40°C
2
4
6
8
10
OUTPUT CURRENT (mA)
Figure 26. Output Voltage Swing vs. Output Current,
−40°C, +25°C, +85°C, +125°C
Figure 23. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 100)
160
140
G = +1000
100
G = +100
G = +10
80
G = +2
60
40
05063-034
20
0
0.1
+125°C
VS = ±5V
–10
TEMPERATURE (°C)
120
–40°C
4
05063-109
OUTPUT VOLTAGE SWING (V)
6
05063-102
POSITIVE SUPPLY CURRENT (mA)
8
PSR (dB)
10
FREQUENCY (kHz)
FREQUENCY (Hz)
1
10
FREQUENCY (kHz)
Figure 24. Positive PSR vs. Frequency, RTI
Rev. 0 | Page 9 of 16
12
AD8230
THEORY OF OPERATION
Auto-zeroing is a dynamic offset and drift cancellation technique that reduces input referred voltage offset to the µV level
and voltage offset drift to the nV/°C level. A further advantage
of dynamic offset cancellation is the reduction of low frequency
noise, in particular the 1/f component.
The AD8230 is an instrumentation amplifier that uses an
auto-zeroing topology and combines it with high commonmode signal rejection. The internal signal path consists of an
active differential sample-and-hold stage (preamp) followed by
a differential amplifier (gain amp). Both amplifiers implement
auto-zeroing to minimize offset and drift. A fully differential
topology increases the immunity of the signals to parasitic noise
and temperature effects. Amplifier gain is set by two external
resistors for convenient TC matching.
In Phase B, the differential signal is transferred to the hold
capacitors refreshing the value stored on CHOLD. The output of
the preamplifier is held at a common-mode voltage determined
by the reference potential, VREF. In this manner, the AD8230 is
able to condition the difference signal and set the output voltage
level. The gain amplifier conditions the updated signal stored on
the hold capacitors, CHOLD.
SETTING THE GAIN
Two external resistors set the gain of the AD8230. The gain is
expressed in the following function:
Gain = 2(1 +
RF
)
RG
+VS
–VS
The signal sampling rate is controlled by an on-chip, 6 kHz
oscillator and logic to derive the required nonoverlapping
clock phases. For simplification of the functional description,
two sequential clock phases, A and B, are used to distinguish
the order of internal operation, as depicted in Figure 27 and
Figure 28, respectively.
0.1µF
10µF
0.1µF
4
1
AD8230
VREF2
5
VREF1
GAIN AMP
PREAMP
10µF
2
VOUT
8
RG
7
6
RF
3
RG
CHOLD
V+IN
VDIFF
+VCM
05063-030
–VS
+
–
–
+
VOUT
CSAMPLE
V–IN
Figure 29. Gain Setting
Table 4. Gains Using Standard 1% Resistors
CHOLD
VREF
RG
RF
05063-103
–VS
Figure 27. Phase A of the Sampling Phase
During Phase A, the sampling capacitors are connected to the
inputs. The input signal’s difference voltage, VDIFF, is stored
across the sampling capacitors, CSAMPLE. Since the sampling
capacitors only retain the difference voltage, the common-mode
voltage is rejected. During this period, the gain amplifier is not
connected to the preamplifier so its output remains at the level
set by the previously sampled input signal held on CHOLD, as
shown in Figure 27.
GAIN AMP
PREAMP
Gain
2
10
50
100
200
500
1000
+
–
–
+
VOUT
CSAMPLE
V–IN
CHOLD
RG
Figure 28. Phase B of the Sampling Phase
RF
05063-104
–VS
VREF
Actual Gain
2
10
50.5
99.6
202
501
1002
RL||(RF + RG) > 2 kΩ
CHOLD
V+IN
RG
None
2 kΩ
499 Ω
200 Ω
100 Ω
200 Ω
200 Ω
Figure 29 and Table 4 provide an example of some gain settings.
As Table 4 shows, the AD8230 accepts a wide range of resistor
values. Since the instrumentation amplifier has finite driving
capability, make sure that the output load in parallel with the
sum of the gain setting resistors is greater than 2 kΩ.
–VS
VDIFF
+VCM
RF
0 Ω (short)
8.06 kΩ
12.1 kΩ
9.76 kΩ
10 kΩ
49.9 kΩ
100 kΩ
Offset voltage drift at high temperature can be minimized by
keeping the value of the feedback resistor, RF, small. This is due
to the junction leakage current on the RG pin, Pin 7. The effect
of the gain setting resistor on offset voltage drift is shown in
Figure 30. In addition, experience has shown that wire-wound
resistors in the gain feedback loop may degrade the offset
voltage performance.
Rev. 0 | Page 10 of 16
AD8230
0
INPUT VOLTAGE RANGE
The input common-mode range of the AD8230 is rail to rail.
However, the differential input voltage range is limited to,
approximately, 750 mV. The AD8230 does not phase invert
when its inputs are overdriven.
–2
INPUT PROTECTION
–3
RF = 100kΩ, RG = 1kΩ
–4
–5
–50
0
50
TEMPERATURE (°C)
100
150
05063-110
RF = 10kΩ, RG = 100Ω
The input voltage is limited to within one diode drop beyond
the supply rails by the internal ESD protection diodes. Resistors
and low leakage diodes may be used to limit excessive, external
voltage and current from damaging the inputs, as shown in
Figure 32. Figure 34 shows an overvoltage protection circuit
between the thermocouple and the AD8230.
+VS
Figure 30. Effect of Feedback Resistor on Offset Voltage Drift
LEVEL-SHIFTING THE OUTPUT
0.1µF
A reference voltage, as shown in Figure 31, can be used to levelshift the output 1 V from midsupply. Otherwise, it is nominally
tied to midsupply. The voltage source used to level-shift the
output should have a low output impedance to avoid contributing to gain error. In addition, it should be able to source and
sink current. To minimize offset voltage, the VREF pins should be
connected either to the local ground or to a reference voltage
source that is connected to the local ground.
2
4
2.49kΩ
2.49kΩ
8
VOUT
7
5
6
+VS –VS
BAV199
19.1kΩ
200Ω
Figure 32. Overvoltage Input Protection
–VS
POWER SUPPLY BYPASSING
0.1µF
A regulated dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins may adversely affect
performance. Bypass capacitors should be used to decouple
the amplifier.
0.1µF
2
1
AD8230
8
VOUT
7
5
1
AD8230
3
+VS
4
–VS
BAV199
0.1µF
+VS –VS
05063-037
OFFSET VOLTAGE (µV RTI)
–1
6
3
RF
The AD8230 has internal clocked circuitry that requires
adequate supply bypassing. A 0.1 µF capacitor should be placed
as close to each supply pin as possible. As shown in Figure 29,
a 10 µF tantalum capacitor may be used further away from
the part.
VLEVEL-SHIFT =
(+VS + –VS)
± 1V
2
05063-031
RG
Figure 31. Level-Shifting the Output
SOURCE IMPEDANCE AND INPUT SETTLING TIME
The input stage of the AD8230 consists of two actively driven,
differential switched capacitors, as described in Figure 27 and
Figure 28. Differential input signals are sampled on CSAMPLE such
that the associated parasitic capacitances, 70 pF, are balanced
between the inputs to achieve high common-mode rejection.
On each sample period (approximately 85 µs), these parasitic
capacitances must be recharged to the common-mode voltage
by the signal source impedance (10 kΩ max).
POWER SUPPLY BYPASSING FOR MULTIPLE
CHANNEL SYSTEMS
The best way to prevent clock interference in multichannel
systems is to lay out the PCB with a star node for the positive
supply and a star node for the negative supply. Each AD8230
has a pair of traces leading to the star nodes. Using such a technique, crosstalk between clocks is minimized. If laying out star
nodes is unfeasible, then use thick traces to minimize parasitic
inductance and decouple frequently along the power supply
traces. Examples are shown in Figure 33. Care and forethought
go a long way in maximizing performance.
Rev. 0 | Page 11 of 16
AD8230
–VS
+VS
10µF
1µF
10µF
0.1µF
1
2
0.1µF
1µF
–VS
1
8
+VS
–VS
1
8
+VS
AD8230
0.1µF
3
6
3
4
5
5
5
5
0.1µF
AD8230
AD8230
1
8
+VS
2
4
4
4
–VS
7
6
6
6
1
8
+VS
3
3
3
0.1µF
0.1µF
–VS
2
2
2
1µF
7
7
7
0.1µF
1µF
0.1µF
0.1µF
0.1µF
–VS
8
+VS
7
6
5
4
AD8230
AD8230
STAR –VS
10µF
STAR +VS
10µF
1
1
8
+VS
7
2
3
6
4
5
2
0.1µF
–VS
0.1µF
1
8
+VS
3
6
3
4
5
3
6
4
5
AD8230
1
8
+VS
2
2
0.1µF
–VS
7
7
AD8230
0.1µF
0.1µF
–VS
0.1µF
–VS
8
+VS
7
6
05063-106
0.1µF
0.1µF
5
4
AD8230
AD8230
Figure 33. Use Star Nodes for +VS and −VS or Use Thick Traces and Decouple Frequently Along the Supply Lines
LAYOUT
The AD8230 has two reference pins: VREF1 and VREF2. VREF1
draws current to set the internal voltage references. In
contrast, VREF2 does not draw current. It sets the common
mode of the output signal. As such, VREF1 and VREF2 should
be star-connected to ground (or to a reference voltage). In
addition, to maximize CMR, the trace between VREF2 and the
gain resistor, RG, should be kept short.
thermocouple connection is broken. Well-matched 1% 4.99 kΩ
resistors are used in the RFI filter. It is good practice to match
the source impedances to ensure high CMR. The circuit is
configured for a gain of 193, which provides an overall
temperature sensitivity of 10 mV/°C.
+VS
–VS
0.1µF
0.1µF
+VS
APPLICATIONS
2
4
+VS
350Ω
–VS
1
4
4.99kΩ
4.99kΩ
100MΩ
350Ω
1
AD8230
1µF
6
3
–VS
8
–VS
VOUT
Figure 35. Bridge Measurement with Filtered Output
19.1kΩ
200Ω
+VS –VS
BAV199
102kΩ
7
5
1nF
6
3
VOUT
1µF
1kΩ
2
1nF
TYPE J
THERMOCOUPLE
350Ω
0.1µF
05063-032
100MΩ
0.1µF
8
7
5
+VS
4kΩ
AD8230
350Ω
05063-033
BAV199
+VS –VS
Figure 34. Type J Thermocouple with Overvoltage Protection and RFI Filter
The AD8230 may be used in thermocouple applications, as
shown in Figure 2 and Figure 34. Figure 34 is an example of
such a circuit for use in an industrial environment. It has
voltage overload protection (see the Input Protection section
for more information) and an RFI filter in front. The matched
100 MΩ resistors serve to provide input bias current to the
input transistors and also serve as an indicator as to when the
Measuring load cells in industrial environments can be a
challenge. Often, the load cell is located some distance away
from the instrumentation amplifier. The common-mode
potential can be several volts, exceeding the common-mode
input range of many 5 V auto-zero instrumentation amplifiers.
Fortunately, the AD8230’s wide common-mode input voltage
range spans 16 V, relieving designers of having to worry about
the common-mode range.
Rev. 0 | Page 12 of 16
AD8230
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
5
4.00 (0.1574)
3.80 (0.1497) 1
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
6.20 (0.2440)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
COPLANARITY
SEATING 0.31 (0.0122)
0.10
PLANE
0.50 (0.0196)
× 45°
0.25 (0.0099)
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 36. 8-Lead Standard Small Outline Package [SOIC]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
AD8230YRZ1
AD8230YRZ-REEL1
AD8230YRZ-REEL71
AD8230-EVAL
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead SOIC
8-Lead SOIC, 13" Tape and Reel
8-Lead SOIC, 7" Tape and Reel
Evaluation Board
Z = Pb-free part.
Rev. 0 | Page 13 of 16
Package Option
R-8
R-8
R-8
AD8230
NOTES
Rev. 0 | Page 14 of 16
AD8230
NOTES
Rev. 0 | Page 15 of 16
AD8230
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05063–0–10/04(0)
Rev. 0 | Page 16 of 16
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