Revised February 2005 74VHC08 Quad 2-Input AND Gate General Description Features The VHC08 is an advanced high speed CMOS 2 Input AND Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. ■ High Speed: tPD The internal circuit is composed of 4 stages including buffer output, which provide high noise immunity and stable output. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. ■ Low noise: VOLP 4.3 ns (typ) at TA ■ High noise immunity: VNIH VNIL 25qC 28% VCC (min) ■ Power down protection is provided on all inputs 2 PA (Max) @ TA ■ Low power dissipation: ICC 25qC 0.8V (max) ■ Pin and function compatible with 74HC08 Ordering Code: Order Number Package Package Description Number 74VHC08M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC08MX_NL (Note 1) M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC08SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC08MTCX_NL (Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 74VHC08N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only. Connection Diagram Logic Symbol IEEE/IEC Truth Table Pin Descriptions Pin Names Description A B L L O L L H L An, Bn Inputs H L L On Outputs H H H © 2005 Fairchild Semiconductor Corporation DS011514 www.fairchildsemi.com 74VHC08 Quad 2-Input AND Gate November 1992 74VHC08 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions (Note 3) 0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC 0.5V 20 mA r20 mA r25 mA r50 mA 65qC to 150qC Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT ) DC VCC/GND Current (ICC) Storage Temperature (TSTG) 0V to 5.5V Output Voltage (VOUT) 0V to VCC 40qC to 85qC Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) Lead Temperature (TL) VCC 3.3V r 0.3V 0 ns/V a 100 ns/V VCC 5.0V r 0.5V 0 ns/V a 20 ns/V Note 2: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. 260qC (Soldering, 10 seconds) 2.0V to 5.5V Supply Voltage (VCC) Input Voltage (VIN) Note 3: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VCC (V) Parameter HIGH Level Input Voltage VIL VOH VOL 25qC Typ 40qC to 85qC TA Max Min 2.0 1.50 1.50 3.0 5.5 0.7 VCC 0.7 VCC LOW Level Input Voltage TA Min 2.0 0.50 0.50 0.3 VCC 0.3 VCC 2.0 1.9 2.0 1.9 Output Voltage 3.0 2.9 3.0 2.9 4.5 4.4 4.5 3.0 2.58 2.48 4.5 3.94 3.80 Low Level 2.0 Output Voltage Input Leakage Current ICC Quiescent Supply Current Units Conditions V 3.0 - 5.5 HIGH Level IIN Max V VIN V VIH IOH 4.4 0.0 0.1 IOH V 0.1 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 IOH VIN V VIH IOL 8 mA 50 PA 3.0 0.36 0.44 4.5 0.36 0.44 0 - 5.5 r0.1 r1.0 PA VIN 5.5V or GND 5.5 2.0 20.0 PA VIN VCC or GND Parameter V TA 25qC VCC (V) Typ Limits Units IOL 4 mA IOL 8 mA Conditions VOLP (Note 4) Quiet Output Maximum Dynamic VOL 5.0 0.3 0.8 V CL 50 pF VOLV (Note 4) Quiet Output Minimum Dynamic VOL 5.0 0.3 0.8 V CL 50 pF VIHD (Note 4) Minimum HIGH Level Dynamic Input Voltage 5.0 3.5 V CL 50 pF VILD (Note 4) Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL 50 pF Note 4: Parameter guaranteed by design. www.fairchildsemi.com 4 mA or VIL Noise Characteristics Symbol 50 PA or VIL 2 Symbol tPHL Parameter Propagation Delay VCC (V) 3.3 r 0.3 tPLH 5.0 r 0.5 TA Min 25qC TA 40qC to 85qC Typ Max Min Max 6.2 8.8 1.0 10.5 8.7 12.3 1.0 14.0 4.3 5.9 1.0 7.0 5.8 7.9 1.0 9.0 10 CIN Input Capacitance 4 CPD Power Dissipation Capacitance 18 10 Units ns ns Conditions CL 15 pF CL 50 pF CL 15 pF CL 50 pF pF VCC pF (Note 5) Open Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) CPD * VCC * fIN I CC/4 (per gate). 3 www.fairchildsemi.com 74VHC08 AC Electrical Characteristics 74VHC08 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A www.fairchildsemi.com 4 74VHC08 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com 74VHC08 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 www.fairchildsemi.com 6 74VHC08 Quad 2-Input AND Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com