ON NGD18N40CLB Ignition igbt 18 amps, 400 volt Datasheet

NGD18N40CLB
Ignition IGBT
18 Amps, 400 Volts
N−Channel DPAK
This Logic Level Insulated Gate Bipolar Transistor (IGBT) features
monolithic circuitry integrating ESD and Over−Voltage clamped
protection for use in inductive coil drivers applications. Primary uses
include Ignition, Direct Fuel Injection, or wherever high voltage and
high current switching is required.
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18 AMPS
400 VOLTS
VCE(on) 3 2.0 V @
IC = 10 A, VGE . 4.5 V
Features
•
•
•
•
•
•
•
•
•
•
•
•
Ideal for Coil−on−Plug Applications
DPAK Package Offers Smaller Footprint for Increased Board Space
Gate−Emitter ESD Protection
Temperature Compensated Gate−Collector Voltage Clamp Limits
Stress Applied to Load
Integrated ESD Diode Protection
New Design Increases Unclamped Inductive Switching (UIS) Energy
Per Area
Low Threshold Voltage Interfaces Power Loads to Logic or
Microprocessor Devices
Low Saturation Voltage
High Pulsed Current Capability
Optional Gate Resistor (RG) and Gate−Emitter Resistor (RGE)
Emitter Ballasting for Short−Circuit Capability
Pb−Free Package is Available*
C
RG
G
RGE
E
4
1 2
3
MARKING DIAGRAM
1
Gate
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Collector−Emitter Voltage
VCES
430
VDC
Collector−Gate Voltage
VCER
430
VDC
Gate−Emitter Voltage
VGE
18
VDC
IC
15
50
ADC
AAC
Rating
Collector Current−Continuous
@ TC = 25°C − Pulsed
ESD (Human Body Model)
R = 1500 Ω, C = 100 pF
ESD
ESD (Machine Model) R = 0 Ω, C = 200 pF
ESD
800
V
PD
115
0.77
Watts
W/°C
TJ, Tstg
−55 to
+175
°C
Total Power Dissipation @ TC = 25°C
Derate above 25°C
Operating and Storage Temperature Range
kV
8.0
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
May, 2006 − Rev. 7
DPAK
CASE 369C
STYLE 7
1
2
Collector
YWW
G18
N40BG
4
Collector
3
Emitter
G18N40B
Y
WW
G
= Device Code
= Year
= Work Week
= Pb−Free Device
ORDERING INFORMATION
Device
Package
Shipping†
NGD18N40CLBT4
DPAK
2500/Tape & Reel
NGD18N40CLBT4G
DPAK
2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NGD18N40CLB/D
NGD18N40CLB
UNCLAMPED COLLECTOR−TO−EMITTER AVALANCHE CHARACTERISTICS (−55° ≤ TJ ≤ 175°C)
Characteristic
Symbol
Single Pulse Collector−to−Emitter Avalanche Energy
VCC = 50 V, VGE = 5.0 V, Pk IL = 21.1 A, L = 1.8 mH, Starting TJ = 25°C
VCC = 50 V, VGE = 5.0 V, Pk IL = 16.2 A, L = 3.0 mH, Starting TJ = 25°C
VCC = 50 V, VGE = 5.0 V, Pk IL = 18.3 A, L = 1.8 mH, Starting TJ = 125°C
EAS
Reverse Avalanche Energy
VCC = 100 V, VGE = 20 V, Pk IL = 25.8 A, L = 6.0 mH, Starting TJ = 25°C
EAS(R)
Value
Unit
mJ
400
400
300
mJ
2000
MAXIMUM SHORT−CIRCUIT TIMES (−55°C ≤ TJ ≤ 150°C)
Short Circuit Withstand Time 1 (See Figure 17, 3 Pulses with 10 ms Period)
tsc1
750
ms
Short Circuit Withstand Time 2 (See Figure 18, 3 Pulses with 10 ms Period)
tsc2
5.0
ms
RθJC
1.3
°C/W
RθJA
95
°C/W
TL
275
°C
THERMAL CHARACTERISTICS
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
DPAK (Note 1)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 5 seconds
ELECTRICAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions
Temperature
Min
Typ
Max
Unit
IC = 2.0 mA
TJ = −40°C to
150°C
380
395
420
VDC
IC = 10 mA
TJ = −40°C to
150°C
390
405
430
TJ = 25°C
−
2.0
20
TJ = 150°C
−
10
40*
TJ = −40°C
−
1.0
10
TJ = 25°C
−
−
2.0
TJ = 25°C
−
0.7
1.0
TJ = 150°C
−
12
25*
TJ = −40°C
−
0.1
1.0
TJ = 25°C
27
33
37
TJ = 150°C
30
36
40
TJ = −40°C
25
32
35
IG = 5.0 mA
TJ = −40°C to
150°C
11
13
15
VDC
VGE = 10 V
TJ = −40°C to
150°C
384
640
700
μADC
OFF CHARACTERISTICS
Collector−Emitter Clamp Voltage
Zero Gate Voltage Collector Current
BVCES
ICES
VCE = 350 V,
VGE = 0 V
VCE = 15 V,
VGE = 0 V
Reverse Collector−Emitter Leakage Current
IECS
VCE = −24 V
Reverse Collector−Emitter Clamp Voltage
BVCES(R)
IC = −75 mA
Gate−Emitter Clamp Voltage
Gate−Emitter Leakage Current
BVGES
IGES
μADC
mA
VDC
Gate Resistor
RG
−
TJ = −40°C to
150°C
−
70
−
Ω
Gate Emitter Resistor
RGE
−
TJ = −40°C to
150°C
10
16
26
kΩ
1. When surface mounted to an FR4 board using the minimum recommended pad size.
*Maximum Value of Characteristic across Temperature Range.
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2
NGD18N40CLB
ELECTRICAL CHARACTERISTICS (continued)
Characteristic
Symbol
Test Conditions
Temperature
Min
Typ
Max
Unit
VDC
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage
Threshold Temperature Coefficient
(Negative)
Collector−to−Emitter On−Voltage
VGE(th)
TJ = 25°C
1.1
1.4
1.9
IC = 1.0 mA,
VGE = VCE
TJ = 150°C
0.75
1.0
1.4
TJ = −40°C
1.2
1.6
2.1*
−
−
−
3.4
−
mV/°C
TJ = 25°C
1.0
1.4
1.6
VDC
TJ = 150°C
0.9
1.3
1.6
TJ = −40°C
1.1
1.45
1.7*
TJ = 25°C
1.3
1.6
1.9*
TJ = 150°C
1.2
1.55
1.8
TJ = −40°C
1.4
1.6
1.9*
TJ = 25°C
1.4
1.8
2.05
TJ = 150°C
1.4
1.8
2.0
TJ = −40°C
1.4
1.8
2.1*
TJ = 25°C
1.8
2.2
2.5
TJ = 150°C
2.0
2.4
2.6*
TJ = −40°C
1.7
2.1
2.5
TJ = 25°C
1.3
1.8
2.0*
TJ = 150°C
1.3
1.75
2.0*
TJ = −40°C
1.4
1.8
2.0*
IC = 6.5 A,
VGE = 3.7 V
TJ = 25°C
−
−
1.65
VCE = 5.0 V, IC = 6.0 A
TJ = −40°C to
150°C
8.0
14
25
Mhos
400
800
1000
pF
VCC = 25 V, VGE = 0 V
f = 1.0 MHz
TJ = −40°C to
150°C
50
75
100
4.0
7.0
10
−
VCE(on)
IC = 6.0 A,
VGE = 4.0 V
IC = 8.0 A,
VGE = 4.0 V
IC = 10 A,
VGE = 4.0 V
IC = 15 A,
VGE = 4.0 V
IC = 10 A,
VGE = 4.5 V
Forward Transconductance
gfs
DYNAMIC CHARACTERISTICS
Input Capacitance
CISS
Output Capacitance
COSS
Transfer Capacitance
CRSS
SWITCHING CHARACTERISTICS
Turn−Off Delay Time (Resistive)
td(off)
VCC = 300 V, IC = 6.5 A
RG = 1.0 kΩ, RL = 46 Ω,
TJ = 25°C
−
4.0
10
Fall Time (Resistive)
tf
VCC = 300 V, IC = 6.5 A
RG = 1.0 kΩ, RL = 46 Ω,
TJ = 25°C
−
9.0
15
Turn−On Delay Time
td(on)
VCC = 10 V, IC = 6.5 A
RG = 1.0 kΩ, RL = 1.5 Ω
TJ = 25°C
−
0.7
4.0
tr
VCC = 10 V, IC = 6.5 A
RG = 1.0 kΩ, RL = 1.5 Ω
TJ = 25°C
−
4.5
7.0
Rise Time
2. Pulse Test: Pulse Width v 300 μS, Duty Cycle v 2%.
*Maximum Value of Characteristic across Temperature Range.
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3
μSec
μSec
NGD18N40CLB
TYPICAL ELECTRICAL CHARACTERISTICS (unless otherwise noted)
60
50
5V
4.5 V
40
30
4V
TJ = 25°C
3.5 V
20
3V
10
0
2.5 V
0
1
2
3
4
5
6
7
4.5 V
3.5 V
20
3V
10
2.5 V
1
0
3
2
5
4
6
7
Figure 1. Output Characteristics
Figure 2. Output Characteristics
8
60
VGE = 10 V
5V
40
TJ = 150°C
4.5 V
30
4V
20
3.5 V
3V
10
2.5 V
0
1
2
3
4
5
7
6
55
VCE = 10 V
50
45
40
35
30
TJ = 25°C
25
20
15
10
5
0
8
0
COLLECTOR TO EMITTER VOLTAGE (VOLTS)
IC = 25 A
3.0
IC = 20 A
2.5
IC = 15 A
2.0
IC = 10 A
1.5
IC = 5 A
1.0
0.5
0.0
−50
−25
0
25
50
75
100
2
3
4
5
6
7
8
Figure 4. Transfer Characteristics
4.0
VGE = 5 V
1
VGE, GATE TO EMITTER VOLTAGE (VOLTS)
Figure 3. Output Characteristics
3.5
TJ = 150°C
TJ = −40°C
VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)
VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)
4V
TJ = −40°C
30
VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)
50
0
5V
40
0
8
VGE = 10 V
50
VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)
60
IC, COLLECTOR CURRENT (AMPS)
IC, COLLECTOR CURRENT (AMPS)
VGE = 10 V
IC, COLLECTOR CURRENT (AMPS)
IC, COLLECTOR CURRENT (AMPS)
60
125
150
3
TJ = 25°C
2.5
IC = 15 A
2
IC = 10 A
1.5
IC = 5 A
1
0.5
0
3
TJ, JUNCTION TEMPERATURE (°C)
4
5
6
7
8
9
GATE−TO−EMITTER VOLTAGE (VOLTS)
Figure 5. Collector−to−Emitter Saturation
Voltage versus Junction Temperature
Figure 6. Collector−to−Emitter Voltage versus
Gate−to−Emitter Voltage
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4
10
10000
3
TJ = 150°C
IC = 15 A
2
IC = 10 A
1.5
1000
Ciss
100
Coss
10
Crss
C, CAPACITANCE (pF)
2.5
IC = 5 A
1
0.5
0
4
5
6
7
8
9
10
20
40
60
80
100 120
140 160 180 200
VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)
Figure 7. Collector−to−Emitter Voltage versus
Gate−to−Emitter Voltage
Figure 8. Capacitance Variation
30
2
1.8
VTH + 4 σ
1.6
1.4
0
GATE TO EMITTER VOLTAGE (VOLTS)
VTH
VTH − 4 σ
1.2
1
0.8
0.6
0.4
0.2
0
−50 −30 −10
10
30
50
70
90
VCC = 50 V
VGE = 5.0 V
RG = 1000 Ω
25
L = 1.8 mH
20
15
L = 3 mH
10
L = 6 mH
5
0
−50 −25
110 130 150
0
25
50
75
100
125
150 175
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Gate Threshold Voltage versus
Temperature
Figure 10. Minimum Open Secondary Latch
Current versus Temperature
12
30
VCC = 50 V
VGE = 5.0 V
RG = 1000 Ω
25
L = 1.8 mH
20
10
SWITCHING TIME (μs)
IL, LATCH CURRENT (AMPS)
1
0
3
IL, LATCH CURRENT (AMPS)
GATE THRESHOLD VOLTAGE (VOLTS)
COLLECTOR TO EMITTER VOLTAGE (VOLTS)
NGD18N40CLB
L = 3 mH
15
L = 6 mH
10
8
VCC = 300 V
VGE = 5.0 V
RG = 1000 Ω
IC = 10 A
L = 300 μH
tf
6
td(off)
4
2
5
0
−50 −25
0
25
50
75
100
125
150
0
−50 −30 −10
175
10
30
50
70
90
110 130 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Typical Open Secondary Latch
Current versus Temperature
Figure 12. Inductive Switching Fall Time
versus Temperature
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5
NGD18N40CLB
100
COLLECTOR CURRENT (AMPS)
COLLECTOR CURRENT (AMPS)
100
DC
10
100 μs
1 ms
1
10 ms
100 ms
0.1
0.01
10
100
100 μs
0.1
1000
100 ms
1
1 ms
10 ms
10
100
1000
COLLECTOR−EMITTER VOLTAGE (VOLTS)
COLLECTOR−EMITTER VOLTAGE (VOLTS)
Figure 13. Single Pulse Safe Operating Area
(Mounted on an Infinite Heatsink at TA = 255C)
Figure 14. Single Pulse Safe Operating Area
(Mounted on an Infinite Heatsink at TA = 1255C)
100
100
t1 = 1 ms, D = 0.05
COLLECTOR CURRENT (AMPS)
COLLECTOR CURRENT (AMPS)
1
0.01
1
t1 = 2 ms, D = 0.10
10
t1 = 3 ms, D = 0.30
1
0.1
0.01
10 DC
1
10
100
t1 = 1 ms, D = 0.05
t1 = 3 ms, D = 0.30
1
0.1
0.01
1000
t1 = 2 ms, D = 0.10
10
1
10
100
1000
COLLECTOR−EMITTER VOLTAGE (VOLTS)
COLLECTOR−EMITTER VOLTAGE (VOLTS)
Figure 15. Pulse Train Safe Operating Area
(Mounted on an Infinite Heatsink at TC = 255C)
Figure 16. Pulse Train Safe Operating Area
(Mounted on an Infinite Heatsink at TC = 1255C)
VBATT = 16 V
VBATT = 16 V
RL = 0.1 W
RL = 0.1 W
L = 10 mH
L = 10 mH
5.0 V
5.0 V
VIN
VIN
RG = 1 kW
RG = 1 kW
RS = 55 mW
Figure 17. Circuit Configuration for
Short Circuit Test #1
Figure 18. Circuit Configuration for
Short Circuit Test #2
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6
NGD18N40CLB
100
R(t), TRANSIENT THERMAL RESISTANCE (°C/Watt)
Duty Cycle = 0.5
0.2
10
0.1
0.05
0.02
1
0.01
0.1
0.01
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
P(pk)
Single Pulse
t1
0.001
t2
DUTY CYCLE, D = t1/t2
0.0001
0.00001
0.0001
0.001
TJ(pk) − TA = P(pk) RqJA(t)
RqJC X R(t) for t ≤ 0.2 s
0.01
t,TIME (S)
Figure 19. Transient Thermal Resistance
(Non−normalized Junction−to−Ambient mounted on
minimum pad area)
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7
0.1
1
NGD18N40CLB
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
−T−
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
4
Z
A
S
1
2
3
U
K
F
J
L
H
D
G
2 PL
0.13 (0.005)
M
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
0.180 0.215
0.025 0.040
0.020
−−−
0.035 0.050
0.155
−−−
STYLE 7:
PIN 1.
2.
3.
4.
T
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.57
5.45
0.63
1.01
0.51
−−−
0.89
1.27
3.93
−−−
GATE
COLLECTOR
EMITTER
COLLECTOR
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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