Cypress CY2DL15110AZC 1:10 differential lvds fanout buffer with selectable clock input Datasheet

CY2DL15110
1:10 Differential LVDS Fanout Buffer with
Selectable Clock Input
1:10 Differential LVDS Fanout Buffer with Selectable Clock Input
Features
Functional Description
■
Select one of two low-voltage differential signal (LVDS) input
pairs to distribute to 10 LVDS output pairs
■
40-ps maximum output-to-output skew
■
600-ps maximum propagation delay
■
0.11-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
■
Up to 1.5-GHz operation
■
Asynchronous output enable function
■
32-pin thin quad flat pack (TQFP) package
■
2.5-V or 3.3-V operating voltage [1]
■
Commercial and industrial operating temperature range
The CY2DL15110 is an ultra-low noise, low skew, low
propagation delay 1:10 LVDS fanout buffer targeted to meet the
requirements of high speed clock distribution applications. The
CY2DL15110 can select between two separate LVDS input clock
pairs using the IN_SEL pin. The output enable function allows
the outputs to be asynchronously driven to a high-impedance
state. The device has a fully differential internal architecture that
is optimized to achieve low additive jitter and low skew at
operating frequencies of up to 1.5 GHz.
Logic Block Diagram
VDD
Q0
Q0#
Q1
Q1#
VDD
VSS
Q2
Q2#
IN0
IN0#
Q3
Q3#
IN1
IN1#
Q4
Q4#
Q5
Q5#
IN_SEL
RP
Q6
Q6#
VBB
Q7
Q7#
VDD
RP
OE
Q8
Q8#
Q9
Q9#
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation
Document Number: 001-69398 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 12, 2012
CY2DL15110
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Absolute Maximum Ratings ............................................ 4
Operating Conditions ....................................................... 4
DC Electrical Specifications ............................................ 5
AC Electrical Specifications ............................................ 6
Ordering Information ........................................................ 9
Ordering Code Definitions ........................................... 9
Package Dimension ........................................................ 10
Document Number: 001-69398 Rev. *C
Acronyms ........................................................................ 11
Document Conventions ................................................. 11
Units of Measure ....................................................... 11
Document History Page ................................................. 12
Sales, Solutions, and Legal Information ...................... 13
Worldwide Sales and Design Support ....................... 13
Products .................................................................... 13
PSoC Solutions ......................................................... 13
Page 2 of 13
CY2DL15110
Pinouts
Q3
Q3#
Q4
Q4#
Q5
Q5#
Q6
Q6#
Figure 1. Pin Diagram - CY2DL15110
24
23
22
21
20
19
18
17
VSS
25
16
VDD
Q2#
26
15
Q7
Q2
27
14
Q7#
Q1#
28
13
Q8
Q1
29
12
Q8#
Q0#
30
11
Q9
Q0
31
10
Q9#
VDD
32
9
VSS
1
2
3
4
5
6
7
8
NC
IN_SEL
IN0
IN0#
VBB
IN1
IN1#
OE
CY2DL15110
Pin Definitions
Pin No.
Pin Name
Pin Type
Description
1
NC
2
IN_SEL
Input
Input clock select pin. Low-voltage complementary metal oxide semiconductor
(LVCMOS)/low-voltage transistor-transistor-logic (LVTTL).
When IN_SEL = Low, the IN0/IN0# differential input pair is active
When IN_SEL = High, the IN1/IN1# differential input pair is active
3
IN0
Input
LVDS input clock. Active when IN_SEL = Low
4
IN0#
Input
LVDS complementary input clock. Active when IN_SEL = Low
5
VBB
Output
LVDS reference voltage output
6
IN1
Input
LVDS input clock. Active when IN_SEL = High
7
IN1#
Input
LVDS complementary input clock. Active when IN_SEL = High
8
OE
Input
Output enable. LVCMOS/LVTTL;
When OE = Low, Q(0:9) and Q(0:9)# outputs are disabled
9, 25
VSS
Power
Ground
10, 12, 14, 17, 19, Q(0:9)#
21, 23, 26, 28, 30
Output
LVDS complementary output clocks
11, 13, 15, 18, 20, Q(0:9)
22, 24, 27, 29, 31
Output
LVDS output clocks
16, 32
Power
Power supply
VDD
No connection
Document Number: 001-69398 Rev. *C
Page 3 of 13
CY2DL15110
Absolute Maximum Ratings
Min
Max
Unit
VDD
Parameter
Supply voltage
Description
Nonfunctional
Condition
–0.5
4.6
V
VIN[2]
Input voltage, relative to VSS
Nonfunctional
–0.5
lesser of 4.0
or VDD + 0.4
V
VOUT[2]
DC output or I/O Voltage, relative to VSS
Nonfunctional
–0.5
lesser of 4.0
or VDD + 0.4
V
TS
Storage temperature
Nonfunctional
–55
150
°C
ESDHBM
Electrostatic discharge (ESD) protection
(Human body model)
JEDEC STD 22-A114-B
2000
–
V
LU
Latch up
UL–94
Flammability rating
MSL
Moisture sensitivity level
Meets or exceeds JEDEC Spec
JESD78B IC latch up test
At 1/8 in.
V–0
3
Operating Conditions
Min
Max
Unit
VDD
Parameter
Supply voltage
Description
2.5-V supply
Condition
2.375
2.625
V
3.3-V supply
3.135
3.465
V
TA
Ambient operating temperature
Commercial
0
70
°C
Industrial
–40
85
°C
tPU
Power ramp time
Power-up time for VDD to reach
minimum supply voltage (power
ramp must be monotonic.)
0.05
500
ms
tSTARTUP
Start up time
Time taken from VDD reaching
95% of its minimum supply
voltage to the device being
operational.
1
–
ms
Note
2. The voltage on any I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.
Document Number: 001-69398 Rev. *C
Page 4 of 13
CY2DL15110
DC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Condition
All LVDS outputs terminated with 100 load
[3, 4]
Min
Max
Unit
–
125
mA
IDD
Operating supply current
VIH1
Input high Voltage, LVDS input
clocks, IN0, IN0#, IN1, and IN1#
–
VDD + 0.3
V
VIL1
Input low voltage, LVDS input
clocks, IN0, IN0#, IN1, and IN1#
–0.3
–
V
VIH2
2.0
VDD + 0.3
V
VIL2
Input high voltage, IN_SEL and OE VDD = 3.3 V
Input low voltage, IN_SEL and OE VDD = 3.3 V
–0.3
0.8
V
VIH3
Input high voltage, IN_SEL and OE VDD = 2.5 V
1.7
VDD + 0.3
V
VIL3
Input low voltage, IN_SEL and OE VDD = 2.5 V
–0.3
0.7
V
VID[5]
Input differential amplitude
See Figure 3 on page 7
0.4
0.8
V
VICM
Input common mode voltage
See Figure 3 on page 7
0.5
VDD – 0.2
V
–
150
A
IIH
Input high current, All inputs
Input = VDD
[6]
VSS[6]
IIL
Input low current, All inputs
Input =
–150
–
A
VPP
LVDS differential output voltage
peak to peak, single-ended
VDD = 3.3 V or 2.5 V,
RTERM = 100  between Q and Q# pairs [3, 7]
250
470
mV
VOCM
Change in VOCM between
complementary output states
VDD = 3.3 V or 2.5 V,
RTERM = 100  between Q and Q# pairs [3, 7]
–
50
mV
VBB
Output reference voltage
0 to 150 A output current
1.125
1.375
V
IOZ
Output leakage current
OE = VSS, VOUT = 0.75 V to 1.75 V
–15
15
A
RP
Internal pull-up / pull-down
resistance, LVCMOS logic input
IN_SEL pin has pull-down only
OE pin has pull-up only
60
140
k
CIN
Input capacitance
Measured at 10 MHz per pin
–
3
pF
Notes
3. Refer to Figure 2 on page 7.
4. IDD includes current that is dissipated externally in the output termination resistors.
5. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of greater than 200 mV.
6. Positive current flows into the input pin, negative current flows out of the input pin.
7. Refer to Figure 4 on page 7.
Document Number: 001-69398 Rev. *C
Page 5 of 13
CY2DL15110
AC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Min
Typ
Max
Unit
DC
–
1.5
GHz
DC
–
1.5
GHz
Propagation delay input pair to output pair Input rise/fall time < 1.5 ns (20% to 80%)
–
–
600
ps
tODC[9]
Output duty cycle
50% duty cycle at input
Frequency range up to 1 GHz
48
–
52
%
tSK1[10]
Output-to-output skew
Any output to any output, with same load
conditions at DUT
–
–
40
ps
tSK1 D[10]
Device-to-device output skew
Any output to any output between two or
more devices. Devices must have the
same input and have the same output
load.
–
–
150
ps
PNADD
Additive RMS phase noise 156.25-MHz Offset = 1 kHz
input Rise/fall time < 150 ps (20% to 80%) Offset = 10 kHz
VID > 400 mV
Offset = 100 kHz
–
–
–120 dBc/Hz
–
–
–135 dBc/Hz
–
–
–135 dBc/Hz
Offset = 1 MHz
–
–
–150 dBc/Hz
Offset = 10 MHz
–
–
–154 dBc/Hz
FIN
Input frequency
FOUT
Output frequency
tPD[8]
Condition
FOUT = FIN
Offset = 20 MHz
–
–
–155 dBc/Hz
tJIT[11]
Additive RMS phase jitter (Random)
–
–
0.11
ps
tR, tF[12]
156.25 MHz, 12 kHz to 20 MHz offset;
input rise/fall time < 150 ps (20% to 80%),
VID > 400 mV
Output rise/fall time, single-ended
50% duty cycle at input,
20% to 80% of full swing (VOL to VOH)
Input rise/fall time < 1.5 ns (20% to 80%)
Measured at 1 GHz
–
–
300
ps
Notes
8. Refer to Figure 5 on page 7.
9. Refer to Figure 6 on page 7.
10. Refer to Figure 7 on page 8.
11. Refer to Figure 8 on page 8.
12. Refer to Figure 9 on page 8.
Document Number: 001-69398 Rev. *C
Page 6 of 13
CY2DL15110
Figure 2. LVDS Output Termination
Z = 50
BUF
QX
100
Z = 50
QX#
Figure 3. Input Differential and Common Mode Voltages
VA
IN
VICM = (VA + VB)/2
VID
IN#
VB
Figure 4. Output Differential and Common Mode Voltages
QX
VA
VOCM = (VA + VB)/2
VB
VOCM = | VOCM1 – VOCM2 |
VPP
QX#
Figure 5. Input to Any Output Pair Propagation Delay
IN
IN #
QX
Q X#
t PD
Figure 6. Output Duty Cycle
QX
Q X#
tPW
tPERIOD
tODC =
Document Number: 001-69398 Rev. *C
tPW
tPERIOD
Page 7 of 13
CY2DL15110
Figure 7. Output-to-output and Device-to-device Skew
QX
Device 1
Q X#
QY
Q Y#
tSK1
QZ
Device 2
Q Z#
tSK1 D
Figure 8. RMS Phase Jitter
Phase noise
Noise Power
Phase noise mark
Offset Frequency
f2
f1
RMS Jitter 
Area Under the Masked Phase Noise Plot
Figure 9. Output Rise/Fall Time
QX
80% 80%
VPP
20%
QX#
20%
tR
Document Number: 001-69398 Rev. *C
tF
Page 8 of 13
CY2DL15110
Ordering Information
Part Number
Type
Production Flow
Pb-free
CY2DL15110AZC
32-pin TQFP
Commercial, 0 °C to 70 °C
CY2DL15110AZCT
32-pin TQFP tape and reel
Commercial, 0 °C to 70 °C
CY2DL15110AZI
32-pin TQFP
Industrial, –40 °C to 85 °C
CY2DL15110AZIT
32-pin TQFP tape and reel
Industrial, –40 °C to 85 °C
Ordering Code Definitions
CY 2DL151 10
AZ X
T
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Grade: X = C or I
C = Commercial; I = Industrial
Package Type:
AZ = 32-pin TQFP (Pb-free)
Number of differential output pairs
Base Part Number
Company ID: CY = Cypress
Document Number: 001-69398 Rev. *C
Page 9 of 13
CY2DL15110
Package Dimension
Figure 10. 32-pin TQFP (7 × 7 × 1.0 mm) A3210 Package Outline, 51-85063
51-85063 *D
Document Number: 001-69398 Rev. *C
Page 10 of 13
CY2DL15110
Acronyms
Acronym
Document Conventions
Description
Units of Measure
ESD
electrostatic discharge
HBM
human body model
°C
degree Celsius
I/O
input/output
dBc
decibels relative to the carrier
JEDEC
joint electron devices engineering council
GHz
gigahertz
LVDS
low-voltage differential signal
Hz
hertz
LVCMOS
low-voltage complementary metal oxide
semiconductor
I/O
input/output
LVTTL
low-voltage transistor-transistor logic
kHz
kilohertz
OE
output enable
k
kilohm
RMS
root mean square
TQFP
thin quad flat pack
Document Number: 001-69398 Rev. *C
Symbol
Unit of Measure
µA
microampere
mA
milliampere
mm
millimeter
ms
millisecond
mV
millivolt
MHz
megahertz
ns
nanosecond

ohm
%
percent
pF
picofarad
ps
picosecond
V
volt
W
watt
Page 11 of 13
CY2DL15110
Document History Page
Document Title: CY2DL15110, 1:10 Differential LVDS Fanout Buffer with Selectable Clock Input
Document Number: 001-69398
Revision
ECN
Orig. of
Change
Submission
Date
**
3269680
CXQ
06/02/2011
New Datasheet.
*A
3292902
CXQ
06/27/2011
Minor edits in Logic Block Diagram (changed the OE resistor value from 100k
to RP).
Minor edits in Figure 2 and Figure 4 (Replaced “Q” and “Q#” with “QX” and
“QX#”).
Deleted the Notes “Refer to Figure 2.” and “Refer to Figure 4.” in page 7 and
their references in Figure 2 and Figure 4.
*B
3357978
BASH
09/07/2011
Updated Operating Conditions (Added a parameter tSTARTUP and its details).
Updated Package Dimension.
*C
3548521
BASH
03/12/2012
Changed status from Advance to Final.
Post to external web.
Document Number: 001-69398 Rev. *C
Description of Change
Page 12 of 13
CY2DL15110
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2011-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-69398 Rev. *C
Revised March 12, 2012
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 13 of 13
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