Renesas HD74LV2GT74AUSE Single d-type flip flops with preset and clear / cmos logic level shifter Datasheet

HD74LV2GT74A
Single D–type Flip Flops with Preset and Clear /
CMOS Logic Level Shifter
REJ03D0146–0200Z
(Previous ADE-205-681A (Z))
Rev.2.00
Oct.17.2003
Description
The HD74LV2GT74A has independent data, preset, clear, and clock inputs Q and Q outputs in an 8 pin
package. The input data is transferred to the output at the rising edge of clock pulse CLK. The input
protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used
as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to
3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high-speed
operation is suitable for the battery powered products (e.g., notebook computers), and the low power
consumption extends the battery life.
Features
• The basic gate function is lined up as Renesas uni logic series.
• Supplied on emboss taping for high-speed automatic mounting.
• TTL compatible input level.
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –40 to +85°C
• Logic-level translate function
3.0 V CMOS logic → 5.0 V CMOS logic (@VCC = 5.0 V)
1.8 V or 2.5 V CMOS logic → 3.3 V CMOS logic (@VCC = 3.3 V)
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
• All the logical input has hysteresis voltage for the slow transition.
• Ordering Information
Part Name
Package Type
HD74LV2GT74AUSE SSOP-8 pin
Rev.2.00, Oct.17.2003, page 1 of 1
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
TTP-8DBV
US
E (3,000 pcs/reel)
HD74LV2GT74A
Outline and Article Indication
• HD74LV2GT74A
Index band
Lot No.
Y M W
T 7 4
Y : Year code
(the last digit of year)
M : Month code
W : Week code
SSOP–8
Marking
Function Table
Inputs
Outputs
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
*1
H *1
L
L
X
X
H
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
↓
X
Q0
Q0
H : High level
L : Low level
X : Immaterial
↑ : Low to high transition
↓ : High to low transition
Q0 : The level of Q immediately before the input conditions shown in the above table are determined.
Note : 1. Q and Q will remain high as long as preset and clear are low, but Q and Q are unpredictable, if
preset and clear go high simultaneously.
Rev.2.00, Oct.17.2003, page 2 of 9
HD74LV2GT74A
Pin Arrangement
CLK
1
8
VCC
D
2
7
PRE
Q
3
6
CLR
GND
4
5
Q
(Top view)
Absolute Maximum Ratings
Item
Supply voltage range
Input voltage range
*1
Output voltage range
*1, 2
Symbol
Ratings
Unit
VCC
–0.5 to 7.0
V
VI
–0.5 to 7.0
V
VO
–0.5 to VCC + 0.5
V
–0.5 to 7.0
Test Conditions
Output : H or L
VCC : OFF
Input clamp current
IIK
–20
mA
VI < 0
Output clamp current
IOK
±50
mA
VO < 0 or VO > VCC
Continuous output current
IO
±25
mA
VO = 0 to VCC
Continuous current through
VCC or GND
ICC or IGND
±50
mA
Maximum power dissipation
*3
at Ta = 25°C (in still air)
PT
200
mW
Storage temperature
Tstg
–65 to 150
°C
Notes:
The absolute maximum ratings are values, which must not individually be exceeded, and
furthermore no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.2.00, Oct.17.2003, page 3 of 9
HD74LV2GT74A
Recommended Operating Conditions
Item
Symbol
Ratings
Unit
Supply voltage
VCC
3.0 to 5.5
V
Input voltage
VIN
0 to 5.5
V
Output voltage
VOUT
0 to VCC
V
Operating temperature
Topr
–40 to +85
°C
Input rise / fall time
tr, tf
0 to 100 (VCC = 3.0 to 3.6 V)
ns
0 to 20 (VCC = 4.5 to 5.5 V)
Note: Unused or floating inputs must be held high or low.
Logic Diagram
PRE
C
CLK
C
C
Q
TG
D
C
C
TG
TG
TG
C
C
C
CLR
Rev.2.00, Oct.17.2003, page 4 of 9
C
C
Q
HD74LV2GT74A
Electrical Characteristic
• Ta = –40 to 85°C
Item
Symbol VCC (V) *
Input voltage
VIH
VIL
Hysteresis voltage
Output voltage
VH
VOH
VOL
Min
Typ
Max
Unit Test condition
3.0 to 3.6
1.5
—
—
V
4.5 to 5.5
2.0
—
—
3.0 to 3.6
—
—
0.6
4.5 to 5.5
—
—
0.8
3.3
—
0.10
—
5.0
—
0.15
—
V
V
VT+ – VT–
IOH = –50 µA
Min to Max
VCC–0.1
—
—
3.0
2.48
—
—
IOH = –6 mA
4.5
3.8
—
—
IOH = –12 mA
Min to Max
—
—
0.1
IOL = 50 µA
3.0
—
—
0.44
IOL = 6 mA
4.5
—
—
0.55
IOL = 12 mA
Input current
IIN
0 to 5.5
—
—
±1
µA
VIN = 5.5 V or GND
Quiescent
supply current
ICC
5.5
—
—
10
µA
VIN = VCC or GND,
IO = 0
∆ICC
5.5
—
—
1.5
mA
One input VIN = 3.4 V,
other input VCC or GND
Output leakage current IOFF
0
—
—
5
µA
VO = 5.5 V
Input capacitance
5.0
—
2.5
—
pF
VIN = VCC or GND
CIN
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
Rev.2.00, Oct.17.2003, page 5 of 9
HD74LV2GT74A
Switching Characteristics
• VCC = 3.3 ± 0.3 V
Ta = 25°C
Item
FROM
Min
Typ
Max
Min
Max
Unit Conditions (Input)
Maximum clock fmax
frequency
80
140
—
70
—
MHz CL = 15 pF
50
90
—
45
—
CL = 50 pF
Propagation
delay time
—
7.0
12.5
1.0
14.5
—
8.0
12.0
1.0
14.0
—
9.0
16.0
1.0
18.0
—
10.0
15.5
1.0
17.5
6.0
—
—
7.0
—
5.0
—
—
5.0
—
Setup time
Symbol
Test
Ta = –40 to 85°C
tPLH
tPHL
tsu
ns
CL = 15 pF
TO
(Output)
PRE/CLR Q or Q
CLK
CL = 50 pF
PRE/CLR Q or Q
CLK
D
ns
PRE or CLR inactive
Hold time
th
0.5
—
—
0.5
—
ns
Pulse width
tw
6.0
—
—
7.0
—
ns
6.0
—
—
7.0
—
PRE or CLR “L”
CLK “H” or “L”
• VCC = 5.0 ± 0.5 V
Ta = 25°C
Item
FROM
Min
Typ
Max
Min
Max
Unit Conditions (Input)
Maximum clock fmax
frequency
130
180
—
110
—
MHz CL = 15 pF
90
140
—
75
—
CL = 50 pF
Propagation
delay time
—
5.0
7.7
1.0
9.0
—
5.6
7.3
1.0
8.5
—
6.6
9.7
1.0
11.0
—
7.2
9.3
1.0
10.5
5.0
—
—
5.0
—
3.0
—
—
3.0
—
Setup time
Symbol
Test
Ta = –40 to 85°C
tPLH
tPHL
tsu
ns
(Output)
PRE/CLR Q or Q
CLK
CL = 50 pF
PRE/CLR Q or Q
CLK
ns
D
PRE or CLR inactive
Hold time
th
0.5
—
—
0.5
—
ns
Pulse width
tw
5.0
—
—
5.0
—
ns
5.0
—
—
5.0
—
Rev.2.00, Oct.17.2003, page 6 of 9
CL = 15 pF
TO
PRE or CLR “L”
CLK “H” or “L”
HD74LV2GT74A
Operating Characteristics
• CL = 50 pF
Ta = 25°C
Item
Symbol
VCC (V) Min
Typ
Max
Unit
Test Conditions
Power dissipation
capacitance
CPD
5.0
14.0
—
pF
f = 10 MHz
—
Test Circuit
VCC
VCC
Input
PRE
Pulse Generator
Zout = 50 Ω
D
CL
Input
Pulse Generator
Zout = 50 Ω
Output Q
Q
CLK
CLR
Output Q
Q
CL
Notes: 1. C L includes probe and jig capacitance.
Rev.2.00, Oct.17.2003, page 7 of 9
HD74LV2GT74A
• Waveform – 1
tf
tr
VI
90 %
90 %
Vref
Timming input
10 %
10 %
t su
th
0V
VI
Data input
Vref
Vref
0V
tw
VI
Input
Vref
Vref
0V
• Waveform – 2
tf
tr
90 %
Vref
Input
VI
90 %
Vref
10 %
10 %
0V
t PHL
t PLH
VOH
Same-phase output
50 %
50 %
VOL
t PHL
t PLH
VOH
Opposite-phase output
50 %
50 %
VOL
INPUTS
VCC (V)
VI
Vref
t r / tf
3.3±0.3 2.5 V ≤ 3.0 ns
50%
≤ 3.0 ns
1.5 V
5.0±0.5
3V
Notes: 1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω.
2. The output are measured one at a time with one transition per measurement.
Rev.2.00, Oct.17.2003, page 8 of 9
HD74LV2GT74A
Package Dimensions
2.0 ± 0.2
1.5 ± 0.2
+ 0.1
(0.17)
8 − 0.2 − 0.05
Package Code
JEDEC
JEITA
Mass (reference value)
Rev.2.00, Oct.17.2003, page 9 of 9
+ 0.1
0.13 − 0.05
0 − 0.1
0.7 ± 0.1 (0.4)
2.3 ± 0.1
(0.5) (0.5) (0.5)
3.1 ± 0.3
(0.4)
Unit: mm
TTP–8DBV


0.010 g
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Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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