TI CY54FCT373ATDMB 8-bit latch Datasheet

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY54/74FCT373T
CY54/74FCT573T
8-Bit Latches
SCCS021 - May 1994 - Revised February 2000
Features
Functional Description
• Function and pinout compatible with FCT, and F logic
• FCT-C speed at 4.2 ns max. (Com’l),
FCT-A speed at 5.2 ns max. (Com’l)
• Reduced VOH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• ESD > 2000V
• Matched rise and fall times
• Extended commercial range of −40˚C to +85˚C
• Fully compatible with TTL input and output logic levels
• Sink current
64 mA (Com’l), 32 mA (Mil)
Source current 32 mA (Com’l), 12 mA (Mil)
The FCT373T and FCT573T consist of eight latches with
three-state outputs for bus organized applications. When latch
enable (LE) is HIGH, the flip-flops appear transparent to the
data. Data that meets the required set-up times are latched
when LE transitions from HIGH to LOW. Data appears on the
bus when the (OE) is LOW. When output enable is HIGH, the
bus output is in the impedance state. In this mode, data may
be entered into the latches. The FCT573T is identical to the
FCT373T except for the flow-through pinout, which simplifies
board design.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Logic Block Diagram
D0
D1
D2
D3
D4
D5
D6
D7
LE
CP
D
CP
CP
D
D
CP
D
CP
D
CP
D
CP
D
CP
D
Q
Q
Q
Q
Q
Q
Q
Q
O0
O1
O2
O3
O4
O5
O6
O7
OE
Pin Configurations
DIP/SOIC/QSOP
Top View
DIP/SOIC/QSOP
Top View
20
2
3
19
4
18
D3
17
16
O2
O3
O5
D4
6
D5
7
15
14
O4
D5
13
D4
D6
8
13
O6
12
11
O4
D7
GND
9
10
12
11
O7
20
2
3
19
18
VCC
O7
D7
D6
O6
O2
17
FCT373T
5
16
6
15
D2
7
14
D3
8
O3
GND
9
10
O1
1
D0
FCT573T
5
1
O0
D0
D1
OE
VCC
O0
O1
OE
4
D1
D2
LE
O5
LE
Logic Symbol
D0
LE
OE
O0
D1
D2
D3
D4
D5
D6
D7
O1
O2
O3
O4
O5
O6
O7
Copyright
© 2000, Texas Instruments Incorporated
CY54/74FCT373T
CY54/74FCT573T
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Function Table[1]
Inputs
DC Input Voltage ........................................... –0.5V to +7.0V
Outputs
OE
LE
D
O
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
DC Output Voltage......................................... –0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin) ...... 120 mA
Power Dissipation .......................................................... 0.5W
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Operating Range
Maximum Ratings[2, 3]
Range
Ambient
Temperature
VCC
T, AT, CT
–40°C to +85°C
5V ± 5%
All
–55°C to +125°C
5V ± 10%
Range
(Above which the useful life may be impaired. For user guidelines, not tested.)
Commercial
Storage Temperature .................................–65°C to +150°C
Military[4]
Ambient Temperature with
Power Applied .............................................–65°C to +135°C
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Test Conditions
Min.
Typ.[5]
Max.
Unit
VCC=Min., IOH=–32 mA
Com’l
2.0
V
VCC=Min., IOH=–15 mA
Com’l
2.4
3.3
V
VCC=Min., IOH=–12 mA
Mil
2.4
3.3
V
VCC=Min., IOL=64 mA
Com’l
0.3
0.55
V
VCC=Min., IOL=32 mA
Mil
0.3
0.55
V
VIH
Input HIGH Voltage
2.0
V
VIL
Input LOW Voltage
VH
Hysteresis[6]
All inputs
0.2
VIK
Input Clamp Diode Voltage
VCC=Min., IIN=–18 mA
–0.7
II
Input HIGH Current
IIH
0.8
V
V
–1.2
V
VCC=Max., VIN=VCC
5
µA
Input HIGH Current
VCC=Max., VIN=2.7V
±1
µA
IIL
Input LOW Current
VCC=Max., VIN=0.5V
±1
µA
IOZH
Off State HIGH-Level Output
Current
VCC=Max., VOUT=2.7V
10
µA
IOZL
Off State LOW-Level
Output Current
VCC=Max., VOUT=0.5V
–10
µA
IOS
Output Short Circuit Current[7]
VCC=Max., VOUT=0.0V
–225
mA
IOFF
Power-Off Disable
VCC=0V, VOUT=4.5V
±1
µA
–60
–120
Notes:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = HIGH Impedance
Qn = Previous state of flip flops (Qn-1)
2. Unless otherwise noted, these limits are over the operating free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
4. TA is the “instant on” case temperature.
5. Typical values are at VCC=5.0V, TA=+25˚C ambient.
6. This parameter is specified but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
2
CY54/74FCT373T
CY54/74FCT573T
Capacitance[6]
Parameter
Description
Typ.[5]
Max.
Unit
CIN
Input Capacitance
6
10
pF
COUT
Output Capacitance
8
12
pF
Power Supply Characteristics
Parameter
Description
Test Conditions
Typ.[5]
Max.
Unit
Quiescent Power Supply Current
VCC=Max., VIN ≤ 0.2V, VIN ≥ VCC – 0.2V
0.1
0.2
mA
∆ICC
Quiescent Power Supply Current
(TTL inputs HIGH)
VCC=Max., VIN=3.4V, f1=0, Outputs Open[8]
0.5
2.0
mA
ICCD
Dynamic Power Supply Current[9]
VCC=Max., One Input Toggling,
50% Duty Cycle, Outputs Open,
OE=GND, VIN ≤ 0.2V or VIN ≥ VCC – 0.2V
0.6
0.12
mA/MHz
IC
Total Power Supply Current[10]
VCC=Max., 50% Duty Cycle, Outputs Open,
One Bit Toggling at f1=10 MHz,
OE=GND, LE=VCC
VIN ≤ 0.2V or VIN ≥ VCC – 0.2V
0.7
1.4
mA
VCC=Max., 50% Duty Cycle, Outputs Open,
One Bit Toggling at f1=10 MHz,
OE=GND, LE=VCC, VIN=3.4V or VIN=GND
1.0
2.4
mA
VCC=Max., 50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f1=2.5 MHz,
OE=GND, LE=VCC,
VIN ≤ 0.2V or VIN ≥ VCC – 0.2V
1.3
2.6[11]
mA
VCC=Max., 50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f1=2.5 MHz,
OE=GND, LE=VCCVIN=3.4V or VIN=GND
3.3
10.6[11]
mA
ICC
Notes:
8. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
= IQUIESCENT + IINPUTS + IDYNAMIC
10. IC
IC
= ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC = Quiescent Current with CMOS input levels
∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V)
DH = Duty Cycle for TTL inputs HIGH
= Number of TTL inputs at DH
NT
ICCD = Dynamic Current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
f0
= Input signal frequency
f1
= Number of inputs changing at f1
N1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
3
CY54/74FCT373T
CY54/74FCT573T
e
Switching Characteristics Over the Operating Range[12]
FCT373T/FCT573T
Military
Parameter
Description
FCT373AT/FCT573AT
Commercial
Military
Commercial
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Fig.
No.[13]
tPLH
tPHL
Propagation Delay
D to O
1.5
8.5
1.5
8.0
1.5
5.6
1.5
5.2
ns
1, 3
tPLH
tPHL
Propagation Delay
LE to O
2.0
15.0
2.0
13.0
2.0
9.8
2.0
8.5
ns
1, 5
tPZH
tPZL
Output Enable Time
1.5
13.5
1.5
12.0
1.5
7.5
1.5
6.5
ns
1, 7, 8
tPHZ
tPLZ
Output Disable Time
1.5
10.0
1.5
7.5
1.5
6.5
1.5
5.5
ns
1, 7, 8
tS
Set-Up Time
HIGH to LOW
D to LE
2.0
2.0
2.0
2.0
ns
9
tH
Set-Up Time
HIGH to LOW
D to LE
1.5
1.5
1.5
1.5
ns
9
tW
LE Pulse
Width HIGH
6.0
6.0
6.0
5.0
ns
5
FCT373CT/
FCT573CT
Commercial
Parameter
Description
Min.
Max.
Unit
Fig. No.[13]
tPLH
tPHL
Propagation Delay D to O
1.5
4.2
ns
1, 3
tPLH
tPHL
Propagation Delay LE to O
2.0
5.5
ns
1, 5
tPZH
tPZL
Output Enable Time
1.5
5.5
ns
1, 7, 8
tPHZ
tPLZ
Output Disable Time
1.5
5.0
ns
1, 7, 8
tS
Set-Up Time, HIGH to LOW D to LE
2.0
ns
9
tH
Set-Up Time, HIGH to LOW D to LE
1.5
ns
9
tW
LE Pulse Width HIGH
5.0
ns
5
Note:
12. Minimum limits are specified but not tested on Propagation Delays.
13. See “Parameter Measurement Information” in the General Information section.
4
CY54/74FCT373T
CY54/74FCT573T
Ordering Information–FCT373T
Speed
(ns)
4.2
5.2
Ordering Code
CY74FCT373CTQCT
Package
Name
Q5
Package Type
20-Lead (150-Mil) QSOP
CY74FCT373CTSOC/SOCT
S5
20-Lead (300-Mil) Molded SOIC
CY74FCT373ATQCT
Q5
20-Lead (150-Mil) QSOP
Operating
Range
Commercial
Commercial
CY74FCT373ATSOC/SOCT
S5
20-Lead (300-Mil) Molded SOIC
5.6
CY54FCT373ATDMB
D6
20-Lead (300-Mil) CerDIP
8.0
CY74FCT373TSOC/SOCT
S5
20-Lead (300-Mil) Molded SOIC
Commercial
8.5
CY54FCT373TDMB
D6
20-Lead (300-Mil) CerDIP
Military
Military
Ordering Information—FCT573T
Speed
(ns)
4.2
5.2
8.0
8.5
Ordering Code
Package
Name
Package Type
CY74FCT573CTQCT
Q5
20-Lead (150-Mil) QSOP
CY74FCT573CTSOC/SOCT
S5
20-Lead (300-Mil) Molded SOIC
CY74FCT573ATPC
P5
20-Lead (300-Mil) Molded DIP
CY74FCT573ATQCT
Q5
20-Lead (150-Mil) QSOP
CY74FCT573ATSOC/SOCT
S5
20-Lead (300-Mil) Molded SOIC
CY74FCT573TQCT
Q5
20-Lead (150-Mil) QSOP
CY74FCT573TSOC/SOCT
S5
20-Lead (300-Mil) Molded SOIC
CY54FCT573TDMB
D6
20-Lead (300-Mil) CerDIP
Document #: 38-00272-B
5
Operating
Range
Commercial
Commercial
Commercial
Military
CY54/74FCT373T
CY54/74FCT573T
Package Diagrams
20-Lead (300-Mil) CerDIP D6
MIL-STD-1835
D- 8 Config.A
20-Lead (300-Mil) Molded DIP P5
6
CY54/74FCT373T
CY54/74FCT573T
Package Diagrams (continued)
20-Lead Quarter Size Outline Q5
20-Lead (300-Mil) Molded SOIC S5
7
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