AD AD8116 200 mhz, 16 x 16 buffered video crosspoint switch Datasheet

a
PRODUCT DESCRIPTION
The AD8116 is a high speed 16 × 16 video crosspoint switch
matrix. It offers a –3 dB signal bandwidth greater than 200 MHz
and channel switch times of 60 ns with 0.1% settling. With –70 dB
of crosstalk and –105 dB of isolation (@ 5 MHz), the AD8116
is useful in many high speed applications. The differential gain
and differential phase errors of better than 0.01% and 0.01°,
respectively, along with 0.1 dB flatness out to 60 MHz make the
AD8116 ideal for video signal switching.
The AD8116 includes output buffers that can be placed into a
high impedance state for paralleling crosspoint outputs so that
off channels do not load the output bus. It operates on voltage
*Patent Pending.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
AD8116
CLK
CLK
DATA IN
DATA OUT
80-BIT SHIFT REG.
UPDATE
CE
UPDATE
CE
80
PARALLEL LATCH
80
DECODE
16 ⴛ 5:16 DECODERS
256
RESET
SET INDIVIDUAL OR
RESET ALL OUTPUTS
TO "OFF"
RESET
16
OUTPUT
BUFFER
+1
+1
ENABLE/DISABLE
+1
+1
+1
SWITCH
MATRIX
+1
+1
16 INPUTS
+1
+1
+1
16 OUTPUTS
+1
+1
+1
+1
+1
+1
+0.5
+4
RL=150V
+3
+0.4
+2
+0.3
+0.2
+1
200mV p-p
0
–1
+0.1
FLATNESS
2V p-p
0
0.1dB FLATNESS – dB
APPLICATIONS
Routing of High Speed Signals Including:
Composite Video (NTSC, PAL, S, SECAM, etc.)
Component Video (YUV, RGB, etc.)
3-Level Digital (HDB3)
Video on Demand
Ultrasound
Communication Satellites
FUNCTIONAL BLOCK DIAGRAM
MAGNITUDE – dB
FEATURES
Large 16 ⴛ 16 High Speed Nonblocking Switch Array
Switch Array Controllable via an 80-Bit Serial Word
Serial Data Out Allows “Daisy Chaining” of Multiple
AD8116s to Create Large Switch Arrays Over 256 ⴛ 256
Complete Solution
Buffered Inputs
16 Individual Output Amplifiers
Drives 150 ⍀ Loads
Excellent Video Performance
60 MHz 0.1 dB Gain Flatness
0.01% Differential Gain Error (RL = 150 ⍀)
0.01ⴗ Differential Phase Error (R L = 150 ⍀)
Excellent AC Performance
200 MHz –3 dB Bandwidth
300 V/␮s Slew Rate
Low Power of 900 mW (3.5 mW per Point)
Low All Hostile Crosstalk of –70 dB @ 5 MHz
Output Disable Allows Direct Connection of Multiple
Device Outputs
Chip Enable Allows Selection of Individual AD8116s in
Large Arrays (or Parallel Programming of AD8116s)
Reset Pin Allows Disabling of All Outputs (Connected
Through a Capacitor to Ground Provides “PowerOn” Reset Capability)
128-Lead LQFP Package (14 mm ⴛ 14 mm)
200 MHz, 16 ⴛ 16 Buffered
Video Crosspoint Switch
AD8116*
–0.1
–2
2V p-p
–0.2
–3
200mV p-p
–4
100k
1M
10M
FREQUENCY – Hz
100M
–0.3
1G
Figure 1. Frequency Response
supplies of ±5 V while consuming only 90 mA of idle current.
The channel switching is performed via a serial digital control
that can accommodate “daisy chaining” of several devices.
The AD8116 is packaged in a 128-lead LQFP package occupying only 0.36 square inches, and is specified over the commercial temperature range of 0°C to +70°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD8116–SPECIFICATIONS (V = ⴞ 5 V, T = +25ⴗC, R = 1 k⍀ unless otherwise noted)
S
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Slew Rate
Settling Time
Gain Flatness
NOISE/DISTORTION PERFORMANCE
Differential Gain Error
Differential Phase Error
Crosstalk, All Hostile
Off Isolation, Input-Output
Input Voltage Noise
DC PERFORMANCE
Gain
Gain Matching
OUTPUT CHARACTERISTICS
Output Offset Voltage
Output Impedance
Output Disable Capacitance
Output Leakage Current
Output Voltage Range
Output Current
Short Circuit Current
INPUT CHARACTERISTICS
Input Voltage Range
Input Capacitance
Input Resistance
Input Bias Current
SWITCHING CHARACTERISTICS
Enable On Time
Switching Time
A
L
Conditions
Min
Supply Voltage Range
PSRR
OPERATING TEMPERATURE RANGE
Temperature Range
θJA
Max
Units
Reference
Figure
200 mV p-p, R L = 150 Ω
1 V p-p, RL = 150 Ω
2 V p-p, RL = 150 Ω
2 V Step, RL = 150 Ω
0.1%, 2 V Step, RL = 150 Ω
0.05 dB, 200 mV p-p, R L = 150 Ω
0.05 dB, 2 V p-p, R L = 150 Ω
0.1 dB, 200 mV p-p, R L = 150 Ω
0.1 dB, 2 V p-p, RL = 150 Ω
200
120
80
300
60
25
20
60
45
MHz
MHz
MHz
V/µs
ns
MHz
MHz
MHz
MHz
6
–
6
10
11
6
6
6
6
NTSC or PAL, RL = 1 kΩ
NTSC or PAL, RL = 150 Ω
NTSC or PAL, RL = 1 kΩ
NTSC or PAL, RL = 150 Ω
ƒ = 5 MHz
ƒ = 10 MHz
ƒ = 10 MHz, RL = 150 Ω, One Channel
0.01 MHz to 50 MHz
0.01
0.01
0.01
0.01
–70
–60
–105
15
%
%
Degrees
Degrees
dB
dB
dB
nV/√Hz
–
–
–
–
7
7
16
13
1.000
1.000
0.15
0.5
V/V
V/V
%
%
–
–
–
–
45
mV
Ω
MΩ
pF
µA
V
mA
mA
22
17
14
14
–
–
–
–
V
pF
MΩ
µA
–
18
18
–
60
50
ns
ns
–
21
15
mV p-p
15
ƒ = 100 kHz
ƒ = 1 MHz
75
95
25
70
95
22.5
25
35
10
15
± 4.5 to ± 5.5
60
40
mA
mA
mA
mA
mA
mA
V
dB
dB
–
–
–
–
–
–
–
12
12
Operating (Still Air)
Operating (Still Air)
0 to +70
37
°C
°C/W
–
–
No Load
RL = 1 kΩ
No Load, Ch-Ch
RL = 1 kΩ, Ch-Ch
0.995 0.999
0.992 0.999
Worst Case All Switch Configurations
DC, Enabled
Disabled
1
Disabled
± 2.5
20
± 2.5
Any Switch Configuration
1
50% UPDATE to 1% Output Settling,
2 V Step
Switching Transient (Glitch)
POWER SUPPLIES
Supply Current
Limit
Typ
AVCC, Outputs Enabled, No Load
AVCC, Outputs Disabled
AVEE, Outputs Enabled, No Load
AVEE, Outputs Disabled
DVCC, Outputs Enabled, No Load
DVEE, Outputs Enabled, No Load
15
0.2
10
3
1
±3
40
65
±3
5
10
2
5
Specifications subject to change without notice.
–2–
REV. A
AD8116
TIMING CHARACTERISTICS
Parameter
Symbol
Min
Data Setup Time
CLK Pulsewidth
Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulsewidth
CLK to DATA OUT Valid
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz
CLK, UPDATE Rise and Fall Times
RESET Time
t1
t2
t3
t4
t5
t6
t7
–
–
–
–
20
100
20
100
0
50
t2
Limit
Typ
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
200
50
16
100
200
t4
1
CLK
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
0
t1
t3
1
DATA IN
0
OUT15 (D4)
OUT15 (D3)
OUT00 (D0)
t5
1 = LATCHED
UPDATE
0 = TRANSPARENT
t6
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t7
DATA OUT
0 1 2 3 4 5 6 7 8 9 10
15
20
25
75
79
CLOCK
T=0
CONNECT TO
INPUT 00
ENABLE OUTPUT 00
CONNECT TO
INPUT 03
ENABLE OUTPUT 11
CONNECT TO
INPUT 15
ENABLE OUTPUT 12
DON’T CARE
DISABLE OUTPUT 13
UPDATE
CONNECT TO
INPUT 01
ENABLE OUTPUT 14
CONNECT TO
NPUT 00
ENABLE OUTPUT 15
DATA IN
INCREASING TIME
Figure 2. Timing Diagram and Programming Example
Table I. Logic Levels
VIH
VIL
VOH
VOL
IIH
IIL
IOH
IOL
CLK, DATA IN,
CE, UPDATE
CLK, DATA IN,
CE, UPDATE
DATA OUT
DATA OUT
CLK, DATA IN,
CE, UPDATE
CLK, DATA IN,
CE, UPDATE
DATA OUT
DATA OUT
2.0 V min
0.8 V max
2.7 V min
0.5 V max
20 µA max
–400 µA min
–400 µA max
3.0 mA min
REV. A
–3–
AD8116
ABSOLUTE MAXIMUM RATINGS 1
MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.0 V
Internal Power Dissipation2
AD8116 128-Lead Plastic LQFP (ST) . . . . . . . . . . . . 3.5 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± VS
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
The maximum power that can be safely dissipated by the
AD8116 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition
temperature of the plastic, approximately +150°C. Temporarily
exceeding this limit may cause a shift in parametric performance
due to a change in the stresses exerted on the die by the package.
Exceeding a junction temperature of +175°C for an extended
period can result in device failure.
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air (T A = +25°C):
128-lead plastic LQFP (ST): θJA = 37°C/W.
While the AD8116 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction temperature (+150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves shown in Figure 3.
5.0
TJ = 150ⴗC
Model
Temperature
Range
AD8116JST 0°C to +70°C
AD8116-EB
Package
Description
MAXIMUM POWER DISSIPATION – Watts
ORDERING GUIDE
Package
Option
128-Lead Plastic LQFP ST-128A
(14 mm × 14 mm)
Evaluation Board
4.0
3.0
2.0
1.0
0
–50 –40 –30 –20 –10
0
10
20
30 40
50
60 70
80 90
AMBIENT TEMPERATURE – ⴗC
Figure 3. Maximum Power Dissipation vs. Temperature
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8116 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. A
AD8116
Table II. Operation Truth Table
Control Lines
CE
UPDATE
CLK
DATA IN
DATA OUT
RESET
Operation/Comment
1
0
X
1
X
f
X
Data i
X
Data i-80
1
1
0
0
X
X
X
1
X
X
X
X
X
0
No change in logic.
The data on the DATA IN line is loaded into the
serial register. The first bit clocked into the serial
register appears at DATA OUT 80 clocks later.
Data in the serial shift register transfers into the
parallel latches that control the switch array.
Latches are transparent.
Asynchronous operation. All outputs are disabled.
Remainder of logic is unchanged.
DATA IN
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
DATA OUT
CLK
LE
OUTPUT CH
CH BIT #
SERIAL BIT #
D LE
D LE
D LE
D LE
D LE
D
OUT0
OUT0
OUT0
OUT0
OUT0
OUT1
0
LSB
79
1
2
3
EN
MSB
75
0
Q
78
77
Q
76
Q
Q CLR Q
LE
D LE
D LE
D LE
D LE
D LE
D
OUT14 OUT15 OUT15 OUT15 OUT15 OUT15
EN
74
5
Q
CLR Q
0
LSB
4
Q
1
2
3
3
2
Q
1
Q
EN
MSB
0
Q CLR Q
DECODE
256
16
SWITCH MATRIX
OUTPUT
ENABLE
Figure 4. Logic Diagram
REV. A
–5–
AD8116
PIN FUNCTION DESCRIPTIONS
Pin Name
Pin Numbers
Pin Description
INxx
2, 4, 6, 8, 10, 12, 14, 16, 18,
20, 22, 24, 26, 28, 30, 32
37, 126
36, 125
35, 124
38, 123
Analog Inputs; xx = Channel No. 00 thru 15.
DATA IN
CLK
DATA OUT
UPDATE
RESET
CE
OUTyy
AGND
DVCC
DGND
DVEE
AVEE
AVCC
AGNDxx
AVCC00
AVCC15
AVCCxx/yy
AVEExx/yy
39, 122
40, 121
65, 67, 69, 71, 73, 75, 77, 79,
81, 83, 85, 87, 89, 91, 93, 95
1, 3, 5, 7, 9, 11, 13, 15, 17, 19,
21, 23, 25, 27, 29, 31, 33, 128
34, 39, 127
41, 120
42, 119
43, 44, 45, 116, 117, 118
46, 47, 48, 113, 114, 115
56–63, 97–104
96
64
68, 72, 76, 80, 84, 88, 92
66, 70, 74, 78, 82, 86, 90, 94
Serial Data Input, TTL Compatible.
Serial Clock, TTL Compatible. Falling edge triggered.
Serial Data Out, TTL Compatible.
Enable (Transparent) “Low.” Allows serial register to connect directly to switch
matrix. Data latched when “high.”
Disable Outputs, Enable “Low.”
Chip Enable, Enable “Low.” Must be “low” to clock in & latch data.
Analog Outputs yy = Channel Nos. 00 thru 15.
Analog Ground for inputs and switch matrix.
+5 V for Digital Circuitry.
Ground for Digital Circuitry.
–5 V for Digital Circuitry.
–5 V for Inputs and Switch Matrix.
+5 V for Inputs and Switch Matrix.
Ground for Output Amp, xx = Output Channel Nos. 00 thru 15. Must be connected.
+5 V for Output Channel 00. Must be connected.
+5 V for Output Channel 15. Must be connected.
+5 V for Output Amplifier that is shared by Channel Nos. xx and yy. Must be connected.
–5 V for Output Amplifier that is shared by Channel Nos. xx and yy. Must be connected.
VCC
VCC
VCC
ESD
ESD
INPUT
ESD
OUTPUT
ESD
20k⍀
RESET
ESD
ESD
VEE
VEE
a. Analog Input
b. Analog Output
c. Reset Input
VCC
VCC
ESD
2k⍀
ESD
OUTPUT
INPUT
ESD
ESD
VEE
VEE
d. Logic Input
e. Logic Output
Figure 5. I/O Pin Schematics
–6–
REV. A
AD8116
97 AGND07
98 AGND06
99 AGND05
101 AGND03
100 AGND04
102 AGND02
104 AGND00
103 AGND01
105 NC
106 NC
108 NC
107 NC
109 NC
111 NC
110 NC
112 NC
113 AVCC
115 AVCC
114 AVCC
116 AVEE
117 AVEE
118 AVEE
119 DVEE
121
120 DGND
122
124 DATA OUT
123
126 DATA IN
125 CLK
128 AGND
127 DVCC
PIN CONFIGURATION
96 AVCC00
AGND
1
IN00
2
AGND
3
94 AVEE00/01
IN01
4
93 OUT01
AGND
5
92 AVCC01/02
IN02
6
91 OUT02
AGND
7
90 AVEE02/03
IN03
8
89 OUT03
AGND
9
88 AVCC03/04
PIN 1
IDENTIFIER
95 OUT00
87 OUT04
IN04 10
86 AVEE04/05
AGND 11
IN05 12
85 OUT05
AGND 13
84 AVCC05/06
AD8116
IN06 14
83 OUT06
128L LQFP
(14mm x 14mm)
TOP VIEW
(Not to Scale)
AGND 15
IN07 16
AGND 17
82 AVEE06/07
81 OUT07
80 AVCC07/08
79 OUT08
IN08 18
78 AVEE08/09
AGND 19
77 OUT09
IN09 20
AGND 21
76 AVCC09/10
IN10 22
75 OUT10
AGND 23
74 AVEE10/11
IN11 24
73 OUT11
72 AVCC11/12
AGND 25
71 OUT12
IN12 26
70 AVEE12/13
AGND 27
69 OUT13
IN13 28
AGND 29
68 AVCC13/14
IN14 30
67 OUT14
AGND 31
66 AVEE14/15
NC = NO CONNECT
REV. A
–7–
AVCC15 64
AGND08 63
AGND09 62
AGND10 61
AGND11 60
AGND12 59
AGND13 58
AGND14 57
NC 55
AGND15 56
NC 54
NC 53
NC 52
NC 51
NC 50
NC 49
AVCC 48
AVCC 47
AVCC 46
AVEE 45
AVEE 44
AVEE 43
DVEE 42
DGND 41
39
40
38
DATA IN 37
CLK 36
DATA OUT 35
DVCC 34
65 OUT15
AGND 33
IN15 32
AD8116 –Typical Performance Characteristics
+0.5
+4
100mV p-p
+0.4
MAGNITUDE – dB
+2
+0.3
+1
+0.2
200mV p-p
0
+0.1
FLATNESS
–1
2V p-p
0
–2
FLATNESS – dB
+3
RL=150V
CL=0pF
25mV/DIV
–0.1
2V p-p
–3
–0.2
200mV p-p
–4
100k
1M
10M
FREQUENCY – Hz
–0.3
1G
100M
100ns/DIV
Figure 9. Step Response, 100 mV Step
Figure 6. Frequency Response
–10
–20
RL = 1kV
RS = 37.5V
ALL HOSTILE CROSSTALK
VIN = 632mV p-p
CROSSTALK – dB
–30
–40
2V p-p
–50
500mV/DIV
–60
–70
ADJACENT CHANNEL
CROSSTALK
VIN = 632mV p-p
–80
–90
–100
300k
100ns/DIV
1M
10M
FREQUENCY – Hz
100M 200M
Figure 10. Step Response, 2 V Step
Figure 7. Crosstalk vs. Frequency
0
VIN = 2V p-p, RL = 150V
HARMONIC DISTORTION – dB
–10
2V STEP
RL = 150⍀
–20
–30
–40
2mV/DIV
= 0.1%/DIV
–50
–60
2ND HARMONIC
–70
3RD HARMONIC
–80
–90
–100
100k
1M
10M
FREQUENCY – Hz
0
100M
20
40 60 80 100 120 140 160 180
20ns/DIV
Figure 11. Settling Time
Figure 8. Total Harmonic Distortion
–8–
REV. A
Typical Performance Characteristics–AD8116
POWER SUPPLY REJECTION – dB
–20
5
4
3
1V/DIV 2
1
0
–30
–40
20
10
–50
10mV/DIV 0
–10
–60
–20
–70
10k
100k
1M
FREQUENCY – Hz
50ns/DIV
10M
Figure 15. Switching Transient (Glitch)
Figure 12. PSRR vs. Frequency
–50
316
–60
–70
OFF ISOLATION – dB
nV/ Hz
100
31.6
10
VIN = 2V p-p
–80
–90
–100
–110
–120
–130
–140
3.16
10
–150
100k
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
1M
100M
10M
FREQUENCY – Hz
100M
500M
Figure 16. Off Isolation, Input-Output
Figure 13. Voltage Noise vs. Frequency
10,000
10M
1000
OUTPUT IMPEDANCE – Ω
OUTPUT IMPEDANCE – ⍀
1M
100k
10k
100
10
1
1k
0.1
100
100k
1M
10M
FREQUENCY – Hz
100M
500M
1M
10M
FREQUENCY – Hz
100M
Figure 17. Output Impedance, Enabled
Figure 14. Output Impedance, Disabled
REV. A
100k
–9–
500M
AD8116
10M
INPUT IMPEDANCE – V
1M
VOUT
100k
10k
1k
100mV, 50ns
100
30k
100k
1M
10M
FREQUENCY – Hz
100M
500M
Figure 18. Input Impedance vs. Frequency
Figure 21. Switching Time
+15
+12
VIN = 200mV
RL = 150V
+9
30pF
18pF
+3
FREQUENCY
GAIN – dB
+6
0
12pF
–3
–6
–9
–12
–15
30k
100k
1M
10M
FREQUENCY – Hz
100M
500M
170
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
–0.035
Figure 19. Frequency Response vs. Capacitive Load
–0.025
–0.015
–0.005
0.005
OFFSET VOLTAGE – Volts
0.015
0.025
Figure 22. Offset Voltage Distribution
+0.5
2.0
VIN = 200mV
RL = 150V
+0.4
1.5
+0.3
CL = 30pF
1.0
CL = 18pF
+0.1
0.5
VOS – mV
FLATNESS – dB
+0.2
0
–0.1
CL = 12pF
0.0
–0.5
–0.2
–0.3
–1.0
–0.4
–1.5
–0.5
30k
100k
1M
FREQUENCY – Hz
10M
100M
–2.0
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE – 8C
Figure 20. Flatness vs. Capacitive Load
Figure 23. Offset Voltage Drift vs. Temperature
–10–
REV. A
AD8116
THEORY OF OPERATION
APPLICATIONS
Multichannel Video
Loading Data
Data to control the switches is clocked serially into an 80-bit
shift register and then transferred in parallel to an 80-bit latch.
The falling edge of CLK (the serial clock input) loads data into
the shift register. The first five bits of the 80 bits are loaded via
DATA IN (the serial data input) program OUT15. The first of
the five bits (D4) enables or disables the output. The next four
bits (D3–D0, D3 = MSB, D0 = LSB) determine which one of
the 16 inputs will be connected to OUT15 (only one of the 16
inputs can be connected to a given output). The remaining bits
program OUT14 thru OUT00.
The excellent video specifications of the AD8116 make it an
ideal candidate for creating composite video crosspoint switches.
These can be made quite dense by taking advantage of the
AD8116’s high level of integration and the fact that composite
video requires only one crosspoint channel per system video
channel. There are, however, other video formats that can be
routed with the AD8116 requiring more than one crosspoint
channel per video channel.
Some systems use twisted pair wiring to carry video signals.
These systems utilize differential signals and can lower costs
because they use lower cost cables, connectors and termination
methods. They also have the ability to lower crosstalk and reject
common-mode signals, which can be important for equipment that operates in noisy environments or where commonmode voltages are present between transmitting and receiving
equipment.
After the shift register is filled with the new 80 bits of control
data, UPDATE is activated (low) to transfer the data to the
parallel latches. The switch control latches are static and will
hold their data as long as power is applied.
To extend the number of switches in an array, the DATA
OUT and DATA IN pins of multiple AD8116s can be daisychained together. The DATA OUT pin is the end of the shift
register and may be directly connected to the DATA IN pin of
the follow-on AD8116. CE can be used to control the clocking
of data into selected devices.
In such systems, the video signals are differential; there is a
positive and negative (or inverted) version of the signals. These
complementary signals are transmitted onto each of the two
wires of the twisted pair, yielding a first order zero commonmode voltage. At the receive end, the signals are differentially
received and converted back into a single-ended signal.
Serial Logic
The AD8116 employs a serial interface for programming the
state of the crosspoint array. The 80-bit shift register (Figure 4)
consists of static D flip-flops while the parallel latch uses transparent latches that are latched by a logic high state of UPDATE,
and transparent on logic low of the same signal. The 4-to-16
decoder is a small current-mode multilevel gate array that steers
a small select current to the selected point in the crosspoint array.
The RESET signal is connected to only the enable/disable bit on
each output buffer. This means that the AD8116 will have a
random configuration on power-up. In normal operation though,
RESET and UPDATE can be used together to alternately enable and disable an entire array at once, if desired.
Separate chip enable (CE), update (UPDATE) and serial data
out (DATA OUT) signals allow several options for programming larger arrays of AD8116s. The function of each bit in the
80-bit word that programs the state of the AD8116 is shown in
Figure 4. In normal operation, the DATA OUT pin of one
AD8116 is connected to the DATA IN of the next. In this way, for
example, an array of eight AD8116s would be programmed with
one 640-bit sequence. In this mode CE is logic low and the
CLK and UPDATE pins are connected in parallel.
In one alternate mode of programming, the CE pin can be used
to select one AD8116 at a time. This might be desirable when
the ability to program just one device at a time is required. In
this mode CLK, UPDATE and DATA IN are all connected in
parallel. The user then selects each AD8116 in turn (with the
CE signal) and programs it with the desired data. Larger arrays
can also be programmed by connecting each DATA IN signal to
a larger parallel bus. In this way only 80 clock cycles would be
needed to program the entire array. The logic signals are configured so that all programming can be accomplished with
synchronous logic and a continuous clock, so that no missing
cycles or delays need be generated.
REV. A
When switching these differential signals, two channels are
required in the switching element to handle the two differential
signals that make up the video channel. Thus, one differential
video channel is assigned to a pair of crosspoint channels, both
input and output. For a single AD8116, eight differential video
channels can be assigned to the 16 inputs and 16 outputs. This
will effectively form an 8 × 8 differential crosspoint switch.
Programming such a device will require that inputs and outputs
be programmed in pairs. This information can be deduced by
inspection of the programming format of the AD8116 and the
requirements of the system.
There are other analog video formats requiring more than one
analog circuit per video channel. One two-circuit format that is
more commonly being used in systems such as satellite TV,
digital cable boxes and higher quality VCRs, is called S-video or
Y/C video. This format carries the brightness (luminance or Y)
portion of the video signal on one channel and the color
(chrominance or C) on a second channel.
Since S-video also uses two separate circuits for one video channel, creating a crosspoint system requires assigning one video
channel to two crosspoint channels as in the case of a differential video system. Aside from the nature of the video format,
other aspects of these two systems will be the same.
There are yet other video formats using three channels to carry
the video information. Video cameras produce RGB (red, green,
blue) directly from the image sensors. RGB is also the usual
format used by computers internally for graphics. RGB can also
be converted to Y, R-Y, B-Y format, sometimes called YUV
format. These three-circuit video standards are referred to as
component analog video.
The three-circuit video standards require three crosspoint channels per video channel to handle the switching function. In a
fashion similar to the two-circuit video formats, the inputs and
outputs are assigned in groups of three and the appropriate logic
programming is performed to route the video signals.
–11–
AD8116
Creating Larger Crosspoint Arrays
The AD8116 is a high density building block for crosspoint
arrays over 256 × 256. Various features such as output disable,
chip enable, serial data out and multiple pinouts for logic signals
are very useful for the creation of these larger arrays.
The first consideration in constructing a larger crosspoint is to
determine the minimum number of devices that are required.
The 16 × 16 architecture of the AD8116 contains 256 “points,”
which is a factor of four greater than an 8 × 8 crosspoint and a
factor of 64 greater than a 4 × 1 crosspoint. The PC board area
and power consumption savings are readily apparent when
compared to using these smaller devices.
For a nonblocking crosspoint, the number of points required is
the product of the number of inputs multiplied by the number
of outputs. Nonblocking requires that the programming of a
given input to one or more outputs does not restrict the availability of that input to be a source for any other outputs.
Using additional crosspoint devices in the design can lower the
number of outputs that have to be wire-ORed together. Figure
26 shows a block diagram of a system using ten AD8116s to
create a nonblocking 128 × 16 crosspoint that restricts the wireORing at the output to only four outputs. This will prevent an
enabled output from having to drive a large number of disabled
devices. Additionally, by using the lower eight outputs from
each of the two Rank 2 AD8116s, a blocking 128 × 32 crosspoint
array can be realized.
There are, however, some drawbacks to this technique. The
offset voltages of the various cascaded devices will accumulate
and the bandwidth limitations of the devices will compound. In
addition, the extra devices will consume more current and take
up more board space. Once again, the overall system design
specifications will determine how to make the various trade-offs.
Thus a 32 × 32 crosspoint will require 1024 points. This number is
then divided by 256, or the number of points in one AD8116
device, to yield four in this case. This says that the minimum
number of 16 × 16 devices required for a fully programmable
32 × 32 crosspoint is four.
The 32 × 32 crosspoint requires each input driver drive two
inputs in parallel and each output be wire-ORed with one other
output. The 48 × 48 crosspoint requires driving three inputs in
parallel and having the outputs wire-ORed in groups of three. It
is required of the system programming that only one output of a
wired-OR node be active at a time.
It is not essential that crosspoint architectures be square. For
example, a 64 × 16 crosspoint array can be constructed with
four AD8116s by driving each input with a separate signal and
wire-ORing together the corresponding outputs of each device.
It can be seen, however, that by going to larger arrays the
number of disabled outputs an active output has to drive
starts to increase.
IN
0–15
OUT
AD8116
IN
OUT
16
Some nonblocking crosspoint architectures will require more
than this minimum as calculated above. Also, there are blocking
architectures that can be constructed with fewer devices than this
minimum. These systems have connectivity available on a statistical basis that is determined when designing the overall system.
The basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to “wireOR” the outputs together in the vertical direction. The meaning
of horizontal and vertical can best be understood by looking at a
diagram. Figure 24 illustrates this concept for a 32 × 32 crosspoint
array. A 48 × 48 crosspoint is illustrated in Figure 25.
AD8116
IN 0–15
AD8116
IN 16–31
IN
16–31
OUT
AD8116
IN
OUT
16
16
16
OUT 0–15
OUT 16–31
Figure 24. 32 × 32 Crosspoint Array Using Four AD8116s
AD8116
IN 0–15
IN
AD8116
OUT
IN
AD8116
OUT
IN
OUT
16
AD8116
IN 16–31
IN
AD8116
OUT
IN
AD8116
OUT
IN
OUT
16
AD8116
IN 32–47
At some point, the number of outputs that are wire-ORed becomes too great to maintain system performance. This will vary
according to which system specifications are most important.
For example, a 128 × 16 crosspoint can be created with eight
AD8116s. This design will have 128 separate inputs and have
the corresponding outputs of each device wire-ORed together
in groups of eight.
IN
AD8116
OUT
IN
AD8116
OUT
IN
OUT
16
16
OUT 0–15
16
OUT 16–31
16
OUT 32–47
Figure 25. 48 × 48 Crosspoint Array Using Nine AD8116s
–12–
REV. A
AD8116
capacitor to the logical high state. If several AD8116s are used,
the pull-up resistors will be in parallel, so a larger value capacitance should be used.
RANK 1
(128:32)
8
IN 0–15
16
8
If the system requires the ability to be reset while power is still
applied, the RESET driver will have to be able to charge and
discharge this capacitance in the required time. With too many
devices in parallel, this might become more difficult; if this
occurs, the reset circuits should be broken up into smaller subsets with each controlled by a separate driver.
8
IN 16–31
16
8
8
IN 32–47
16
8
8
IN 48–63
16
RANK 2
32:16 NONBLOCKING
(32:32 BLOCKING)
8
8
NONBLOCKING
OUTPUTS
CROSSTALK
OUT 0–16
8
8
IN 64–79
8
16
8
8
ADDITIONAL
16 OUTPUTS
8
IN 80–95
16
8
8
IN 96–111
16
8
FOUR AD8116 OUTPUTS
WIRE-ORED TOGETHER
8
IN 112–127
16
8
Figure 26. Nonblocking 128 × 16 Array (128 × 32 Blocking)
Logic Operation
There are two basic options for controlling the logic in multicrosspoint arrays. One is to serially connect the data paths
(DATA OUT to DATA IN) of all the devices and tie all the
CLK and UPDATE signals in parallel. CE can be tied low for
all the devices. A long serial sequence with the desired programming data consisting of 80 bits times the number of
AD8116 devices can then be shifted through all the parallel
devices by using the DATA IN of the first device and the CLK.
When finished clocking in the data, UPDATE can be pulled low
to program all the device crosspoint matrices.
This technique has an advantage in that a separate CE signal
is not required for each chip, but has a disadvantage in that
several chips’ data cannot be shifted in parallel. In addition, if
another device is added into the system between already existing
devices, the programming sequence will have to be lengthened
at some midpoint to allow for programming of the added device.
The second programming method is to connect all the CLK
and the DATA IN pins in parallel and use the CE pins in sequence to program each device. If a byte or 16-bit word of data
is available for providing the programming data, then multiple
AD8116s can be programmed in parallel with just 80 clock
cycles. This method can be used to speed up the programming
of large arrays. Of course, in a practical system, various combinations of these basic methods can be used.
Power-On Reset
Most systems will want all the AD8116s to be in the reset state
(all outputs disabled) when power is applied to the system. This
ensures that two outputs that are wire-ORed together will not
fight each other at power up.
The power-on reset function can be implemented by adding a
0.1 µF capacitor from the RESET pin to ground. This will hold
this signal low after the power is applied to reset the device. An
on-chip 20 kΩ resistor from RESET to DVCC will charge the
REV. A
Many systems, such as broadcast video, that handle numerous
analog signal channels have strict requirements for keeping the
various signals from influencing any of the others in the system.
Crosstalk is the term used to describe the coupling of the signals
of other nearby channels to a given channel.
When there are many signals in close proximity in a system, as
will undoubtedly be the case in a system that uses the AD8116,
the crosstalk issues can be quite complex. A good understanding
of the nature of crosstalk and some definition of terms is required
in order to specify a system that uses one or more AD8116s.
Types of Crosstalk
Crosstalk can be propagated by means of any of three methods.
These fall into the categories of electric field, magnetic field and
sharing of common impedances. This section will explain these
effects.
Every conductor can be both a radiator of electric fields and a
receiver of electric fields. The electric field crosstalk mechanism
occurs when the electric field created by the transmitter propagates
across a stray capacitance and couples with the receiver and
induces a voltage. This voltage is an unwanted crosstalk signal
in any channel that receives it.
Currents flowing in conductors create magnetic fields that circulate around the currents. These magnetic fields will then generate voltages in any other conductors whose paths they link. The
undesired induced voltages in these other channels are crosstalk
signals. The channels that crosstalk can be said to have a
mutual inductance that couples signals from one channel to
another.
The power supplies, grounds and other signal return paths of a
multichannel system are generally shared by the various channels.
When a current from one channel flows in one of these paths, a
voltage that is developed across the impedance becomes an
input crosstalk signal for other channels that share the common
impedance.
All these sources of crosstalk are vector quantities, so the
magnitudes cannot be simply added together to obtain the total
crosstalk. In fact, there are conditions where driving additional
circuits in parallel in a given configuration can actually reduce
the crosstalk.
Areas of Crosstalk
For a practical AD8116 circuit, it is required that it be mounted
to some sort of circuit board in order to connect it to power
supplies and measurement equipment. Great care has been
taken to create a characterization board (also available as an
evaluation board) that adds minimum crosstalk to the intrinsic
device. This, however, raises the issue that a system’s crosstalk
is a combination of the intrinsic crosstalk of the devices and the
circuit board to which they are mounted. It is important to try
–13–
AD8116
to separate these two areas of crosstalk when attempting to
minimize its effect.
In addition, crosstalk can occur among the input circuits to a
crosspoint and among the output circuits. Techniques will be
discussed for diagnosing which part of a system is contributing
to crosstalk.
Measuring Crosstalk
Crosstalk is measured by applying a signal to one or more channels
and measuring the relative strength of that signal on a desired
selected channel. The measurement is usually expressed as dB
down from the magnitude of the test signal. The crosstalk is
expressed by:
|XT| = 20 log10 (Asel(s)/Atest(s))
where s = jω is the Laplace transform variable, Asel(s) is the
amplitude of the crosstalk-induced signal in the selected channel
and Atest(s) is the amplitude of the test signal. It can be seen
that crosstalk is a function of frequency, but not a function of
the magnitude of the test signal. In addition, the crosstalk signal
will have a phase relative to the test signal associated with it.
A network analyzer is most commonly used to measure crosstalk
over a frequency range of interest. It can provide both magnitude and phase information about the crosstalk signal.
As a crosspoint system or device grows larger, the number
of theoretical crosstalk combinations and permutations can
become extremely large. For example, in the case of the 16 × 16
matrix of the AD8116, we can examine the number of crosstalk
terms that can be considered for a single channel, say IN00
input. IN00 is programmed to connect to one of the AD8116
outputs where the measurement can be made.
First, we can measure the crosstalk terms associated with driving a test signal into each of the other 15 inputs one at a time.
We can then measure the crosstalk terms associated with driving
a parallel test signal into all 15 other inputs taken two at a time
in all possible combinations; and then three at a time, etc., until,
finally, there is only one way to drive a test signal into all 15 other
inputs.
Each of these cases is legitimately different from the others and
might yield a unique value depending on the resolution of the
measurement system, but it is hardly practical to measure all
these terms and then to specify them. In addition, this describes
the crosstalk matrix for just one input channel. A similar crosstalk
matrix can be proposed for every other input. In addition, if
the possible combinations and permutations for connecting
inputs to the other (not used for measurement) outputs are
taken into consideration, the numbers rather quickly grow to
astronomical proportions. If a larger crosspoint array of multiple
AD8116s is constructed, the numbers grow larger still.
Obviously, some subset of all these cases must be selected to be
used as a guide for a practical measure of crosstalk. One common
term is “all hostile” crosstalk. This term means that all other
system channels are driven in parallel, and the crosstalk to the
selected channel is measured. In general, this will yield the
worst crosstalk number, but this is not always the case.
Input and Output Crosstalk
The flexible programming capability of the AD8116 can be used
to diagnose whether crosstalk is occurring more on the input
side or the output side. Some examples are illustrative. A given
input channel (IN07 in the middle for this example) can be
programmed to drive OUT07. The input to IN07 is just
terminated to ground and no signal is applied.
All the other inputs are driven in parallel with the same test
signal (practically provided by a distribution amplifier), but all
other outputs except OUT07 are disabled. Since grounded IN07
is programmed to drive OUT07, there should be no signal
present. Any signal that is present can be attributed to the other
15 hostile input signals, because no other outputs are driven.
Thus, this method measures the all-hostile input contribution to
crosstalk into IN07. Of course, the method can be used for
other input channels and combinations of hostile inputs.
For output crosstalk measurement, a single input channel is
driven (IN00 for example) and all outputs other than a given
output (IN07 in the middle) are programmed to connect to
IN00. OUT07 is programmed to connect to IN15 which is
terminated to ground. Thus OUT07 should not have a signal
present since it is listening to a quiet input. Any signal measured
at the OUT07 can be attributed to the output crosstalk of the
other 15 hostile outputs. Again, this method can be modified to
measure other channels and other crosspoint matrix combinations.
Effect of Impedances on Crosstalk
The input side crosstalk can be influenced by the output
impedance of the sources that drive the inputs. The lower the
impedance of the drive source, the lower the magnitude of the
crosstalk. The dominant crosstalk mechanism on the input
side is capacitive coupling. The high impedance inputs do not
have significant current flow to create magnetically induced
crosstalk.
From a circuit standpoint, the input crosstalk mechanism looks
like a capacitor coupling to a resistive load. For low frequencies
the magnitude of the crosstalk will be given by:
|XT| = 20 log10 [(RS CM) × s]
where RS is the source resistance, CM is the mutual capacitance
between the test signal circuit and the selected circuit, and s is
the Laplace transform variable.
From the equation it can be observed that this crosstalk mechanism has a high pass nature; it can be also minimized by reducing
the coupling capacitance of the input circuits and lowering
the output impedance of the drivers. If the input is driven from
a 75 Ω terminated cable, the input crosstalk can be reduced by
buffering this signal with a low output impedance buffer.
On the output side, the crosstalk can be reduced by driving a
lighter load. Although the AD8116 is specified with excellent
differential gain and phase when driving a standard 150 Ω video
load, the crosstalk will be higher than the minimum due to the
high output currents. These currents will induce crosstalk via
the mutual inductance of the output pins and bond wires of the
AD8116.
From a circuit standpoint, this output crosstalk mechanism
Other useful crosstalk measurements are those created by one
looks like a transformer with a mutual inductance between the
nearest neighbor or by the two nearest neighbors on either side.
windings that drives a load resistor. For low frequencies, the
These crosstalk measurements will generally be higher than
magnitude of the crosstalk is given by:
those of more distant channels, so they can serve as a worst case
measure for any other one-channel or two-channel crosstalk
|XT| = 20 log10 (Mxy × s/R L)
measurements.
REV. A
–14–
AD8116
where Mxy is the mutual inductance of output x to output y and
RL is the load resistance on the measured output. This crosstalk
mechanism can be minimized by keeping the mutual inductance
low and increasing RL . The mutual inductance can be kept low
by increasing the spacing of the conductors and minimizing
their parallel length.
One way to increase the load resistance is to buffer the outputs
with a high input impedance buffer as shown in Figure 27. The
AD8079AR is a dual buffer that can be strapped for a gain of +2
(B grade = +2.2). This offsets the halving of the signal when
driving a standard back-terminated video cable.
The input and output signals minimize crosstalk if they are
located between ground planes on layers above and below, and
separated by ground in between. Vias should be located as close
to the IC as possible to carry the inputs and outputs to the inner
layer. The only place the input and output signals surface is at
the input termination resistors and the output series back termination resistors. These signals should also be separated, to the
extent possible, as soon as they emerge from the IC package.
+5V
0.1␮F
The input of the buffer requires a path for bias current. This can
be provided by a 500 Ω to 5 kΩ resistor to ground. This resistor
also serves the purpose of biasing the outputs of the crosspoints
at zero volts when all the outputs are disabled.
OUTXX
G = +2
1
75⍀
8
1k⍀
75⍀
2
AD8079AR
AD8116
3
75⍀
5
4
OUTYY
G = +2
1k⍀
75⍀
–VS
OUTZZ
0.1␮F
+
10␮F
AD8116
PCB Layout
Extreme care must be exercised to minimize additional crosstalk
generated by the system circuit board(s). The areas that must be
carefully detailed are grounding, shielding, signal routing and
supply bypassing.
Each output is separated from its two neighboring outputs by
analog supply pins of either polarity. Each of these analog supply pins provides power to the output stages of only the two
adjacent outputs. These supply pins provide shielding, physical
separation and low impedance supply for the channel outputs.
Individual bypassing of each of these supply pins with a
0.01 µF chip capacitor directly to the ground plane minimizes
high frequency output crosstalk via the mechanism of sharing
common impedances.
10␮F
+VS
In addition, the load resistor actually lowers the crosstalk compared to the conditions of the AD8116 outputs driving a high
impedance (greater than 10 kΩ) or driving a video load (150 Ω).
This is because the electric field crosstalk that dominates in the
high impedance case has a phase of –90 degrees, while the magnetic field crosstalk that dominates in the video load case has a
phase of +90 degrees. With a 500 Ω to 5 kΩ load, the contributions from each of these is roughly equal, and there is some
cancellation of crosstalk due to the phase differences.
The packaging of the AD8116 is designed to help keep the
crosstalk to a minimum. Each input is separated from each
other’s input by an analog ground pin. All of these AGNDs
should be directly connected to the ground plane of the circuit
board. These ground pins provide shielding, low impedance
return paths and physical separation for the inputs. All of these
help to reduce crosstalk.
+
OUTWW
–5V
TO OTHER
AD8116 OUTPUTS
Figure 27. Buffering Wired OR Outputs with the AD8079
Evaluation Board
A four-layer evaluation board for the AD8116 is available. This
board has been carefully laid out and tested to demonstrate the
specified high speed performance of the device. Figure 28 shows
the schematic of the evaluation board. Figure 29 shows the
component side silk-screen. The layouts of the board’s four
layers are given in Figures 30, 31, 32 and 33.
The evaluation board package includes the following:
• Fully populated board with BNC-type connectors.
• Windows® based software for controlling the board from a
PC via the printer port.
• Custom cable to connect evaluation board to PC.
• Disk containing Gerber files of board layout.
Each output also has an on-chip compensation capacitor that
is individually tied to a package pin via the signals called
AGND00 through AGND15. This technique reduces crosstalk
by preventing the currents that flow in these paths from sharing
a common impedance on the IC and in the package pins. These
AGNDxx signals should all be connected directly to the ground
plane.
Windows is a registered trademark of Microsoft Corporation.
REV. A
–15–
AD8116
+
+
DGND
AGND
+
+
10␮F
10␮F
10␮F
10␮F
1
6
POWER SUPPLY
CONNECTOR*
0.1␮F
*6-PIN 0.100 CENTER HEADER
INPUT 07
75⍀
INPUT 08
75⍀
INPUT 09
75⍀
INPUT 10
75⍀
INPUT 11
75⍀
INPUT 12
75⍀
INPUT 13
75⍀
INPUT 14
75⍀
INPUT 15
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AGND
NC
AVCC
DGND
AVEE
DVEE
DVCC
CE
RESET
UPDATE
DATA OUT
CLK
DATA IN
OUT04
AVEE04/05
AGND
IN05
OUT05
AVCC05/06
AGND
IN06
OUT06
AD8116JST
AGND
AVEE06/07
IN07
OUT07
AVCC07/08
AGND
IN08
OUT08
AVEE08/09
AGND
IN09
OUT09
AVCC09/10
AGND
IN10
OUT10
AVEE10/11
AGND
IN11
OUT11
AVCC11/12
AGND
IN12
OUT12
AVEE12/13
AGND
IN13
OUT13
AVCC13/14
AGND
IN14
OUT14
AGND
IN15
75⍀
33
41
37
38
40
35
AVEE14/15
36
39
34
CLIP-ON
TEST POINTS
DIGITAL INTERFACE
CONNECTOR*
NC
6
42
43–45
0.01
␮F
NC
1
AGND
75⍀
14
IN04
NC
INPUT 06
13
AVCC03/04
AGND
AVCC
75⍀
12
OUT03
AVEE
INPUT 05
11
IN03
DVEE
75⍀
10
AVEE02/03
AGND
DVCC
INPUT 04
9
OUT02
IN02
RESET
75⍀
8
AVCC01/02
AGND
CLK
INPUT 03
7
OUT01
IN01
DATA OUT
75⍀
6
AVCC00
AVEE00/01
CE
INPUT 02
5
TO PINS 94,90,86,82
(AVEE)
97–104,
128
105–
112
116–
113–
118 120 115
AGND
UPDATE
75⍀
4
119
127
OUT00
DATA IN
INPUT 01
3
IN00
DGND
75⍀
2
AGND
INPUT 00
NC
NC
NC
NC
NC
NC
NC
0.01␮F
0.01␮F
AGND
TO PINS 96,92,88,84
(AVCC)
0.01␮F 0.01␮F
126 125 124 123 122 121
1
0.1␮F
CLIP-ON TEST POINTS
MOLEX PART NR. 22-23-2061
MATING CONNECTOR
MOLEX PART NR. 22-01-03067
OUT15
NC
95
0.01␮F
0.01␮F
0.01␮F
0.01␮F
0.01µF
0.01␮F
0.01␮F
0.01␮F
0.01␮F
0.01␮F
0.01␮F
0.01␮F
0.01␮F
0.01␮F
0.01␮F
OUTPUT 07
75⍀
OUTPUT 08
75⍀
OUTPUT 09
75⍀
OUTPUT 10
75⍀
OUTPUT 11
75⍀
OUTPUT 12
75⍀
OUTPUT 13
75⍀
OUTPUT 14
75⍀
OUTPUT 15
AVEE
66
65
75⍀
AVCC
68
67
OUTPUT 06
AVEE
70
69
75⍀
AVCC
72
71
OUTPUT 05
AVEE
74
73
75⍀
AVCC
76
75
OUTPUT 04
AVEE
78
77
75⍀
AVCC
80
79
OUTPUT 03
AVEE
82
81
75⍀
AVCC
84
83
OUTPUT 02
AVEE
86
85
75⍀
AVCC
88
87
OUTPUT 01
AVEE
90
89
75⍀
AVCC
92
91
OUTPUT 00
AVEE
94
93
75⍀
0.01␮F
AVCC
49–
46–48
0.01 55 56–63
␮F
AVEE AVCC
AVCC
96
64
AVCC
0.01
␮F
TO PINS
78,74,70,66
(AVEE)
0.1␮F
TO PINS
80,76,72,68
(AVCC)
0.1␮F
NC = NO CONNECT
Figure 28. Evaluation Board Schematic
–16–
REV. A
AD8116
Figure 29. Component Side Silkscreen
REV. A
–17–
AD8116
Figure 30. Board Layout (Top Layer)
–18–
REV. A
AD8116
Figure 31. Board Layout (Signal Layer)
REV. A
–19–
AD8116
Figure 32. Board Layout (Power Layer)
–20–
REV. A
AD8116
Figure 33. Board Layout (Bottom Layer)
REV. A
–21–
AD8116
Optimized for video applications, all signal inputs and outputs
are terminated with 75 Ω resistors. Figure 34 shows a crosssection of one of the input or output tracks along with the arrangement of the PCB layers. It should be noted that unused
regions of the four layers are filled up with ground planes. As a
result, the input and output traces, in addition to having controlled impedances, are well shielded.
The four power supply pins AVCC, DVCC, AVEE and DVEE
should be connected to good quality, low noise, ± 5 V supplies.
Where the same ± 5 V power supplies are used for analog and
digital, separate cables should be run for the power supply to the
evaluation board’s analog and digital power supply pins.
w = 0.008"
(0.2mm)
a = 0.008"
(0.2mm)
t = 0.00135" (0.0343mm)
TOP LAYER
b = 0.0132"
(0.335mm)
SIGNAL LAYER
c = 0.028"
(0.714mm)
POWER LAYER
d = 0.0132"
(0.335mm)
BOTTOM LAYER
Figure 34. Cross Section of Input and Output Traces
The board has 32 BNC type connectors: 16 inputs and 16 outputs.
The connectors are arranged in two crescents around the device.
As can be seen from Figure 31, this results in all sixteen input
signal traces and all sixteen signal output traces having the same
length. This is useful in tests such as All-Hostile Crosstalk
where the phase relationship and delay between signals needs to
be maintained from input to output.
As can be seen in Figure 35, there is extensive power supply
decoupling on the evaluation board. Figure 35 shows the
location of all the decoupling capacitors relative to the AD8116’s
pins. Four large 10 µF capacitors are located near the evaluation board’s power supply connection terminals. These decouple the AVCC, DVCC, AVEE and DVEE supplies. Because
it is required that the voltage difference between DGND and
AGND never exceed 0.7 V, these grounds are connected by
two antiparallel diodes. On the output side of the device (Pin 65
to Pin 96), the sixteen output pins are interleaved with the
AVCC and AVEE power supply pins. Each of these pins is
locally decoupled with a 0.01 µF capacitor. These pins are also
decoupled in groups of four with 0.1 µF capacitors. Due to
space constraints the power supply Pins 34 (DVCC) and 42
(DVEE) are neither connected nor decoupled. These pins are,
however, internally connected to DVCC and DVEE (Pins 127
and 119).
As a general rule, each power supply pin (or group of adjacent
power supply pins) should be locally decoupled with a 0.01 µF
capacitor. If there is a space constraint, it is more important to
decouple analog power supply pins before digital power supply
pins. A 0.1 µF capacitor, located reasonably close to the pins,
can be used to decouple a number of power supply pins. Finally
a 10 µF capacitor should be used to decouple power supplies as
they come on to the board.
–22–
REV. A
AD8116
DVCC
10␮F
128
DVEE
AVEE
AVCC
10␮F
127
10␮F
10␮F
119
113
0.1␮F
97
1
*
*
*
96
*
*
*
*
*
*
0.1␮F
*
*
*
*
*
*
*
*
0.1␮F
*
*
0.1␮F
*
*
65
32
33
34
NC
(DVCC)
42
48
NC
(DVEE)
64
*
*
* 0.01␮F
NC = NO CONNECT
Figure 35. Detail of Decoupling on Evaluation Board
REV. A
–23–
AD8116
Controlling the Evaluation Board from a PC
The evaluation board include Windows-based control software
and a custom cable that connects the board’s digital interface
to the printer port of the PC. The wiring of this cable is shown
in Figure 36. The software requires Windows 3.1 or later to
operate. To install the software, insert the disk labeled “Disk #1
of 2” in the PC and run the file called SETUP.EXE. Additional
installation instructions will be given on-screen. Before beginning installation, it is important to terminate any other Windows applications that are running.
RESET
MOLEX 0.100" CENTER
CRIMP TERMINAL HOUSING
D-SUB 25 PIN
(MALE)
1
14
1
CLK
CE
can be connected with one or more outputs by simply clicking
on the appropriate radio buttons in the 16 × 16 on-screen array.
Each time a button is clicked on, the software automatically
sends and latches the required 80-bit data stream to the
evaluation board. An output can be turned off by clicking the
appropriate button in the Off column. To turn off all outputs,
click on RESET.
The software offers volatile and nonvolatile storage of configurations. For volatile storage, up to two configurations can be
stored and recalled using the Memory 1 and Memory 2 Buffers.
These function in an identical fashion to the memory on a
pocket calculator. For nonvolatile storage of a configuration, the
Save Setup and Load Setup functions can be used. This stores
the configuration as a data file on disk.
Overshoot on PC Printer Ports’ Data Lines
UPDATE
DATA IN
The data lines on some printer ports have excessive overshoot.
Overshoot on the pin that is used as the serial clock (Pin 6 on
the D-Sub-25 connector) can cause communication problems.
This overshoot can be eliminated by connecting a capacitor
from the CLK line on the evaluation board to ground. A pad
has been provided on the solder-side of the evaluation board to
allow this capacitor to be soldered into place. Depending upon
the overshoot from the printer port, this capacitor may need to
be as large as 0.01 µF.
6
DGND
MOLEX
D-SUB-25 TERMINAL HOUSING SIGNAL
2
3
4
5
6
25
EVALUATION BOARD
3
1
4
5
2
6
CE
RESET
UPDATE
DATA IN
CLK
DGND
25
13
PC
Figure 36. Evaluation Board-PC Connection Cable
When you launch the crosspoint control software, you will be
asked to select the printer port you are using. Most modern PCs
have only one printer port, usually called LPT1; however, some
laptop computers use the PRN port.
Figure 37 shows the main screen of the control software in its
initial reset state (all outputs off). Using the mouse, any input
–24–
REV. A
AD8116
Figure 37. Screen Display of Control Software
REV. A
–25–
AD8116
OUTLINE DIMENSIONS
Dimensions shown in millimeters and (inches).
Metric measurements are not rounded. English measurements are rounded.
128-Lead Plastic LQFP
(ST-128A)
0.630 (16.00) BSC
0.063 (1.60)
TYP
C2441a–2–5/99
0.551 (14.00) BSC
0.488 (12.40) BSC
0.030 (0.75)
0.018 (0.45)
97
96
128
1
STANDOFF
0.003 (0.08)
MAX
65
64
32
33
0.006 (0.15)
0.002 (0.05)
7°
0°
0.016 (0.40)
BSC
0.009 (0.23)
0.005 (0.13)
PRINTED IN U.S.A.
0.057 (1.45)
0.053 (1.35)
0.630 (16.00) BSC
TOP VIEW
(PINS DOWN)
0.551 (14.00) BSC
0.488 (12.40) BSC
SEATING
PLANE
–26–
REV. A
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