Mitsubishi M56692FP Bi-cmos & dmos 32bit serial-input latched driver Datasheet

MITSUBISHI <CONTROL / DRIVER IC>
M56692FP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
DESCRIPTION
The M56692FP is a semiconductor integrated circuit that has a
PIN CONFIGURATION (TOP VIEW)
built-in, 32-bit shift register and a latch of CMOS structure with
23 HVO12
14 HVO 3
43
13 HVO 2
44
12 HVO 1
9
15 HVO 4
42
VH 10
PGND 11
Vacuum Fluorescent Display GRID DRIVER
24 HVO13
25 HVO14
26 HVO15
27 HVO16
28 HVO17
29 HVO18
16 HVO 5
41
VH
SOUT(SIN)
VDD
F/R
LGND
CLK
LAT
BLK
SIN(SOUT)
APPLICATION
17 HVO 6
40
1
● Operating temperature: -40 – 85°C
18 HVO 7
M56692FP
39
8
● Driver supply voltage: VH=90V
19 HVO 8
38
7
● Latch circuit included for each stage.
20 HVO 9
37
6
● Cascade connections possible through serial output.
21 HVO10
36
5
● Bidirectional shift register (controlled at F/R terminal)
22 HVO11
4
● Serial input - serial/parallel output
34
35
3
FEATURES
2
HVO23
HVO24
HVO25
HVO26
HVO27
HVO28
HVO29
HVO30
HVO31
HVO32
PGND
30 HVO19
Employed are Bi-CMOS and high pressure proof DMOS
processing technology.
31 HVO20
33 HVO22
parallel output driver of high pressure proof DMOS structure.
32 HVO21
serial input and serial/parallel output, and a 32-bit totem-pole-type
Outline 44P6N-A
BLOCK DIAGRAM
HVO 1
12
HVO 2
13
HVO 3
14
HVO30
41
HVO31
HVO32
42
43
Output
protect
circuit
VDD
1
3
11
BLK 8
LGND
5
LAT
7
SIN
(SOUT)
9
CLK
3-58
VH
10
PGND
44
Q
Q
Q
Q
Q
Q
L D
L D
L D
L D
L D
L D
D Q
D Q
D Q
D Q
D Q
D Q
T
T
T
T
T
T
2
SOUT
(SIN)
4
F/R
6
MITSUBISHI <CONTROL / DRIVER IC>
M56692FP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
Serial-output SOUT is used by connecting to the next stage
M56692FP SIN when more than one M56692FP is used to expand
bits in the series.
In accordance with truth table 2, parallel output allows the latch to
pass data through if LAT input is turned to “H”, and data to be
retained if LAT input is turned to “L”. Driver output HVOn allows
data from the latch to be output if BLK input is turned to “L”, and “L”
to be output if BLK input is turned to “H” irrespective of data from
the latch.
FUNCTION
The M56692FP comprises a 32 bit bidirectional shift register, a 32
bit latch, and a parallel output HVO 1 – HVO32 connected to its
output.
In accordance with truth table 1, the data transfer direction of shift
register depends upon F/R input, and F/R being at “H” or open
allows pin 9 to turn to SIN and pin 2 to turn to SOUT, and F/R
being at “L” allows pin 2 to turn to SIN and pin 9 to turn to SOUT,
permitting data transfer from SIN to SOUT, respectively.
Inputting data to SIN and clock pulse to CLK allows SIN signal to
be put into the internal shift register when the clock changes from
“H” to “L”, and shift register data to be shifted sequentially.
TRUTH TABLE
Truth table 1. Shift register section
Input
Input/output
Shift register
F/R
CLK
SIN(SOUT)
SOUT(SIN)
H
↓
IN
OUT
DATA is shifted.
H
H or L
IN
OUT
No changes.
L
↓
OUT
IN
DATA is shifted.
L
H or L
OUT
IN
No changes.
Truth table 2. Latch and driver sections
Dn
LAT
BLK
HVOn
X
X
H
Output all “L”
H
H
L
H
L
H
L
L
X
L
L
Latch’s data output.
Dn=nth bit DFF retention data
HVOn=nth bit driver output
L = “L” level
H = “H” level
X = “L” level or “H” level
PIN FUNCTION DESCRIPTION
Pin name
VDD
LGND
VH
PGND
CLK
SIN
SOUT
LAT
BLK
F/R
HVO1–32
Function
Logic stage supply voltage
Logic stage ground
Output stage supply voltage
Output stage supply ground
Clock input for the internal shift resister. The data enter the internal shift resisters and the data in the shift registers will be
shifted in order by High to Low change of the clock.
Serial data input
Serial data output
Latch input. When the LATCH is set to “H”, the data in the shift resister will enter the each latch circuit.
When the LATCH input is set to “L”, the data will be held.
Enable input for output control. When the BLK input is set to “L”, data in the latch circuit will appear at outputs.
When the BLK input is set to “H”, all outputs will be set to “L”.
Direction Control for the internal shift resister
Output driver (push-pull)
ABSOLUTE MAXIMUM RATINGS (Ta=25°C, unless otherwise noted)
Symbol
VDD
VH
VI
VO
VHVO
Pd
Tstg
Parameter
Logic stage supply voltage
Output stage supply voltage
Logic inputs voltage
Logic output voltage
Output voltage
Power dissipation range
Storage temperature range
Conditions
Data output
High supply voltage output pin
Ta ≤ 25°C
Ratings
-0.3 – 7
-0.3 – 90
-0.3 – VDD+0.3
-0.3 – VDD+0.3
-0.3 – VH
850
-55 – 150
Unit
V
V
V
V
V
mW
°C
MITSUBISHI <CONTROL / DRIVER IC>
M56692FP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
VH
Topr
Parameter
Supply voltage
Supply voltage
Operating temperature
Conditions
Ratings
4–6
40 – 90
-40 – 85
Unit
V
V
°C
ELECTRICAL CHARACTERISTICS (VDD=5V, VH=80V and Ta=25°C, unless otherwise noted)
Symbol
Parameter
Test conditions
Supply current 1
No load
IH
Supply current 2
IIH
“H” input current
Output all “L”, no load
1 bit “H”, no load
VIH=5V input pin
IIL
“L” input current
VIL = 0V
IDD
VHVOH
VHVOL
VOH
VOL
IHVOH
IHVOL
VTH
VTL
SIN, LAT, CLK
BLK, F/R
IHVOH = -50mA
IHVOL = 10mA
IOH = -0.1mA
IOL = 0.1mA
Duty cycle ≤ 2.5%*
Driver output voltage
Logic output voltage
“H” output current
“L” output current
Min.
70
4.5
Output protect operating voltage
Limits
Typ.
0.4
0
Max.
2
1
0.4
0
0
-250
75.5
0.5
4.9
0.1
1
1
-1
-500
-50
10
3.3
3.0
-100
20
2.5
0.4
Unit
mA
mA
mA
µA
µA
µA
V
V
mA
mA
V
V
* Maximum numbers of Outputs High State are two at the same time.
SWITCHING CHARACTERISTICS (VDD=5V, VH=80V and Ta=25°C, unless otherwise noted)
Symbol
fCLK
t PLH(SO)
t PHL(SO)
t PLH(OUT)
t PHL(OUT)
trout
tfout
Parameter
Test conditions
Min.
Limits
Typ.
Duty = 45 – 55%
Clock frequency
Logic output propagation time
90
60
95
70
35
65
CL = 15pF
Driver output propagation time
RO = 220KΩ
CO = 50pF
Driver output rise and fall time
Max.
8
180
180
TEST CIRCUIT
INPUT
VDD
VH
SOUT
PG
CL
DUT
HVOn
50Ω
CO
RO
(1) Characteristics of pulse generator (PG)
tr≤20ns
tf≤20ns
(2) Capacitance CL includes connection
floating capacitance and probe input
capacitance.
: RO=220KΩ
: CO=50pF
Unit
MHz
ns
ns
ns
ns
ns
ns
MITSUBISHI <CONTROL / DRIVER IC>
M56692FP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
TIMING WAVEFORM
1/fmax
CLK
50%
50%
SIN
50%
50%
50%
th
trso
tsu
tfso
SOUT
90%
50%
10%
tPHL(SO)
BLK
90%
50%
10%
tPLH(SO)
50%
50%
trOUT
HVOn
10%
tPLH(OUT)
90%
50%
tfOUT
90%
50%
tPHL(OUT)
10%
MITSUBISHI <CONTROL / DRIVER IC>
M56692FP
Bi-CMOS & DMOS 32BIT SERIAL-INPUT LATCHED DRIVER
TYPICAL CHARACTERISTICS
Thermal derating
Driver output VON–IOH
1.0
Ta=25°C
-100
0.8
“H” output current IOH(mA)
Power dissipation Pd(W)
Ta=-40°C
0.6
0.4
0.2
-60
-40
-20
0.0
0
0
25
50
75
100 125
Temperature Ta (°C)
150
0
2
6
8
10
12
Duty cycle vs Permissible
output current
100
100
1
90
90
80
70
60
4
50
40
8
30
20
Output current IOH(mA)
2
16
10
20
40
60
80
1
70
60
2
50
40
4
30
20
8
16
0
32
0
80
10
24
0
100
32
0
20
Duty cycle (%)
Note
4
“H” output ON voltage VON (V)
Duty cycle vs Permissible
output current
Output current IOH(mA)
Ta=85°C
-80
• Ta=25°C
• Repeated frequency>100Hz
• Figure in the circle represents the number of
concurrently operating output circuits.
• Current value denotes a numerical value per circuit.
Note
40
60
Duty cycle (%)
80
24
100
• Ta=85°C
• Repeated frequency>100Hz
• Figure in the circle represents the number of
concurrently operating circuits.
• Current value denotes a numerical value per circuit.
(Note) 1. VDD=5V and VH=80V unless otherwise noted.
2. Thermal derating curve represents that of an individual IC unit.
3. Allowable duty cycle output curve represents that when a standard
substrate is mounted. (Standard substrate: 70x70x1.6mm glass epoxy)
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