AKM AK93C95A 16k / 32k / 64kbit serial cmos eeprom Datasheet

ASAHI KASEI
[AK93C85A/95A/10A]
AK93C85A / 95A / 10A
16K / 32K / 64Kbit Serial CMOS EEPROM
Features
ADVANCED CMOS EEPROM TECHNOLOGY
READ/WRITE NON-VOLATILE MEMORY
WIDE VCC OPERATION : VCC = 1.8V to 5.5V
AK93C85A ・・16384 bits, 1024 x 16 organization
AK93C95A ・・32768 bits, 2048 x 16 organization
AK93C10A ・・65536 bits, 4096 x 16 organization
SERIAL INTERFACE
- Interfaces with popular microcontrollers and standard microprocessors
LOW POWER CONSUMPTION
- 0.4mA Max. Read Operation
- 0.8µA Max. Standby
High Reliability
- Endurance
: 100K cycles
- Data Retention : 10 years
Automatic address increment (READ)
Automatic write cycle time-out with auto-ERASE (Max. 8ms: VCC=4.5V to 5.5V)
Busy/Ready status signal
Software controlled write protection
IDEAL FOR LOW DENSITY DATA STORAGE
- Low cost, space saving, 8-pin package (SOP, SSOP)
DO
DATA
REGISTER
DI
INSTRUCTION
REGISTER
INSTRUCTION
DECODE,
CONTROL
AND
CLOCK
GENERATION
16
ADD.
BUFFERS
R/W AMPS
AND
AUTO ERASE
DECODER
16
EEPROM
93C85A=16384bit
93C95A=32768bit
93C10A=65536bit
CS
VPP SW
SK
VREF
VPP
GENERATOR
Block Diagram
DAM02E-03
2004/05
- 1 -
ASAHI KASEI
[AK93C85A/95A/10A]
General Description
The AK93C85A/95A/10A is a 16384/32768/65536-bit serial CMOS EEPROM divided into
1024/2048/4096 registers of 16 bits each. The AK93C85A/95A/10A has 4 instructions such as
READ, WRITE, EWEN and EWDS. Those instructions control the AK93C85A/95A/10A.
The AK93C85A/95A/10A can operate full function under wide operating voltage range from 1.8V to
5.5V. The charge up circuit is integrated for high voltage generation that is used for write
operation.
A serial interface of AK93C85A/95A/10A, consisting of chip select (CS), serial clock (SK), data-in
(DI) and data-out (DO), can easily be controlled by popular microcontrollers or standard
microprocessors. AK93C85A/95A/10A takes in the write data from data input pin (DI) to a register
synchronously with rising edge of input pulse of serial clock pin (SK). And at read operation,
AK93C85A/95A/10A takes out the read data from a register to data output pin (DO) synchronously
with rising edge of SK.
The DO pin is usually in high impedance state. The DO pin outputs "L" or "H" in case of data
output or Busy/Ready signal output.
x Software controlled write protection
When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable
state. In the ERASE/WRITE disable state, execution of WRITE instruction is disabled. Before
WRITE instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable
state continues until EWDS instruction is executed or VCC is removed from the part.
Execution of a read instruction is independent of both EWEN and EWDS instructions.
x Busy/Ready status signal
After a write instruction, the DO output serves as a Busy/Ready status indicator. After the falling
edge of the CS initiates the self-timed programming cycle, the DO indicates the Busy/Ready status
of the chip if the CS is brought high after a minimum of 250ns (tCS). DO=logical "0" indicates that
programming is still in progress. DO=logical "1" indicates that the register at the address specified
in the instruction has been written with the new data pattern contained in the instruction and the part
is ready for a next instruction.
The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO
output goes into a high impedance state.
The Busy/Ready signal outputs until a start bit (Logic"1") of the next instruction is given to the part.
„ Type of Products
Model
AK93C85AM
AK93C95AF
AK93C10AF
Memory size
16K bits
32K bits
64K bits
Temp. Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
DAM02E-03
VCC
1.8V to 5.5V
1.8V to 5.5V
1.8V to 5.5V
Package
8pin Plastic SSOP
8pin Plastic SOP
8pin Plastic SOP
2004/05
- 2 -
ASAHI KASEI
[AK93C85A/95A/10A]
Pin Arrangement
AK93C85AM
1
2
3
4
CS
SK
DI
DO
VCC
NC
NC
GND
8
7
6
5
8pin SSOP
AK93C95AF/10AF
CS
1
8
VCC
SK
2
7
NC
DI
3
6
NC
DO
4
5
GND
8pin SOP
Pin Name
Function
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
VCC
Power Supply
NC
Not Connected
*1
*1: Please Open NC pin.
DAM02E-03
2004/05
- 3 -
ASAHI KASEI
[AK93C85A/95A/10A]
Functional Description
The AK93C85A/95A/10A has 4 instructions such as READ, WRITE, EWEN and EWDS. A valid
instruction consists of a Start Bit (Logic"1"), the appropriate Op Code and the desired memory
Address location.
The CS pin must be brought low for a minimum of 250ns (tCS) between each instruction when the
instruction is continuously executed.
Instructi Start Op
on
Bit
Code
READ
01
10
WRITE
01
01
EWEN
01
00
EWDS
01
00
WRAL
01
00
Address
Data
Comments
A9-A0
A9-A0
11XXXXXXXX
00XXXXXXXX
01XXXXXXXX
D15-D0
D15-D0
Reads data stored in memory, at specified address.
Writes register.
Write enable must precede all programming modes.
Disables all programming instructions.
D15-D0
Writes all registers.
X: Don't care
table1. Instruction Set for the AK93C85A
Instructi Start Op
on
Bit
Code
READ
1
10
WRITE
1
01
EWEN
1
00
EWDS
1
00
WRAL
1
00
Address
Data
Comments
A10-A0
A10-A0
11XXXXXXXXX
00XXXXXXXXX
01XXXXXXXXX
D15-D0
D15-D0
Reads data stored in memory, at specified address.
Writes register.
Write enable must precede all programming modes.
Disables all programming instructions.
D15-D0
Writes all registers.
X: Don't care
table2. Instruction Set for the AK93C95A
Instructi Start Op
Address
on
Bit
Code
READ
1
10
A11-A0
WRITE
1
01
A11-A0
EWEN
1
00 11XXXXXXXXXX
EWDS
1
00 00XXXXXXXXXX
WRAL
1
00 01XXXXXXXXXX
Data
Comments
D15-D0
D15-D0
Reads data stored in memory, at specified address.
Writes register.
Write enable must precede all programming modes.
Disables all programming instructions.
D15-D0
Writes all registers.
X: Don't care
table3. Instruction Set for the AK93C10A
(Note) x The WRAL instruction are used for factory function test only.
User can't use the WRAL instruction.
x The AK93C85A perceives the start bit in the logic"01" and also "001".
x The AK93C95A/10A perceives the start bit in the logic"1" and also "01".
DAM02E-03
2004/05
- 4 -
ASAHI KASEI
[AK93C85A/95A/10A]
WRITE
The write instruction is followed by 16 bits of data to be written into the specified address.
AK93C85A: After the last bit of data is put on the DI pin, the CS pin must be brought low before the
next rising edge of the SK clock. This falling edge of the CS initiates the self-timed programming
cycle. The DO indicates the Busy/Ready status of the chip if the CS is brought high after a
minimum of 250ns (Tcs).
AK93C95A/10A: The self-timed programming cycle is initiated on the rising edge of the SK clock as
the last data bit (D0) is clocked in. The DO indicates the Busy/Ready status of the chip after the
self-timed programming cycle is initiated.
The Busy/Ready status indicator is only valid when CS is active (high). When CS is low, the DO
output goes into a high impedance state. The Busy/Ready signal outputs until a start bit (Logic"1")
of the next instruction is given to the part.
DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the
register at the address specified in the instruction has been written with the new data pattern
contained in the instruction and the part is ready for a next instruction.
CS
SK
DI
1
0
0
1
2
0
Start Bit
3
1
4
A9
5
A8
12
A1
13
A0
14
D15
15
D14
27
D2
28
D1
29
tCS
D0
Op code
Busy
Hi-Z
DO
Ready
AK93C85A output a logic "1" (Ready status),
if previous instruction is WRITE.
tE/W
WRITE (AK93C85A)
CS
SK
DI
1
0
0
1
2
0
Start Bit
3
1
4
A10
5
A9
13
A1
14
A0
15
D15
16
D14
28
D2
29
D1
30
D0
Op code
Hi-Z
DO
Busy
Ready
AK93C95A output a logic "1" (Ready status),
if previous instruction is WRITE.
tE/W
WRITE (AK93C95A)
CS
SK
DI
1
0
0
1
Start Bit
DO
2
0
3
1
4
5
A11
A10
14
A1
15
A0
16
D15
17
D14
29
D2
30
D1
31
D0
Op code
Hi-Z
Busy
Ready
AK93C10A output a logic "1" (Ready status),
if previous instruction is WRITE.
tE/W
WRITE (AK93C10A)
DAM02E-03
2004/05
- 5 -
ASAHI KASEI
[AK93C85A/95A/10A]
READ
The read instruction is the only instruction which outputs serial data on the DO pin.
Following the Start bit, first Op code and address are decoded, then the data from the selected
memory location is available at the DO pin. A dummy bit (logical "0") precedes the 16-bit data from
the selected memory location. The output data changes are synchronized with the rising edges of
the serial clock (SK).
The data in the next address can be read sequentially by continuing to provide clock. The address
automatically cycles to the next higher address after the 16bit data shifted out.
AK93C85A・・When the highest address is reached ($3FF), the address counter rolls over
to address $000 allowing the read cycle to be continued indefinitely.
AK93C95A・・When the highest address is reached ($7FF), the address counter rolls over
to address $000 allowing the read cycle to be continued indefinitely.
AK93C10A・・When the highest address is reached ($FFF), the address counter rolls over
to address $000 allowing the read cycle to be continued indefinitely.
CS
SK
DI
0
0
1
1
2
1
Start bit
3
0
4
A9
5
A8
12
A1
13
14
15
29
30
44
45
A0
Op code
Hi-Z
DO
0
D15 D14
D0
Dummy
address[A9–A0]
Bit
AK93C85A output a logic "1" (Ready status),
if previous instruction is WRITE.
D15
D1
D0
address[A9–A0]+1
READ (AK93C85A)
CS
SK
DI
0
0
1
1
2
1
Start bit
3
0
4
A10
5
A9
13
A1
14
15
16
30
31
45
46
A0
Op code
Hi-Z
DO
0
D15 D14
D0
Dummy
address[A10–A0]
Bit
AK93C95A output a logic "1" (Ready status),
if previous instruction is WRITE.
D15
D1
D0
address[A10–A0]+1
READ (AK93C95A)
CS
SK
DI
0
0
1
1
Start bit
DO
2
1
3
0
4
5
A11
A10
14
A1
15
16
17
31
32
46
47
A0
Op code
Hi-Z
AK93C10A output a logic "1" (Ready status),
if previous instruction is WRITE.
0
D15 D14
D0
Dummy
address[A11–A0]
Bit
D15
D1
D0
address[A11–A0]+1
READ (AK93C10A)
DAM02E-03
2004/05
- 6 -
ASAHI KASEI
[AK93C85A/95A/10A]
EWEN / EWDS
When VCC is applied to the part, the part automatically powers up in the ERASE/WRITE Disable
state. In the ERASE/WRITE disable state, execution of WRITE instruction is disable. Before
WRITE instruction is executed, EWEN instruction must be executed. The ERASE/WRITE enable
state continues until EWDS instruction is executed or VCC is removed from the part.
Execution of a read instruction is independent of both EWEN and EWDS instructions.
CS
SK
DI
0
0
1
1
2
0
3
4
5
0
6
X
7
8
X
X
9
X
10
X
11
X
12
X
13
X
EWEN=11
EWDS=00
Start bit
Hi-Z
DO
AK93C85A output a logic "1" (Ready status),
if previous instruction is WRITE.
X: Don't care
EWEN / EWDS (AK93C85A)
CS
SK
DI
0
0
1
1
2
0
3
4
5
0
6
X
7
8
X
X
9
X
10
X
11
X
12
X
13
X
14
X
EWEN=11
EWDS=00
Start bit
Hi-Z
DO
AK93C95A output a logic "1" (Ready status),
if previous instruction is WRITE.
X: Don't care
EWEN / EWDS (AK93C95A)
CS
SK
DI
0
0
1
1
Start bit
DO
2
0
3
4
5
0
6
X
7
X
8
X
9
X
10
X
11
X
12
X
13
X
14
X
15
X
EWEN=11
EWDS=00
Hi-Z
AK93C10A output a logic "1" (Ready status),
if previous instruction is WRITE.
X: Don't care
EWEN / EWDS (AK93C10A)
DAM02E-03
2004/05
- 7 -
ASAHI KASEI
[AK93C85A/95A/10A]
Absolute Maximum Ratings
Parameter
Power Supply
All Input Voltages
with Respect to Ground
Ambient storage temperature
Symbol
VCC
VIO
Min
-0.6
-0.6
Max
+7.0
VCC+0.6
Unit
V
V
Tst
-65
+150
°C
Stress above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of the specification is not implied. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
Recommended Operating Condition
Parameter
Power Supply
Ambient Operating Temperature
Symbol
VCC
Ta
DAM02E-03
Min
1.8
-40
Max
5.5
+85
Unit
V
°C
2004/05
- 8 -
ASAHI KASEI
[AK93C85A/95A/10A]
Electrical Characteristics
(1) D.C. ELECTRICAL CHARACTERISTICS
( 1.8V ≤ VCC ≤ 5.5V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified )
Parameter
VCC=5.5V, tSKP=1.0µs, *1
Max.
5.5
Unit
mA
ICC2
VCC=1.8V, tSKP=4.0µs, *1
3.0
mA
Current Dissipation
ICC3
VCC=5.5V, tSKP=1.0µs, *1
0.4
mA
(READ, EWEN, EWDS)
ICC4
VCC=1.8V, tSKP=4.0µs, *1
0.1
mA
Current Dissipation
(Standby)
ICCSB
VCC=5.5V
0.8
µA
Input High Voltage
VIH
VCC + 0.5
V
Input Low Voltage
VIL
0.2 x VCC
V
Output High Voltage
VOH1
2.5V ≤ VCC ≤ 5.5V
IOH=-0.1mA
0.8 x VCC
V
VOH2
1.8V ≤ VCC < 2.5V
IOH=-0.1mA
0.8 x VCC
V
VOL1
2.5V ≤ VCC ≤ 5.5V
IOL=1.0mA
0.4
V
VOL2
1.8V ≤ VCC < 2.5V
IOL=0.1mA
0.4
V
Input Leakage
ILI
VCC=5.5V, VIN=5.5V
±1.0
µA
Output Leakage
ILO
VCC=5.5V,
VOUT=5.5V, CS=GND
±1.0
µA
Current Dissipation
(WRITE)
Output Low Voltage
Symbol
ICC1
Condition
Min.
*2
0.8 x VCC
-0.1
*1 : VIN=VIH/VIL, DO=Open
*2 : VIN=VCC/GND, CS=GND, DO=Open
DAM02E-03
2004/05
- 9 -
ASAHI KASEI
[AK93C85A/95A/10A]
(2) A.C. ELECTRICAL CHARACTERISTICS
( 1.8V ≤ VCC ≤ 5.5V, -40°C ≤ Ta ≤ 85°C, unless otherwise specified )
Parameter
SK Cycle Time
SK Pulse Width
Symbol
tSKP1
Condition
4.5V ≤ VCC ≤ 5.5V
Min.
1.0
Max.
Unit
tSKP2
2.0V ≤ VCC < 4.5V
2.0
µs
tSKP3
1.8V ≤ VCC < 2.0V
4.0
µs
tSKW1
4.5V ≤ VCC ≤ 5.5V
500
ns
tSKW2
2.0V ≤ VCC < 4.5V
1.0
µs
tSKW3
1.8V ≤ VCC < 2.0V
2.0
µs
µs
CS Setup Time
tCSS
100
ns
CS Hold Time
tCSH
0
ns
Data Setup Time
tDIS
200
ns
Data Hold Time
tDIH
200
ns
tPD1
4.5V ≤ VCC ≤ 5.5V
500
ns
tPD2
2.0V ≤ VCC < 4.5V
1.0
µs
tPD3
1.8V ≤ VCC < 2.0V
2.0
µs
Selftimed
Programming Time
tE/W1
4.5V ≤ VCC ≤ 5.5V
8
ms
tE/W2
1.8V ≤ VCC < 4.5V
10
ms
Min CS Low Time
tCS
CS to Status Valid1
tSV
CL=100pF
500
ns
CS to Status Valid2
tSVV
CL=100pF
1000
ns
CS to Output High-Z
tOZ1
2.0V ≤ VCC ≤ 5.5V
100
ns
tOZ2
1.8V ≤ VCC < 2.0V
250
ns
Output delay
*3
250
ns
*3 : CL=100pF
DAM02E-03
2004/05
- 10 -
ASAHI KASEI
[AK93C85A/95A/10A]
Synchronous Data timing
tCS
CS
tCSS
tSKW
tSKW
tSKP
SK
tDIS
DI
0
tDIH
1
tSV
Hi-Z
DO
AK93C85A/95A/10A output a logical "1" (Ready status),
if previous instruction is WRITE.
The Start of Instruction
CS
tCSH
SK
DI
tPD
DO
D3
tPD
D2
tPD
D1
tOZ
D0
Hi-Z
The End of Instruction
DAM02E-03
2004/05
- 11 -
ASAHI KASEI
[AK93C85A/95A/10A]
tCS
CS
tCSH
SK
tDIS
DI
tDIH
D1
D0
tSV
Hi-Z
DO
Busy
Ready
tE/W
Busy/Ready Signal Output (AK93C85A)
CS
SK
tDIS
DI
tDIH
D1
D0
tSVV
DO
Hi-Z
tOZ
Busy
Ready
tE/W
Busy/Ready Signal Output (AK93C95A/10A)
DAM02E-03
2004/05
- 12 -
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
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