LINER LTC1771ES8 10ma quiescent current high efficiency step-down dc/dc controller Datasheet

LTC1771
10µA Quiescent Current
High Efficiency Step-Down
DC/DC Controller
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FEATURES
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DESCRIPTIO
The LTC®1771 is a high efficiency current mode stepdown DC/DC controller that draws as little as 10µA DC
supply current to regulate the output at no load while
maintaining high efficiency for loads up to several amps.
Very Low Standby Current: 10µA
Available in Space-Saving 8-Lead MSOP Package
Output Currents: Up to 5A
Wide VIN Range: 2.8V to 20V Operation
VOUT Range: 1.23V to 18V
High Efficiency: Over 93% Possible
±2% Output Accuracy
Very Low Dropout Operation: 100% Duty Cycle
Current Mode Operation for Excellent Line and
Load Transient Response
Defeatable Burst ModeTM Operation
Short-Circuit Protected
Optional Programmable Soft-Start
Micropower Shutdown: IQ = 2µA
The LTC1771 drives an external P-channel power MOSFET
using a current mode, constant off-time architecture. An
external sense resistor is used to program the operating
current level. Current mode control provides short-circuit
protection, excellent transient response and controlled
start-up behavior. Burst Mode operation enables the
LTC1771 to maintain high efficiency down to extremely
low currents. Shutdown mode further reduces the supply
current to a mere 2µA. For low noise applications, Burst
Mode operation can be easily disabled with the MODE pin.
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APPLICATIO S
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Wide input supply range of 2.8V to 18V (20V maximum)
and 100% duty cycle operation for low dropout make the
LTC1771 ideal for a wide variety of battery-powered applications where maximizing battery life is important.
Cellular Telephones and Wireless Modems
1- to 4-Cell Lithium-Ion-Powered Applications
Portable Instruments
Battery-Powered Equipment
Battery Chargers
Scanners
The LTC1771’s availability in both 8-lead MSOP and SO
packages provides for a minimum area solution.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.
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TYPICAL APPLICATIO
VIN
4.5V TO 18V
RSENSE
0.05Ω
LTC1771 Efficiency
+
100
22µF
25V
VIN = 5V
VIN
RUN/SS
CSS
0.01µF
SENSE
PGATE
M1
Si6447DQ
ITH LTC1771
RC
10k
CC
22OpF
VFB
MODE
GND
VIN
L1
15µH
UPS5817
R2
1.64M
1%
+
COUT
150µF
6.3V
VOUT
3.3V
2A
EFFICIENCY (%)
90
80
VIN = 10V
VIN = 15V
70
60
50
R1
1M
1%
CFF
5pF
Figure 1. High Efficiency Step-Down Converter
1771 F01
VOUT = 3.3V
RSENSE = 0.05Ω
40
10
0.1
1
100
1000
LOAD CURRENT (mA)
10000
1771 F01b
1
LTC1771
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ABSOLUTE
RATI GS (Note 1)
Input Supply Voltage (VIN)........................ – 0.3V to 20V
Peak Driver Output Current < 10µs (PGATE) ............. 1A
RUN/SS Voltage ......................... – 0.3V to (VIN + 0.3V)*
MODE Voltage .......................................... – 0.3V to 20V
ITH, VFB Voltage .......................................... – 0.3V to 5V
SENSE Voltage (VIN > 12V)..(VIN – 12V) to (VIN + 0.3V)*
SENSE Voltage (VIN ≤ 12V) ........ – 0.3V to (VIN + 0.3V)*
Junction Temperature (Note 2) ............................ 125°C
Operating Temperature Range (Note 3)
LTC1771E ......................................... – 40°C to 85°C
LTC1771I ......................................... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
*RUN/SS and SENSE cannot exceed 20V.
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
RUN/SS
ITH
VFB
GND
1
2
3
4
8
7
6
5
LTC1771EMS8
MODE
SENSE
VIN
PGATE
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING
TJMAX = 125°C, θJA = 200°C/ W
LTKD
ORDER PART
NUMBER
TOP VIEW
RUN/SS 1
8
MODE
ITH 2
7
SENSE
VFB 3
6
VIN
GND 4
5
PGATE
LTC1771ES8
LTC1771IS8
S8 PART MARKING
S8 PACKAGE
8-LEAD PLASTIC SO
1771
1771I
TJMAX = 125°C, θJA = 110°C/ W
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VIN = 10V, VRUN = open unless otherwise specified.
SYMBOL
PARAMETER
VFB
Feedback Voltage
(Note 5)
●
IFB
Feedback Current
(Note 5)
●
ISUPPLY
No-Load Supply Current
VIN = 10V, ILOAD = 0 (Note 6)
∆VLINEREG
Reference Voltage Line Regulation
VIN = 5V to 15V (Note 5)
●
0.003
0.03
∆VLOADREG
Output Voltage Load Regulation
ITH = 0.5V to 2V, Burst Disabled (Note 5)
●
0.25
1
%
IQ
Input DC Supply Current
Active Mode (PGATE = 0V)
Sleep Mode (Note 6)
Shutdown
Short Circuit
(Note 4)
VIN = 2.8V to 18V
VIN = 2.8V to 18V, VFB = 1.5V
VIN = 2.8V to 18V, VRUN = 0V
VIN = 2.8V to 18V, VFB = 0V
150
9
2
175
235
15
6
275
µA
µA
µA
µA
∆VSENSE(MAX)
Maximum Current Sense Threshold
VFB = VREF – 20mV
140
180
mV
∆VSENSE(MIN)
Minimum Current Sense Threshold
VFB = VREF + 20mV, Burst Disabled
– 25
mV
∆VSENSE(SLEEP)
Sleep Current Sense Threshold
ITH = 1V
50
mV
t OFF
Switch Off Time
VFB at Regulated Value
VFB = 0V
VMODE
Mode Pin Threshold
VMODE Rising
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CONDITIONS
MIN
TYP
MAX
1.205
1.230
1.255
V
1
10
nA
µA
10
●
●
110
UNITS
%/V
3
3.5
70
4
µs
µs
0.5
1.3
2
V
LTC1771
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C.
VIN = 10V, VRUN = open unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
VRUN/SS
RUN/SS Pin Threshold
VRUN/SS Rising
IRUN
Source Current
VRUN = 0V, VIN = 2.8V to 18V
PGATE t r, tf
PGATE Transition Time (Note 7)
Rise Time
Fall Time
CLOAD = 2000pF
CLOAD = 2000pF
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formulas:
LTC1771S8: TJ = TA + (PD)(110°C/W)
LTC1771MS8: TJ = TA + (PD)(150°C/W)
Note 3: The LTC1771E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the – 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC1771I is guaranteed and tested
over the – 40°C to 85°C operating temperature range.
MIN
TYP
0.5
1.0
2
V
0.3
1
3
µA
70
70
140
140
ns
ns
●
MAX
UNITS
Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 5: The LTC1771 is tested in a feedback loop that servos VFB to the
balance point for the error amplifier (VITH = 1.23V).
Note 6: No-load supply current consists of sleep mode current (9µA
typical) plus a small switching component necessary to overcome
Schottky diode leakage and feedback resistor current.
Note 7: tr and tf are measured at 10% to 90% levels.
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TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Input Voltage
Efficiency vs Load Current
100
100
FIGURE 1 CIRCUIT
90
Line Regulation
0.4
Burst Mode OPERATION
ENABLED
FIGURE 1 CIRCUIT
0.3
ILOAD = 50mA
80
ILOAD = 1mA
0.2
70
60
∆VOUT (%)
EFFICIENCY (%)
ILOAD = 1A
EFFICIENCY (%)
80
90
Burst Mode OPERATION
DISABLED
50
40
0.1
ILOAD = 100mA
0
– 0.1
ILOAD = 1A
30
70
– 0.2
20
10
60
2
4
6
8 10 12 14 16
INPUT VOLTAGE (V)
18
20
1771 G01
0
0.1
VIN = 10V
FIGURE 1 CIRCUIT
1
10
100
LOAD CURRENT (mA)
1000
– 0.3
– 0.4
0
5
10
15
20
INPUT VOLTAGE (V)
1771 G02
1771 G03
3
LTC1771
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TYPICAL PERFOR A CE CHARACTERISTICS
Burst Mode OPERATION
DISABLED
VIN = 15V
–0.2
Burst Mode
OPERATION
ENABLED
–0.4
VIN = 5V
–0.6
–0.8
150
TA = –50°C
100
50
0
–1.0
0.5
0
1.0
2.0
1.5
TA = 25°C
2
4
LOAD CURRENT (A)
2
0
SOFT-START CURRENT (µA)
TA = 25°C
2
4
6 8 10 12 14 16 18 20
INPUT VOLTAGE (V)
Current Sense Voltage
vs Temperature
200
TA = –50°C
4
2
1771 G06
5
8
SHUTDOWN QUIESCENT CURRENT (µA)
4
Run/SS Current vs Input Voltage
TA = –50°C
TA = –50°C
6
1771 G05
Shutdown Quiescent Current
vs Input Voltage
4
3
TA = 25°C
2
TA = 100°C
1
VIN = 10V
MAXIMUM
150
100
BURST THRESHOLD
50
0
MINIMUM
TA = 100°C
0
0
2
0
4
6 8 10 12 14 16 18 20
INPUT VOLTAGE (V)
0
2
4
6 8 10 12 14 16 18 20
INPUT VOLTAGE (V)
Reference Voltage
vs Temperature
1.25
–50
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
1771 G09
1771 G08
1771 G07
REFERENCE VOLTAGE (V)
TA = 25°C
8
6 8 10 12 14 16 18 20
INPUT VOLTAGE (V)
1771 G04
6
TA = 100°C
10
0
0
CURRENT SENSE VOLTAGE (mV)
∆VOUT (%)
0
TA = 100°C
SLEEP QUIESCENT CURRENT (µA)
0.2
12
200
FIGURE 1 CIRCUIT
ACTIVE MODE QUIESCENT CURRENT (µA)
0.4
Sleep Quiescent Current
vs Input Voltage
Active Mode Quiescent Current
vs Input Voltage
Load Regulation
Load Step Transient Response
Burst Mode Operation
VIN = 10V
1.24
1.23
VOUT
100mV/DIV
VOUT
50mV/DIV
INDUCTOR
CURRENT
1A/DIV
INDUCTOR
CURRENT
0.5A/DIV
1.22
1.21
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
1771 G10
4
50µs/DIV
VIN = 10V
VOUT = 3.3V
ILOAD = 100mA TO 2A
FIGURE 1 CIRCUIT
1771 G11
10µs/DIV
VIN = 10V
VOUT = 3.3V
ILOAD = 100mA
FIGURE 1 CIRCUIT
1771 G12
LTC1771
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PI FU CTIO S
RUN/SS (Pin 1): The voltage level on this pin controls
shutdown/run mode (ground = shutdown, open/high =
run). Connecting an external capacitor to this pin provides
soft-start.
PGATE (Pin 5): High Current Gate Driver for External
P-Channel MOSFET Switch. Voltage swing is from ground
to VIN.
ITH (Pin 2): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 3V.
SENSE (Pin 7): Current Sense Input for Monitoring Switch
Current. Maximum switch current and Burst Mode
threshold is programmed with an external resistor between SENSE and VIN.
VIN (Pin 6): Main Input Voltage Supply Pin.
VFB (Pin 3): Feedback of Output Voltage for Comparison
to Internal 1.23V Reference. An external resistive divider
across the output is returned to this pin.
MODE (Pin 8): Burst Mode Enable/Disable Pin. Connecting this pin to VIN (or above 2V) enables Burst Mode
operation, while connecting this pin to ground disables
Burst Mode operation. Do not leave floating.
GND (Pin 4): Ground Pin.
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FUNCTIONAL BLOCK DIAGRA
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VIN
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VIN
6
1µA
CSS
READY
RUN/SS
1
MODE
8
+
VIN
CIN
1.23V
REFERENCE
22k
RSENSE
(BURST ENABLE)
10% CURRENT
EA
ON
C
SENSE
+
ON
+
–
1.23V
SOFT-START
–
7
10% CURRENT
VOUT
SLEEP
*
250k
ITH
2
2V
RC
CC
1V
READY
GND
4
1V
+
CURRENT LIMITING
PGATE
B
5
MODE
*OPTIONAL FOR FOLDBACK
BLANKING
VIN
–
ON TRIGGER
D1
L
1-SHOT
3.5µs
STRETCH
VOUT
VFB
R2
+
3
COUT
R1
1771 BD
5
LTC1771
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OPERATIO
(Refer to Functional Block Diagram)
Main Control Loop
The LTC1771 uses a constant off-time, current mode
step-down architecture. During normal operation, the
P-channel MOSFET is turned on at the beginning of each
cycle and turned off when the current comparator C
triggers the 1-shot timer. The external MOSFET switch
stays off for the 3.5µs 1-shot duration and then turns back
on again to begin a new cycle. The peak inductor current
at which C triggers the 1-shot is controlled by the voltage
on Pin 3 (ITH), the output of the error amplifier EA. An
external resistive divider connected between VOUT and
ground allows EA to receive an output feedback voltage
VFB. When the load current increases, it causes a slight
decrease in VFB relative to the 1.23V reference, which in
turn causes the ITH voltage to increase until the average
inductor current matches the new load current.
The main control loop is shut down by pulling Pin 1
(RUN/SS) low. Releasing RUN/SS allows an internal 1µA
current source to charge soft-start capacitor CSS. When
CSS reaches 1V, the main control loop is enabled with the
ITH voltage clamped at approximately 40% of its maximum value. As CSS continues to charge, ITH is gradually
released allowing normal operation to resume.
Burst Mode Operation
The LTC1771 provides outstanding low current efficiency
and ultralow no-load supply current by using Burst Mode
operation when the MODE pin is pulled above 2V. During
Burst Mode operation, short burst cycles of normal switching are followed by a longer idle period with the switch off
and the load current is supplied by the output capacitor.
During this idle period, only the minimum required circuitry—1.23V reference and error amp—are left on, and
the supply current is reduced to 9µA. At no load, the output
capacitor is still discharged very slowly by leakage current
in the Schottky diode and feedback resistor current resulting in very low frequency burst cycles that add a few more
microamps to the supply current.
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Burst Mode operation is provided by clamping the minimum ITH voltage at 1V which represents about 25% of
maximum load current. If the load falls below this level, i.e.
the ITH voltage tries to fall below 1V, the burst comparator
B switches state signaling the LTC1771 to enter sleep
mode. During this time, EA is reduced to 10% of its normal
operating current and the external compensation capacitor is disconnected and clamped to 1V so that the EA can
drive its output with the lower available current. As the load
discharges the output capacitor, the internal ITH voltage
increases. When it exceeds 1V the burst comparator exits
sleep mode, reconnects the external compensation components to the error amplifier output, and returns EA to full
power along with the other necessary circuitry. This
scheme (patent pending) allows the EA to be reduced to
such a low operating current during sleep mode without
adding unacceptable delay to wake up the LTC1771 due to
the compensation capacitor on ITH required for stability in
normal operation.
Burst Mode operation can be disabled by pulling the
MODE pin to ground. In this mode of operation, the burst
comparator B is disabled and the ITH voltage allowed to go
all the way to 0V. The load can now be reduced to about 1%
of maximum load before the loop skips cycles to maintain
regulation. This mode provides a low noise output spectrum, useful for reducing both audio and RF interference,
at the expense of reduced efficiency at light loads.
Off-Time
The off-time duration is 3.5µs when the feedback voltage
is close to the reference voltage; however, as the feedback
voltage drops, the off-time lengthens and reaches a maximum value of about 70µs when VFB is zero. This ensures
that the inductor current has enough time to decay when
the reverse voltage across the inductor is low such as
during short circuit, thus protecting the MOSFET and
inductor.
LTC1771
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APPLICATIO S I FOR ATIO
The basic LTC1771 application circuit is shown in Figure
1 on the first page. External component selection is driven
by the load requirement and begins with the selection of
RSENSE. Once RSENSE is known, L can be chosen. Next, the
MOSFET and D1 are selected. The inductor is chosen
based largely on the desired amount of ripple current and
for Burst Mode operation. Finally CIN is selected for its
ability to handle the required RMS input current and COUT
is chosen with low enough ESR to meet the output voltage
ripple and transient specifications.
RSENSE is chosen based on the required output current.
The LTC1771 current comparator has a maximum threshold of 140mV/RSENSE. The current comparator threshold
sets the peak inductor current, yielding a maximum average output current IMAX equal to the peak less half the
peak-to-peak ripple current ∆IL. For best performance
when Burst Mode operation is enabled, choose ∆IL equal
to 35% of peak current. Allowing a margin for variations in
the LTC1771 and external components gives the following
equation for choosing RSENSE:
RSENSE = 100mV/IMAX
At higher supply voltages, the peak currents may be
slightly higher due to overshoot from current comparator
delay and can be predicted from the second term in the
following equation:
IPEAK
1/ 2
Inductor Value Selection
Once RSENSE is known, the inductor value can be determined. The inductance value has a direct effect on ripple
current. The ripple current decreases with higher inductance and increases with higher VOUT. The ripple current
during continuous mode operation is set by the off-time
and inductance to be:
V
+V 
∆IL(CONT) = t OFF  OUT D 
L


Kool Mµ is a registered trademark of Magnetics, Inc.
∆IL(BURST) ≈ 35% of IPEAK ≈ 0.05/RSENSE
For best efficiency when Burst Mode operation is enabled,
choose:
∆IL(CONT) ≤ ∆IL(BURST)
so that the inductor current is continuous during the burst
periods. This sets a minimum inductor value of:
LMIN = (75µH)(VOUT + VD)(RSENSE)
RSENSE Selection
V –V 
0.14
≅
+ 0.5  IN OUT 
RSENSE
 L(µH) 
where tOFF = 3.5µs. However, the ripple current at low
loads during Burst Mode operation is:
When burst is disabled, ripple currents less than ∆IL(BURST)
can be achieved by choosing L > LMIN. Lower ripple
current reduces output voltage ripple and core losses, but
too low of ripple current will adversely effect efficiency.
Inductor Core Selection
Once the value of L is known, the type of inductor must be
selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron
cores, forcing the use of more expensive ferrite,
molypermalloy or Kool Mµ® cores. Actual core loss is
independent of core size for a fixed inductor value, but is
very dependent on inductance selected. As inductance
increases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent increase in voltage ripple.
Do not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are space efficient, especially
when you can use several layers of wire. Because they
generally lack a bobbin, mounting is more difficult. However, designs for surface mount are available that do not
increase the height significantly.
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LTC1771
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APPLICATIO S I FOR ATIO
Power MOSFET Selection
An external P-channel power MOSFET must be selected
for use with the LTC1771. The main selection criteria for
the power MOSFET are the threshold voltage VGS(TH) and
the “on” resistance RDS(ON), reverse transfer capacitance
and total gate charge.
Since the LTC1771 can operate down to input voltages as
low as 2.8V, a sublogic level threshold MOSFET (RDS(ON)
guaranteed at VGS = 2.5V) is required for applications that
work close to this voltage. When these MOSFETs are used,
make sure that the input supply to the LTC1771 is less than
the absolute maximum VGS rating (typically 12V), as the
MOSFET gate will see the full supply voltage.
The required RDS(ON) of the MOSFET is governed by its
allowable power dissipation. For applications that may
operate the LTC1771 in dropout, i.e. 100% duty cycle, at
its worst case the required RDS(ON) is given by:
RDS(ON) =
(
)
2
(1+ δP )
where PP is the allowable power dissipation and δP is the
temperature dependency of RDS(ON). (1 + δP) is generally
given for a MOSFET in the form of a normalized RDS(ON) vs
temperature curve, but = 0.005/°C can be used as an
approximation for low voltage MOSFETs.
In applications where the maximum duty cycle is less than
100% and the LTC1771 is in continuous mode, the RDS(ON)
is governed by:
RDS(ON) =
DC =
PP
(DC)IOUT2 (1+ δP )
VOUT + VD
VIN + VD
where DC is the maximum operating duty cycle of the
LTC1771.
Catch Diode Selection
The catch diode carries load current during the off-time.
The average diode current is therefore dependent on the
P-channel switch duty cycle. At high input voltages the
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To maximize both low and high current efficiencies, a fast
switching diode with low forward drop and low reverse
leakage should be used. Low reverse leakage current is
critical to maximize low current efficiency since the leakage can potentially exceed the magnitude of the LTC1771
supply current. Low forward drop is critical for high
current efficiency since loss is proportional to forward
drop. The effect of reverse leakage and forward drop on
no- load supply current and efficiency for various Schottky
diodes is shown in Table 1. As can be seen, these are
conflicting parameters and the user must weigh the
importance of each spec in choosing the best diode for the
application.
Table 1. Effect of Catch Diode on Performance
PP
IOUT (MAX)
diode conducts most of the time. As VIN approaches VOUT
the diode conducts only a small fraction of the time. The
most stressful condition for the diode is when the output
is short-circuited. Under this condition, the diode must
safely handle IPEAK at close to 100% duty cycle.
DIODE
LEAKAGE
NO-LOAD
EFFICIENCY
(VR = 3.3V) VF @ 1A SUPPLY CURRENT AT 10V/1A
MBR0540
0.25µA
0.50V
10.4µA
86.3%
UPS5817
2.8µA
0.41V
11.8µA
88.2%
MBR0520
3.7µA
0.36V
12.2µA
88.4%
MBRS120T3
4.4µA
0.43V
12.2µA
87.9%
MBRM120LT3
8.3µA
0.32V
14.0µA
89.4%
MBRS320
19.7µA
0.29V
20.0µA
89.8%
CIN and COUT Selection
At higher load currents, when the inductor current is
continuous, the source current of the P-channel MOSFET
is a square wave of duty cycle VOUT/VIN. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
capacitor current is given by:
CIN required IRMS =
[
]1/ 2
IMAX VOUT (VIN − VOUT )
VIN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer’s
LTC1771
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APPLICATIO S I FOR ATIO
ripple current ratings are often based on 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Do not underspecify this component. An additional 0.1µF ceramic capacitor is also helpful on VIN for
high frequency decoupling.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering.
The output ripple (∆VOUT) in continuous mode is approximated by:

1 
∆VOUT ≈ IRIPPLE  ESR +

8 fCOUT 

where f is the operating frequency, COUT is the output
capacitance and IRIPPLE is the ripple current in the
inductor. For output ripple less than 100mV, assure COUT
required ESR is <2RSENSE.
The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guarantees that the output capacitance does not significantly
discharge during the operating frequency period due to
ripple current. The choice of using smaller output capacitance increases the ripple voltage due to the discharging
term but can be compensated for by using capacitors of
very low ESR to maintain the ripple voltage at or below
50mV. The ITH pin OPTI-LOOPTM compensation components can be optimized to provide stable, high performance transient response regardless of the output
capacitors selected.
When running into dropout, extra input and output capacitance may be necessary for optimal performance due to
the drop in frequency as the duty cycle approaches 100%.
Compare Figure 1 to the low dropout regulators shown in
the Typical Applications section for recommended CIN,
COUT, CFF and CC values for low dropout regulators vs
regulators not requiring low dropout.
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest ESR for its
OPTI-LOOP is a trademark of Linear Technology Corporation.
size of any aluminum electrolytic at a somewhat higher
price. Typically once the ESR requirement is satisfied, the
RMS current rating generally far exceeds the IRIPPLE(P-P)
requirement.
In surface mount applications multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum
electrolytics and dry tantalum capacitors are both available
in surface mount configurations. In case of tantalum, it is
critical that the capacitors are surge tested for use in
switching power supplies. An excellent choice is the
AVX TPS, AVX TPSV and KEMET T510 series of surface
mount tantalums, available in case heights ranging from
2mm to 4mm. Other capacitor types include Sanyo
OS-CON, Sanyo POSCAP, Nichicon PL series and
Panasonic SP.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 +L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in the LTC1771 circuits: the LTC1771 DC bias
current, MOSFET gate charge current, I2R losses and
catch diode losses.
1. The DC bias current is 9µA at no load and increases
proportionally with load up to a constant 150µA during
continuous mode. This bias current is so small that this
loss is negligible at loads above a milliamp but at no
load accounts for nearly all of the loss.
2. The MOSFET gate charge current results from switching the gate capacitance of the power MOSFET switch.
Each time the gate is switched from high to low to high
again, a packet of charge dQ moves from VIN to ground.
The resulting dQ/dt is the current out of VIN which is
typically much larger than the DC bias current. In
9
LTC1771
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APPLICATIO S I FOR ATIO
continuous mode, IGATECHG = fQP where QP is the gate
charge of the internal switch. Both the DC bias and gate
charge losses are proportional to VIN and thus their
effects will be more pronounced at higher supply
voltages.
3. I2R losses are predicted from the internal switch, inductor and current sense resistor. In continuous mode the
average output current flows through L but is “chopped”
between the P-channel MOSFET in series with RSENSE
and the output diode. The MOSFET RDS(ON) plus RSENSE
multiplied by the duty cycle can be summed with the
resistance of L to obtain I2R losses.
4. The catch diode loss is proportional to the forward drop
as the diode conducts current during the off-time and is
more pronounced at high supply voltages where the
off-time is long. However, as discussed in the Catch
Diode section, diodes with lower forward drops often
have higher leakage currents, so although efficiency is
improved, the no-load supply current will increase. The
diode loss is calculated by multiplying the forward
voltage drop times the diode duty cycle multiplied by
the load current.
Other losses including CIN and COUT ESR dissipative
losses, and inductor core losses, generally account for
less than 2% total additional loss.
Output Voltage Programming
The output voltage is programmed with an external divider
from VOUT to VFB (Pin 1) as shown in Figure 2. The
regulated voltage is determined by:
VOUT
VOUT  VOUT 


R1 + R2  VIN 
A 5pF feedforward capacitor across R2 is recommended
to minimize output voltage ripple in Burst Mode operation.
Run/Soft-Start Function
The RUN/SS pin is a dual purpose pin that provides the
soft- start function and a means to shut down the LTC1771.
Soft-start reduces the input surge current from VIN by
gradually increasing the internal current limit. Power
supply sequencing can also be accomplished using
this pin.
An internal 1µA current source charges up an external
capacitor CSS. When the voltage on the RUN/SS reaches
1V, the LTC1771 begins operating. As the voltage on the
RUN/SS continues to ramp from 1V to 2.2V, the internal
current limit is also ramped at a proportional linear rate.
The current limits begins near 40% maximum load at
VRUN/SS = 1V and ends at maximum load at VRUN/SS =
2.2V. The output current thus ramps up slowly, reducing
the starting surge current required from the input power
supply. If the RUN/SS has been pulled all the way to
ground, there will be a delay before the current limit starts
increasing and is given by:
tDELAY ≈ CSS/ICHG
Foldback Current Limiting
CFF
5pF
R2
VFB
R1
GND
1771 F02
Figure 2. LTC1771 Adjustable Configuaration
10
∆IVIN =
where ICHG ≅ 1µA. Pulling the RUN/SS pin below 0.5V
puts the LTC1771 into a low quiescent current shutdown
(IQ < 2µA).
 R2
VOUT = 1.23  1 + 
 R1
LTC1771
To minimize no-load supply current, resistor values in the
megohm range should be used. The increase in supply
current due to the feedback resistors can be calculated
from:
As described in the Catch Diode Selection, the worst-case
dissipation for diode occurs with a short-circuit output,
when the diode conducts the current limit value almost
continuously. In most applications this will not cause
excessive heating, even for extended fault intervals. However, when heat sinking is at a premium or higher forward
voltage drop diodes are being used, foldback current
LTC1771
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APPLICATIO S I FOR ATIO
limiting should be added to reduce the current in proportion to the severity of the fault.
Foldback current limiting is implemented by adding two
diodes in series between the output and the ITH pin as
shown in the Functional Diagram. In a hard short (VOUT =
0V) the current will be reduced to approximately 25% of
the maximum output current.
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest amount of time
that the LTC1771 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays and
the amount of gate charge required to turn on the
P-channel MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
V
+ VD 
tON = tOFF  OUT
 > tON(MIN)
 VIN − VOUT 
Mode Pin
Burst Mode operation is disabled by pulling MODE (Pin 8)
below 0.5V. Disabling Burst Mode operation provides a
low noise output spectrum, useful for reducing both audio
and RF interference. It does this by keeping the frequency
constant (for fixed VIN) down to much lower load current
(1% to 2% of IMAX) and reducing the amount of output
voltage and current ripple at light loads. When Burst Mode
operation is disabled, efficiency is reduced at light loads
and no load supply current increases to 175µA.
Low Supply Operation
Although the LTC1771 can function down to 2.8V, the
maximum allowable output current is reduced when VIN
decreases below 3.2V. Figure 4 shows the amount of
change as the supply is reduced below 3.2V, where 100%
of maximum load equals 0.1/RSENSE. To ensure adequate
output current at VIN < 3.2V, simply lower RSENSE by the
same percentage as the current reduction in Figure 4.
where tOFF = 3.5µs and tON(MIN) is generally about 0.4µs
for the LTC1771.
120
MAXIMUM LOAD (%)
As the on-time approaches tON(MIN), the LTC1771 will
remain in Burst Mode operation for an increasingly larger
portion of the load range (see Figure 3) and at or below
tON(MIN) will remain in Burst Mode operation 100% of the
time. The output voltage will continue to be regulated, but
the ripple current and ripple voltage will increase.
140
100
80
60
40
20
100
0
2.5
% OF MAXIMUM LOAD
80
3.0
3.5
4.0
4.5
INPUT VOLTAGE (V)
5.0
1771 F04
Figure 4. Maximum Load vs Input Voltage
60
40
PC Board Layout Checklist
20
0
0
0.5
1.5
1.0
ON-TIME (µs)
2.0
2.5
1771 F03
Figure 3. Burst Threshold vs On-Time
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1771. These items are also illustrated graphically in
the layout diagram of Figure 5. Check the following in your
layout:
1. Is the Schottky diode closely connected to the drain of
the external MOSFET and the input cap ground?
11
LTC1771
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APPLICATIO S I FOR ATIO
2. Is the 0.1µF input decoupling capacitor closely connected between VIN (Pin 6) and ground (Pin 4)? This
capacitor carries the high frequency peak currents.
3. Does the VFB pin connect directly to the feedback
resistors? The resistive divider R1 and R2 must be
connected between the (+) plate of COUT and signal
ground. Locate the feedback resistors right next to the
LTC1771. The VFB line should not be routed close to any
nodes with high slew rates.
4. Is the 1000pF decoupling capacitor for the current
sense resistor connected as close as possible to Pins 6
and 7? Ensure accurate current sensing with Kelvin
connections to the sense resistor.
5. Is the (+) plate of CIN closely connected to the sense
resistor ? This capacitor provides the AC current to the
MOSFET.
6. Are the signal and power grounds segregated? The
signal ground consists of the (–) plate of COUT, Pin 4 of
the LTC1771 and the resistive divider. The power ground
consists of the Schottky diode anode and the (–) plate
of CIN which should have as short lead lengths as
possible.
7. Keep the switching node (SW) and the gate node
(PGATE) away from sensitive small signal nodes, especially the voltage sensing feedback pin (VFB), and minimize their PC trace area.
CSS
1
CITH
R1
RITH 2
3
4
R2
CFF
RUN/SS
MODE
ITH
SENSE
LTC1771
VFB
GND
VIN
PGATE
8
MODE
7
6
5
0.1µF
CIN D1
+
COUT
L
VOUT
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 5. LTC1771 Layout Diagram
12
As a design example, assume VIN = 10V (nominal), VIN =
15V(MAX), VOUT = 3.3V, and IMAX = 2A. With this information, we can easily calculate all the important components.
RSENSE = 100mV/2A = 0.05Ω
To optimize low current efficiency, MODE pin is tied to VIN
to enable Burst Mode operation, thus the minimum inductance necessary is:
LMIN = 70µH(3.3V + 0.5)(0.05Ω) = 13.3µH
15µH is chosen for the application.
 3.3V + 0.5V 
∆IL = 3.5µs 
 = 0.89A
 15µH 
For the feedback resistors, choose R1 = 1M to minimize
supply current. R2 can then be calculated to be:
R2 = (VOUT/1.23 – 1) • R1 = 1.68M
Assume that the MOSFET dissipation is to be limited to
PP = 0.25W.
If TA = 70°C and the thermal resistance of the MOSFET is
83°C/W, then the junction temperatures will be 91°C and
δP = 0.33. The required RDS(ON) for the MOSFET can now
be calculated:
0.25W
 3.3V + 0.5V 

 2A
 10 V + 0.5V 
= 0.130Ω
P - Channel RDS(ON) =
( ) (1.33)
2
Since the gate of the MOSFET will see the full input voltage,
a MOSFET must be selected whose VGS(MAX) > 15V. A
P-channel MOSFET that meets both the VGS(MAX) and
RDS(ON) requirement is the Si6447DQ.
Q1
+
Design Example
1771 F05
The most stringent requirement for the Schottky diode
occurs when VOUT = 0V (i.e., short circuit) at maximum
VIN. In this case the worst-case dissipation rises to:
 VIN 
PD = ISC(AVG) (VD)

 VIN + VD 
LTC1771
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APPLICATIO S I FOR ATIO
With a 0.05Ω sense resistor ISC(AVG) = 2A will result,
increasing the 0.5V Schottky diode dissipation to 1W.
output ripple. The output voltage ripple due to ESR is
approximately:
CIN is chosen for a RMS current rating of at least 1A at
temperature. COUT is chosen with an ESR of 0.05Ω for low
VORIPPLE ≈ (RESR)(∆IL) = 0.05Ω (0.89AP-P) = 45mVP-P
U
TYPICAL APPLICATIO S
3.3V to 2.5V/1A Regulator with Burst Mode Operation Enabled
0.01µF
1
220pF
10k
2
3
4
RUN/SS
MODE
ITH
SENSE
LTC1771
8
7
6
VFB
1000pF
VIN
GND
PGATE
5
RSENSE
0.1Ω
Si3443DV
1M
1%
1.02M
1%
+
L1
22µH
+
5pF
D1
CIN
33µF
16V
COUT
150µF
6.3V
VIN
3.3V
TO 12V
VOUT
2.5V
1A
1771 TA01
CIN: AVX TPSC336M016R0300
COUT: SANYO POSCAP 6TPB150M
D1: MICROSEMI UPS5817
L1: SUMIDA CDRH6D38-220
Low Dropout 5V/2A Regulator with Burst Mode Operation Disabled
0.01µF
1
330pF
10k
2
3
4
1M
1%
RUN/SS
MODE
ITH
SENSE
LTC1771
VFB
8
7
6
1000pF
VIN
GND
PGATE
3.09M
1%
15pF
5
RSENSE
0.05Ω
Si6447DQ L1
22µH
+
+
D1
CIN
22µF
25V
×2
COUT
150µF
6.3V
VIN
5.5V
TO 18V
VOUT
5V
2A
1771 TA04
CIN: AVX TPSD226M025R0200
COUT: SANYO POSCAP 6TPB150M
D1: MICROSEMI UPS5817
L1: SUMIDA CR75-220
13
LTC1771
U
TYPICAL APPLICATIO S
Low Dropout Single Cell Lithium-Ion to 3V
0.01µF
1
330pF
10k
2
RUN/SS
MODE
ITH
SENSE
8
7
LTC1771
3
1000pF
6
VFB
4
MODE
VIN
GND
5
PGATE
Si3443DV
1M
1%
+
RSENSE
0.05Ω
L1
15µH
1.43M
1%
CIN
47µF
10V
+
15pF
Li-Ion
3.4V TO 4.2V
VOUT
3V
2A
COUT
220µF
4V
D1
1771 TA02
CIN: TAIYO YUDEN LMK550BJ476MM
COUT: SANYO POSCAP 4TPB220M
D1: MICROSEMI UPS5817
L1: SUMIDA CR75-150
12V/1A Zeta Converter
VIN
VIN (V) ILOAD(MAX) (A)
0.01µF
1
3.01M
1%
220pF
Q1
10k
2
280k
1%
3
402k
1%
4
RUN/SS
MODE
ITH
SENSE
LTC1771
VFB
4.5
5
10
15
18
MODE
7
1000pF
6
0.7
0.9
1.8
2.4
2.6
VIN
GND
1M
1%
8
PGATE
5
Si6459DQ
8.66M
1%
•
L1A
47µH
CIN: AVX TPSD226M025R0200
COUT: AVX TPSV107M020R0085
C1: AVX TPSD336M020R0200
D1: MOTOROLA MBRS140T3
L1A, L1B: COILTRONICS VP4-0075, B H ELECTRONICS Q10549
Q1: MOTOROLA MMBT2N2222LT1
CIN
22µF
25V
×2
•
+
5pF
+
RSENSE
0.025Ω
C1
33µF
20V
×2
L1B
47µH
D1
+
COUT
100µF
20V
VIN
5V
TO 18V
VOUT
12V
1A
1771 TA05
2.5V/1A Regulator with Foldback Current Limit
0.01µF
1
220pF
10k
2
3
4
1M
1%
RUN/SS
MODE
ITH
SENSE
LTC1771
VFB
8
MODE
7
6
1000pF
VIN
GND
PGATE
1.02M
1%
5
+
RSENSE
0.1Ω
4 3
2
CIN: AVX TPSC336M016R0300
COUT: SANYO POSCAP 6TPB150M
L1: SUMIDA CDRH6D38-220
U1: INTERNATIONAL RECTIFIER
FETKY TM IRF7422D2
1
ITH
U1
5pF
5 6
7
VIN
2.8V
TO 12V
CIN
33µF
16V
8
1N4148
×2
L1
22µH
+
COUT
150µF
6.3V
1771 TA06
14
VOUT
2.5V
1A
LTC1771
U
TYPICAL APPLICATIONS
4-NiCd/NiMH Battery Charger
0.01µF
1
220pF
10k
2
3
4
RUN/SS
MODE
ITH
SENSE
LTC1771
VFB
8
MODE
7
6
1000pF
VIN
GND
PGATE
5
RSENSE
0.1Ω
Si6447DQ
1M
1%
4.69M
1%
+
L1
47µH
+
5pF
D1
VIN
8V
TO 18V
CIN
22µF
25V
D2
VOUT
4-NiCd
1A
COUT
100µF
10V
1771 TA07
CIN: AVX TPSD226M025R0200
COUT: SANYO POSCAP 10TPB100M
D1, D2: MICROSEMI UPS5817
L1: COILTRONICS UP2B-470, GOWANDA SMP3316-472M
U
PACKAGE DESCRIPTIO
Dimension in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.040 ± 0.006
(1.02 ± 0.15)
0.007
(0.18)
0.034 ± 0.004
(0.86 ± 0.102)
0.118 ± 0.004*
(3.00 ± 0.102)
8
7 6
5
0° – 6° TYP
0.021 ± 0.006
(0.53 ± 0.015)
SEATING
PLANE 0.012
(0.30)
0.0256
REF
(0.65)
BSC
0.006 ± 0.004
(0.15 ± 0.102)
0.118 ± 0.004**
(3.00 ± 0.102)
0.193 ± 0.006
(4.90 ± 0.15)
MSOP (MS8) 1098
1
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
2 3
4
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
0°– 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.014 – 0.019
(0.355 – 0.483)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
8
7
6
5
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
SO8 1298
1
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
2
3
4
15
LTC1771
U
TYPICAL APPLICATIO
5V/1A Zeta Converter
VIN (V) ILOAD(MAX) (A)
2.8
0.8
3.3
1.1
5
1.7
7.5
2.3
10
2.7
12
2.9
0.01µF
1
220pF
10k
2
3
4
1M
1%
RUN/SS
MODE
ITH
SENSE
LTC1771
VFB
8
MODE
7
6
1000pF
VIN
GND
PGATE
5
Si3443DV
3.09M
1%
•
+
5pF
•
L1A
22µH
CIN: AVX TPSD336M020R0200
COUT: SANYO POSCAP 10TPB100M
C1: AVX TPSD107M010R065
D1: MICROSEMI UPS5817
L1A, L1B: COILTRONICS CTX10-4, BH ELECTRONICS S10-1013
C1
100µF
10V
+
RSENSE
0.025Ω
CIN
33µF
20V
×2
D1
L1B
22µH
+
COUT
100µF
10V
VIN
2.8V
TO 12V
VOUT
5V
1A
1771 TA03
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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100% DC, 3.5V ≤ VIN ≤ 16V
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Selectable IPEAK = 300mA or 600mA
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with Internal Schottky Diode
LTC1174 with Internal Schottky Diode
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Constant Frequency, 2V to 10V VIN, MS8
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95% DC, 3.5V to 36V VIN
LT®1761 Series
100mA, Low Noise, LDO Micropower Regulators in SOT-23
20µA Quiescent Current, 20µVRMS Noise
LT1763 Series
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30µA Quiescent Current, 20µVRMS Noise
LTC1772
Constant Frequency Step-Down DC/DC Controller
SOT-23, 2.2V to 9.8V VIN
LTC1877
High Efficiency Monolithic Step-Down Regulator
550kHz, MS8, VIN Up to 10V, IQ = 10µA,
IOUT to 600mA
LTC1878
High Efficiency Monolithic Step-Down Regulator
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IOUT to 600mA
16
Linear Technology Corporation
1771f LT/TP 1000 4K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 2000
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