MM5452, MM5453 www.ti.com SNLS367C – FEBRUARY 1995 – REVISED MARCH 2013 MM5452/MM5453 Liquid Crystal Display Drivers Check for Samples: MM5452, MM5453 FEATURES DESCRIPTION • • • • • • • • The MM5452 is a monolithic integrated circuit utilizing CMOS metal gate, low threshold enhancement mode devices. It is available in a 40-pin PDIP package. The chip can drive up to 32 segments of LCD and can be paralleled to increase this number. The chip is capable of driving a 4½-digit 7-segment display with minimal interface between the display and the data source. 1 2 Serial Data Input No Load Signal Required DATA ENABLE (MM5452) Wide Power Supply Operation TTL Compatibility 32 or 33 Outputs Alphanumeric and Bar Graph Capability Cascaded Operation Capability The MM5452 stores display data in latches after it is clocked in, and holds the data until new display data is received. APPLICATIONS • • • • • COPS™ or Microprocessor Displays Industrial Control Indicator Digital Clock, Thermometer, Counter, Voltmeter Instrumentation Readouts Remote Displays Block Diagram Figure 1. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1995–2013, Texas Instruments Incorporated MM5452, MM5453 SNLS367C – FEBRUARY 1995 – REVISED MARCH 2013 Absolute Maximum Ratings www.ti.com (1) (2) Voltage at Any Pin, Referenced to Gnd -0.3V to +10V Storage Temperature -65°C to +150°C Power Dissipation at 25°C 350mW Power Dissipation at 70°C 300mW Junction Temperature +150°C Lead Temperature (1) (2) (Soldering, 10s) 300°C “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. Recommended Operating Conditions VDD 3V to 10V Operating Temperature −40°C to 85°C Electrical Characteristics TA within operating range, VDD = 3.0V to 10V, VSS = 0V unless otherwise specified. Parameter Conditions Max Units 10 V VDD= 5V 10 µA VDD= 10V 40 µA VDD= 3V 0.4 V VDD= 5V 0.8 V VDD= 10V 0.8 V Supply Voltage, VDD Min Typ 3 Average Supply Current, IDD All Outputs Open, Clock=Gnd, Data=Gnd,OSC=Gnd, BP_IN @ 32Hz Input Logical '0' Voltage, VIL Input Logical '1' Voltage, VIH VDD= 3V 2.0 V VDD= 5V 2.0 V VDD= 10V 8.0 Segment Sink Current, IOL VDD= 3V, VOUT= 0.3V -20 Segment Source Current, IOH VDD= 3V, VOUT= 2.7V Backplane Out Sink Current, IOL VDD= 3V, VOUT= 0.3V Backplane Out Source Current, IOH VDD= 3V, VOUT= 2.7V 320 Segment Output Offset Voltage Segment Load = 250pF Clock Input Frequency, fCLOCK µA 20 40 µA -320 -500 µA 500 µA (1) Backplane Output Offset Voltage Backplane Load = 8750pF Backplane Out Frequency (1) ROSC_IN= 50kΩ, COSC_IN= 0.01µF (2) V -40 +/-50 mV +/-50 mV 75 Hz VDD= 3V (1) (3) 500 VDD= 5V (1) 750 kHz 1.0 MHz 60 % VDD= 10V (1) kHz Clock Input Duty Cycle (2) 40 Data Input Set-Up Time, tDS 300 ns Data Input Hold Time, tDH 300 ns DataEnable Set-up Time, tDES 100 ns (1) (2) (3) 2 This parameter is ensured (but not production tested) over the operating temperature range and the operating supply voltage range. Not to be used in Q.A. testing. Clock input rise time (tr) and fall time (tf) must not exceed 300ns AC input waveform for test purposes: tr≤ 20ns, tf≤ 20ns, fCLOCK= 500kHz, Duty Cycle = 50% ±10% Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: MM5452 MM5453 MM5452, MM5453 www.ti.com SNLS367C – FEBRUARY 1995 – REVISED MARCH 2013 Connection Diagram Figure 2. Top View See Package Number NFJ0040A Figure 3. Top View See Package Number NFJ0040A Figure 4. Top View See Package Number FN0044A Figure 5. Top View See Package Number FN0044A Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: MM5452 MM5453 3 MM5452, MM5453 SNLS367C – FEBRUARY 1995 – REVISED MARCH 2013 www.ti.com FUNCTIONAL DESCRIPTION The MM5452 is specifically designed to operate 4½-digit 7-segment displays with minimal interface with the display and the data source. Serial data transfer from the data source to the display driver is accomplished with 2 signals, serial data and clock. Since the MM5452 does not contain a character generator, the formatting of the segment information must be done prior to inputting the data to the MM5452. Using a format of a leading “1” followed by the 32 data bits allows data transfer without an additional load signal. The 32 data bits are latched after the 36th clock is complete, thus providing non-multiplexed, direct drive to the display. Outputs change only if the serial data bits differ from the previous time. A block diagram is shown in Figure 1. For the MM5452 a DATA ENABLE is used instead of the 33rd output. If the DATA ENABLE signal is not required, the 33rd output can be brought out. This is the MM5453 device. Figure 7 shows the input data format. A start bit of logical “1” precedes the 32 bits of data. At the 36th clock a LOAD signal is generated synchronously with the high state of the clock, which loads the 32 bits of the shift registers into the latches. At the low state of the clock a RESET signal is generated which clears all the shift registers for the next set of data. The shift registers are static master-slave configuration. There is no clear for the master portion of the first shift register, thus allowing continuous operation. If the clock is not continuous, there must be at least a complete set of 36 clocks otherwise the shift registers will not load and clear. Bit 1 is the first bit following the start bit and it will appear on device pin 18 of the MM5452N and MM5453N, and on device pin 20 of the MM5452V and MM5453V. Figure 6 shows the timing relationships between data, clock and DATA ENABLE. Figure 6. Timing Diagram Figure 7. Input Data Format Figure 8 shows a typical application. Note how the input data maps to the output pins and the display. The MM5452 and MM5453 do not have format restrictions, as all outputs are controllable. The application assumes a specific display pinout. Different display/driver connection patterns will, of course, yield a different input data format. 4 Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: MM5452 MM5453 MM5452, MM5453 www.ti.com SNLS367C – FEBRUARY 1995 – REVISED MARCH 2013 Consult LCD manufacturer’s data sheet for specific pinouts. Figure 8. Typical 4½-Digit Display Application Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: MM5452 MM5453 5 MM5452, MM5453 SNLS367C – FEBRUARY 1995 – REVISED MARCH 2013 www.ti.com *The minimum recommended value for R for the oscillator input is 9 kΩ. An RC time constant of approximately 4.91 × 10−4 should produce a backplane frequency between 30 Hz and 150 Hz. Figure 9. Parallel Backplane Outputs Figure 10. External Backplane Clock Figure 11 shows a four wire remote display that takes advantage of the device’s serial input to move many bits of display information on a few wires. USING AN EXTERNAL CLOCK The MM5452/MM5453 LCD Drivers can be used with an externally supplied clock, provided it has a duty cycle of 50%. Deviations from a 50% duty cycle result in an offset voltage on the LCD. In Figure 10, a flip-flop is used to assure a 50% duty cycle. The oscillator input is grounded to prevent oscillation and reduce current consumptions in the chips. The oscillator is not used. Using an external clock allows synchronizing the display drive with AC power, internal clocks, or DVM integration time to reduce interference from the display. Figure 12 is a general block diagram that shows how the device’s serial input can be used to advantage in an analog display. The analog voltage input is compared with a staircase voltage generated by a counter and a digital-to-analog converter or resistor array. The result of this comparison is clocked into the MM5452, MM5453. The next clock pulse increments the staircase and clocks the new data in. 6 Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: MM5452 MM5453 MM5452, MM5453 www.ti.com SNLS367C – FEBRUARY 1995 – REVISED MARCH 2013 With a buffer amplifier, the same staircase waveform can be used for many displays. The digital-to-analog converter need not be linear; logarithmic or other non-linear functions can be displayed by using weighted resistors or special DACs. This system can be used for status indicators, spectrum analyzers, audio level and power meters, tuning indicators, and other applications. Figure 11. Four Wire Remote Display Data is high until staircase > input Figure 12. Analog Display Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: MM5452 MM5453 7 MM5452, MM5453 SNLS367C – FEBRUARY 1995 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision B (March 2013) to Revision C • 8 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 7 Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated Product Folder Links: MM5452 MM5453 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) MM5452N NRND PDIP NFJ 40 TBD Call TI Call TI -40 to 85 MM5452N MM5452N/NOPB ACTIVE PDIP NFJ 40 9 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 MM5452N MM5452V NRND PLCC FN 44 25 TBD Call TI Call TI -40 to 85 MM5452V MM5452V/NOPB ACTIVE PLCC FN 44 25 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -40 to 85 MM5452V MM5452VX/NOPB ACTIVE PLCC FN 44 500 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -40 to 85 MM5452V MM5453N NRND PDIP NFJ 40 9 TBD Call TI Call TI -40 to 85 MM5453N MM5453N/NOPB ACTIVE PDIP NFJ 40 9 Green (RoHS & no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 MM5453N MM5453V/NOPB ACTIVE PLCC FN 44 25 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -40 to 85 MM5453V MM5453VX/NOPB ACTIVE PLCC FN 44 500 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR -40 to 85 MM5453V (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2015 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA NFJ0040A N0040A N40A (Rev E) www.ti.com MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) 4040005 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. 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