Freescale Semiconductor Data Sheet MCF5475EC Rev. 2, 10/2004 MCF547x Integrated Microprocessor Electrical Characteristics Applies to the MCF5470, MCF5471, MCF5472, MCF5473, MCF5474, and MCF5475 This chapter contains electrical specification tables and reference timing diagrams for the MCF547x microprocessor. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of the MCF547x. NOTE The parameters specified in this MPU document supersede any values found in the module specifications. 1 Maximum Ratings Table 1 lists maximum and minimum ratings for supply and operating voltages and storage temperature. Operating outside of these ranges may cause erratic behavior or damage to the processor. © Freescale Semiconductor, Inc., 2004. All rights reserved. Table of Contents 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Maximum Ratings................................................1 Thermal Characteristics ......................................2 DC Electrical Specifications ................................3 Supply Voltage Sequencing and Separation Cautions ..............................................................5 Output Driver Capability and Loading .................6 PLL Timing Specifications ...................................7 Reset Timing Specifications ................................8 FlexBus................................................................8 SDRAM Bus ......................................................11 PCI Bus .............................................................17 Fast Ethernet AC Timing Specifications ............18 General Timing Specifications...........................21 I2C Input/Output Timing Specifications .............21 JTAG and Boundary Scan Timing .....................23 DSPI Electrical Specifications ...........................26 Timer Module AC Timing Specifications............26 Thermal Characteristics Table 1. Absolute Maximum Ratings Rating Symbol Value Units External (I/O pads) supply voltage (3.3-V power pins) EVDD –0.3 to +4.0 V Internal logic supply voltage IVDD –0.5 to +2.0 V Memory (I/O pads) supply voltage (2.5-V power pins) SD VDD –0.3 to +4.0 SDR Memory –0.3 to +2.8 DDR Memory V PLL supply voltage PLL VDD –0.5 to +2.0 V Internal logic supply voltage, input voltage level Vin –0.5 to +3.6 V Storage temperature range Tstg –55 to +150 2 Thermal Characteristics 2.1 Operating Temperatures o C Table 2 lists junction and ambient operating temperatures. Table 2. Operating Temperatures Characteristic Symbol Value Units Maximum operating junction temperature Tj 105 oC Maximum operating ambient temperature TAmax <701 oC Minimum operating ambient temperature TAmin –0 oC NOTES: 1 This published maximum operating ambient temperature should be used only as a system design guideline. All device operating parameters are guaranteed only when the junction temperature lies within the specified range. 2.2 Thermal Resistance Table 3 lists thermal resistance values. Table 3. Thermal Resistance Characteristic Symbol Value Unit 324 pin TEPBGA — Junction to ambient, natural Four layer board (2s2p) convection θJMA 22–241,2 °C/W 388 pin TEPBGA — Junction to ambient, natural Four layer board (2s2p) convection θJMA 20–221,2 °C/W Junction to ambient (@200 ft/min) θJMA 231,2 °C/W Junction to board θJB 153 °C/W Junction to case θJC 104 °C/W Ψjt 21,5 °C/W Junction to top of package Four layer board (2s2p) Natural convection MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 2 Freescale Semiconductor DC Electrical Specifications NOTES: 1 θJA and Ψjt parameters are simulated in accordance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of θJA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer’s system using the Ψjt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. 2 Per JEDEC JESD51-6 with the board horizontal. 3 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 4 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 5 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 3 DC Electrical Specifications Table 4 lists DC electrical operating temperatures. This table is based on an operating voltage of EVDD = 3.3 VDC ± 0.3 VDC and IVDD of 1.5 ± 0.07 VDC. Table 4. DC Electrical Specifications Characteristic Symbol Min Max Units EVDD 3.0 3.6 V SD VDD 2.30 2.70 V IVDD 1.43 1.58 V PLL VDD 1.43 1.58 V USB_OSVDD 3.0 3.6 V USBVDD 3.0 3.6 V USB_PHYVDD 3.0 3.6 V USB_OSCAVDD 1.43 1.58 V USB_PLLVDD 1.43 1.58 V Input high voltage SSTL 3.3V (SDR DRAM) VIH 2.0 3.6 V Input low voltage SSTL 3.3V (SDR DRAM) VIL –0.5 0.8 V Input high voltage SSTL 2.5V (DDR DRAM) VIH 2.0 2.8 V Input low voltage SSTL 2.5V (DDR DRAM) VIL –0.5 0.8 V Output high voltage IOH = 8 mA, 16 mA,24 mA VOH 2.4 — V Output low voltage IOL = 8 mA, 16 mA,24 mA5 VOL — 0.5 V CIN — TBD pF External (I/O pads) operation voltage range Memory (I/O pads) operation voltage range (DDR Memory) Internal logic operation voltage range 1 PLL Analog operation voltage range 1 USB oscillator operation voltage range USB digital logic operation voltage range USB PHY operation voltage range USB oscillator analog operation voltage range USB PLL operation voltage range Capacitance 2, Vin = 0 V, f = 1 MHz NOTES: 1 IVDD and PLL VDD should be at the same voltage. PLL VDD should have a filtered input. Please see Figure 1 for an example circuit. Note: There are three PLL VDD inputs. A filter circuit should used on each PLL VDD input. 2 Capacitance C is periodically sampled rather than 100% tested. IN MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 Freescale Semiconductor 3 DC Electrical Specifications 3.1 PLL Power Filtering To further enhance noise isolation, an external filter is strongly recommended for PLL analog VDD pins. The filter shown in Figure 1 should be connected between the board VDD and the PLL VDD pins. The resistor and capacitors should be placed as close to the dedicated PLL VDD pin as possible. 10 W Board VDD PLL VDD Pin 10 µF 0.1 µF GND Figure 1. System PLL VDD Power Filter 3.2 USB Power Filtering To minimize noise, a external filters are required for each of the USB power pins. The filter shown in Figure 2 should be connected between the board EVDD or IVDD and each of the USB VDD pins. The resistor and capacitors should be placed as close to the dedicated USB VDD pin as possible. A separate filter circuit should be included for each USB VDD pin, a total of five circuits. R Board EVDD/IVDD USB VDD Pin 10 µF 0.1 µF GND Figure 2. USB VDD Power Filter NOTE In addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel with those shown. Table 5 lists the resistor values and supply voltages to be used in the circuit for each of the USB VDD pins. Table 5. USB Filter Circuit Values USB VDD Pin Nominal Voltage Resistor Value (R) USB_OSCVDD 3.3V 0Ω USBVDD 3.3V 0Ω USB_PHYVDD 3.3V 0Ω USB_OSCAVDD 1.5V 0Ω USB_PLLVDD 1.5V 10Ω MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 4 Freescale Semiconductor Supply Voltage Sequencing and Separation Cautions 4 Supply Voltage Sequencing and Separation Cautions DC Power Supply Voltage Figure 3 shows situations in sequencing the I/O VDD (EVDD), SDRAM VDD (SD VDD), PLL VDD (PLL VDD), and Core VDD (IVDD). EVDD, SD VDD (3.3V) 3.3V Supplies Stable 2.5V 1.5V SD VDD (2.5V) IVDD, PLL VDD 1 2 0 Time NOTES: 1. IVDD should not exceed EVDD, SD VDD or PLL VDD by more than 0.4V at any time, including power-up. 2. Recommended that IVDD/PLL VDD should track EVDD/SD VDD up to 0.9V, then separate for completion of ramps. 3. Input voltage must not be greater than the supply voltage (EVDD, SD VDD, IVDD, or PLL VDD) by more than 0.5V at any time, including during power-up. 4. Use 1 microsecond or slower rise time for all supplies. Figure 3. Supply Voltage Sequencing and Separation Cautions The relationship between SD VDD and EVDD is non-critical during power-up and power-down sequences. Both SD VDD (2.5V or 3.3V) and EVDD are specified relative to IVDD. 4.1 Power Up Sequence If EVDD/SD VDD are powered up with the IVDD at 0V, then the sense circuits in the I/O pads will cause all pad output drivers connected to the EVDD/SD VDD to be in a high impedance state. There is no limit on how long after EVDD/SD VDD powers up before IVDD must power up. IVDD should not lead the EVDD, SD VDD or PLL VDD by more than 0.4V during power ramp up, or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond to avoid turning on the internal ESD protection clamp diodes. MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 Freescale Semiconductor 5 Output Driver Capability and Loading The recommended power up sequence is as follows: 1. Use 1 microsecond or slower rise time for all supplies. 2. IVDD/PLL VDD and EVDD/SD VDD should track up to 0.9V, then separate for the completion of ramps with EVDD/SD VDD going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator. 4.2 Power Down Sequence If IVDDPLL VDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high impedance state. There is no limit on how long after IVDD and PLL VDD power down before EVDD or SD VDD must power down. IVDD should not lag EVDD, SD VDD, or PLL VDD going low by more than 0.4V during power down or there will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: 1. Drop IVDD/PLL VDD to 0V 2. Drop EVDD/SD VDD supplies 5 Output Driver Capability and Loading Table 6 lists values for drive capability and output loading. Table 6. I/O Driver Capability Signal Drive Output Capability Load (CL) SDRAMC (SDADDR[12:0], SDDATA[31:0], RAS, CAS, SDDM[3:0], SDWE, SDBA[1:0] 24 mA 15 pF SDRAMC DQS and clocks (SDDQS[3:0], SDRDQS, SDCLK[1:0], SDCLK[1:0], SDCKE) 24 mA 15 pF SDRAMC chip selects (SDCS[3:0]) 24 mA 15 pF FlexBus (AD[31:0], FBCS[5:0], ALE, R/W, BE/BWE[3:0], OE) 16 mA 20 pF FEC (EnMDIO, EnMDC, EnTXEN, EnTXD[3:0], EnTXER 8 mA 15 pF Timer (TOUT[3:0]) 8 mA 50 pF DACK[1:0] 8 mA 30 pF PSC (PSCnTXD[3:0], PSCnRTS/PSCnFSYNC, 8 mA 30 pF DSPI (DSPISOUT, DSPICS0/SS, DSPICS[2:3], DSPICS5/PCSS) 24 mA 50 pF PCI (PCIAD[31:0], PCIBG[4:1], PCIBG0/PCIREQOUT, PCIDEVSEL, PCICXBE[3:0], PCIFRM, PCIPERR, PCIRESET, PCISERR, PCISTOP, PCIPAR, PCITRDY, PCIIRDY 16 mA 50 pF I2C (SCL, SDA) 8 mA 50 pF BDM (PSTCLK, PSTDDATA[7:0], DSO/TDO, 8 mA 25 pF RSTO 8 mA 50 pF MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 6 Freescale Semiconductor PLL Timing Specifications 6 PLL Timing Specifications The specifications in Table 7 are for the CLKIN pin. Table 7. Clock Timing Specification Num Characteristic Min Max Units 15.15 33.3 ns C1 Cycle time C2 Rise time (20% of Vdd to 80% of vdd) — 2 ns C3 Fall time (80% of Vdd to 20% of Vdd) — 2 ns C4 Duty cycle (at 50% of Vdd) 40 60 % C1 CLKIN C4 C4 C2 C3 Input Clock Timing Diagram Table 8 shows the supported PLL encodings. Table 8. MCF547X Divide Ratio Encodings CLKIN—PCI and FlexBus Clock Ratio Frequency Range (MHz) AD[12:8]1 Internal XLB, SDRAM Bus, and PSTCLK Frequency Range (MHz) Core Frequency Range (MHz) 00011 1:2 41.6–66.66 83.33–133.33 166.66–266.66 00101 1:2 25.0–44.4 50.0–88.8 100.0–177.66 01111 1:4 25.0–33.3 100–133.33 200–266.66 NOTES: 1 All other values of AD[12:8] are reserved. Figure 4 correlates CLKIN, internal bus, and core clock frequencies for the 1x–4x multipliers. CLKIN Internal Clock Core Clock 2x 25.0 2x 50.0 66.66 4x 50 100.0 70 266.66 2x 25.0 33.33 25 100.0 133.33 30 CLKIN (MHz) 50 70 90 110 Internal Clock (MHz) 133.33 130 266.66 200.0 60 80 100 120 140 160 180 200 220 240 260 Core Clock (MHz) Figure 4. CLKIN, Internal Bus, and Core Clock Ratios MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 Freescale Semiconductor 7 Reset Timing Specifications 7 Reset Timing Specifications Table 9 lists specifications for the reset timing parameters shown in Figure 5 Table 9. Reset Timing Specification 66 MHz CLKIN Num Characteristic Units Min Max R1 1 Valid to CLKIN (setup) 8 — nS R2 CLKIN to invalid (hold) 1.0 — nS R3 RSTI to invalid (hold) 1.0 — nS NOTES: 1 RSTI and FlexBus data lines are synchronized internally. Setup and hold times must be met only if recognition on a particular clock is required. Figure 5 shows reset timing for the values in Table 9. CLKIN R1 RSTI R2 Mode Select FlexBus R1 R3 NOTE: Mode selects are registered on the rising clock edge before the cycle in which RSTI is recognized as being negated. Figure 5. Reset Timing 8 FlexBus A multi-function external bus interface called FlexBus is provided on the MCF5472 with basic functionality to interface to slave-only devices up to a maximum bus frequency of 66 MHz. It can be directly connected to asynchronous or synchronous devices such as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional circuitry. For asynchronous devices, a simple chip-select based interface can be used. The FlexBus interface has six general purpose chip-selects (FBCS[5:0]). Chip-select FBCS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word (16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM / flash memories. MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 8 Freescale Semiconductor FlexBus 8.1 FlexBus AC Timing Characteristics The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the system clock. Table 10. FlexBus AC Timing Specifications Num Characteristic Frequency of Operation Min Max Unit Notes 30 66 Mhz 1 15.15 33.33 ns 2 FB1 Clock Period (CLKIN) FB2 Address, Data, and Control Output Valid (AD[31:0], FBCS[5:0], R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST) — 7.0 ns 3 FB3 Address, Data, and Control Output Hold ((AD[31:0], FBCS[5:0], R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST) 1 — ns 3, 4 FB4 Data Input Setup 3.5 — ns FB5 Data Input Hold 0 — ns FB6 Transfer Acknowledge (TA) Input Setup 4 — ns FB7 Transfer Acknowledge (TA) Input Hold 0 — ns FB8 Address Output Valid (PCIAD[31:0]) — 7.0 ns 5 FB9 Address Output Hold (PCIAD[31:0]) 0 — ns 5 NOTES: 1 The frequency of operation is the same as the PCI frequency of operation. The MCF547X supports a single external reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI. 2 Max cycle rate is determined by CLKIN and how the user has the system PLL configured. 3 Timing for chip selects only applies to the FBCS[5:0] signals. Please see Section 9.2, “DDR SDRAM AC Timing Characteristics” for SDCS[3:0] timing. 4 The FlexBus supports programming an extension of the address hold. Please consult the MCF547X specification manual for more information. 5 These specs are used when the PCIAD[31:0] signals are configured as 32-bit, non-muxed FlexBus address signals. MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 Freescale Semiconductor 9 FlexBus CLKIN FB1 FB3 AD[X:0] A[X:0] FB2 AD[31:Y] FB5 A[31:Y] DATA R/W FB4 ALE TSIZ[1:0] TSIZ[1:0] FBCSn, BE/BWEn FB7 OE FB6 TA Figure 6. FlexBus Read Timing MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 10 Freescale Semiconductor SDRAM Bus CLKIN FB1 FB3 AD[X:0] A[X:0] FB2 AD[31:Y] FB3 A[31:Y] DATA R/W ALE TSIZ[1:0] TSIZ[1:0] FBCSn, BE/BWEn FB7 OE FB6 TA Figure 7. FlexBus Write Timing 9 SDRAM Bus The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time. The SDRAM controller uses SSTL2 and SSTL3 I/O drivers. Both SSTL drive modes are programmable for either Class I or Class II drive strength. 9.1 SDR SDRAM AC Timing Characteristics The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the memory bus clock, when operating in SDR mode on write cycles and relative to SDR_DQS on read cycles. The MCF547x SDRAM controller is a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must still be supplied to the MCF547x for each data beat of an SDR read. The MCF547x accomplishes this by asserting a signal called SDR_DQS during read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the SDR_DQS signal and its usage. MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 Freescale Semiconductor 11 SDRAM Bus Table 11. SDR Timing Specifications Symbol Characteristic Frequency of Operation Min Max Unit Notes 83 133 Mhz 1 7.52 12 ns 2 SD1 Clock Period (tCK) SD2 Clock Skew (tSK) SD3 Pulse Width High (tCKH) 0.45 0.55 SDCLK 3 SD4 Pulse Width Low (tCKL) 0.45 0.55 SDCLK 4 SD5 Address, CKE, CAS, RAS, WE, BA, CS - Output Valid (tCMV) 0.5 × SDCLK + 1.0ns ns SD6 Address, CKE, CAS, RAS, WE, BA, CS - Output Hold (tCMH) SD7 SDRDQS Output Valid (tDQSOV) SD8 SDDQS[3:0] input setup relative to SDCLK (tDQSIS) SD9 SDDQS[3:0] input hold relative to SDCLK (tDQSIH) SD10 Data Input Setup relative to SDCLK (reference only) (tDIS) 0.25 × SDCLK ns SD11 Data Input Hold relative to SDCLK (reference only) (tDIH) 1.0 ns SD12 Data and Data Mask Output Valid (tDV) SD13 Data and Data Mask Output Hold (tDH) TBD 2.0 0.25 × SDCLK ns Self timed ns 5 0.40 × SDCLK ns 6 Does not apply. 0.5 SDCLK fixed width. 0.75 × SDCLK +0.500ns 1.5 7 8 ns ns NOTES: 1 The frequency of operation is either 2x or 4x the CLKIN frequency of operation. The MCF547X supports a single external reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI, but SDRAM clock operates at the same frequency as the internal bus clock. Please see the PLL chapter of the MCF547X Specification for more information on setting the SDRAM clock rate. 2 SDCLK is one SDRAM clock in (ns). 3 Pulse width high plus pulse width low cannot exceed min and max clock period. 4 Pulse width high plus pulse width low cannot exceed min and max clock period. 5 SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This is a guideline only. Subtle variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each data beat. 6 SDR_DQS is designed to pulse 0.25 clock before the rising edge of the memory clock. This spec is a guideline only. Subtle variation from this guideline is expected. SDR_DQS will only pulse during a read cycle and one pulse will occur for each data beat. 7 The SDR_DQS pulse is designed to be 0.5 clock in width. The timing of the rising edge is most important. The falling edge does not affect the memory controller. 8 Since a read cycle in SDR mode still uses the DQS circuit within the MCF547X, it is most critical that the data valid window be centered 1/4 clk after the rising edge of DQS. Ensuring that this happens will result in successful SDR reads. The input setup spec is just provided as guidance. MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 12 Freescale Semiconductor SDRAM Bus SD2 SD3 SD1 SDCLK0 SD4 SD2 SDCLK1 SD6 SDCSn,SDWE, RAS, CAS CMD SD5 SDADDR, SDBA[1:0] ROW COL SD12 SDDM SD13 SDDATA WD1 WD2 WD3 WD4 Figure 8. SDR Write Timing MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 Freescale Semiconductor 13 SDRAM Bus SD1 SD2 SDCLK0 SD2 SDCLK1 SD6 SDCSn,SDWE, RAS, CAS CMD 3/4 MCLK Reference SD5 SDADDR, SDBA[1:0] ROW COL tDQS SDDM SD7 SDRQS (Measured at Output Pin) Board Delay SDDQS SD9 (Measured at Input Pin) Board Delay SD8 Delayed SDCLK SD10 SDDATA form Memories WD1 NOTE: Data driven from memories relative to delayed memory clock. WD2 WD3 WD4 SD11 Figure 9. SDR Read Timing 9.2 DDR SDRAM AC Timing Characteristics When using the DDR SDRAM controller, the following timing numbers must be followed to properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte lanes. Table 12shows the DDR clock crossover specifications. Table 12. DDR Clock Crossover Specifications Symbol Characteristic Min Max Unit VMP Clock output mid-point voltage 1.05 1.45 V VOUT Clock output voltage level –0.3 SD_VDD + 0.3 V VID Clock output differential voltage (peak to peak swing) 0.7 SD_VDD + 0.6 V 1.05 1.45 V VIX Clock crossing point voltage1 NOTES: 1 The clock crossover voltage is only guaranteed when using the highest drive strength option for the SDCLK[1:0] and SDCLK[1:0] signals. MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 14 Freescale Semiconductor SDRAM Bus SDCLK VIX VMP VIX VID SDCLK Figure 10. DDR Clock Timing Diagram Table 13. DDR Timing Specifications Symbol Characteristic Frequency of Operation Min Max Unit Notes 83 133 MHz 1 DD1 Clock Period (tCK) 7.52 12 ns 2 DD2 Pulse Width High (tCKH) 0.45 0.55 SDCLK 3 DD3 Pulse Width Low (tCKL) 0.45 0.55 SDCLK 4 DD4 Address, SDCKE, CAS, RAS, WE, SDBA, SDCS—Output Valid (tCMV) — 0.5 × SDCLK + 1.0 ns ns 5 DD5 Address, SDCKE, CAS, RAS, WE, SDBA, SDCS—Output Hold (tCMH) 2.0 — ns DD6 Write Command to first DQS Latching Transition (tDQSS) — 1.25 SDCLK DD7 Data and Data Mask Output Setup (DQ−>DQS) Relative to DQS (DDR Write Mode) (tQS) 1.0 — ns DD8 Data and Data Mask Output Hold (DQS−>DQ) Relative to DQS (DDR Write Mode) (tQH) 1.0 DD9 Input Data Skew Relative to DQS (Input Setup) (tIS) DD10 Input Data Hold Relative to DQS (tIH) DD11 6 7 — ns 8 1 ns 9 0.25 × SDCLK + 0.5ns — ns 10 DQS falling edge to SDCLK rising (output setup time) (tDSS) 0.5 — ns DD12 DQS falling edge from SDCLK rising (output hold time) (tDSH) 0.5 — ns DD13 DQS input read preamble width (tRPRE) 0.9 1.1 SDCLK DD14 DQS input read postamble width (tRPST) 0.4 0.6 SDCLK DD15 DQS output write preamble width (tWPRE) 0.25 — SDCLK DD16 DQS output write postamble width (tWPST) 0.4 0.6 SDCLK NOTES: 1 The frequency of operation is either 2x or 4x the CLKIN frequency of operation. The MCF547X supports a single external reference clock (CLKIN). This signal defines the frequency of operation for both FlexBus and PCI, but SDRAM clock operates at the same frequency as the internal bus clock. Please see Section 2.2.6, “Reset Configuration Pins.” 2 SDCLK is one memory clock in (ns). 3 Pulse width high plus pulse width low cannot exceed max clock period. 4 Pulse width high plus pulse width low cannot exceed max clock period. 5 Command output valid should be 1/2 the memory bus clock (SDCLK) plus some minor adjustments for process, temperature, and voltage variations. 6 This specification relates to the required input setup time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3, SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0. 7 The first data beat will be valid before the first rising edge of SDDQS and after the SDDQS write preamble. The remaining data beats will be valid for each subsequent SDDQS edge. MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 Freescale Semiconductor 15 SDRAM Bus 8 This specification relates to the required hold time of today’s DDR memories. SDDATA[31:24] is relative to SDDQS3, SDDATA[23:16] is relative to SDDQS2, SDDATA[15:8] is relative to SDDQS1, and SDDATA[7:0] is relative SDDQS0. 9 Data input skew is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). 10 Data input hold is derived from each SDDQS clock edge. It begins with a SDDQS transition and ends when the first data line becomes invalid. DD1 DD2 SDCLK0 DD3 SDCLK1 SDCLK0 SDCLK1 DD5 SDCSn,SDWE, RAS, CAS CMD DD4 SDADDR, SDBA[1:0] DD6 ROW COL DD7 SDDM DD8 SDDQS DD7 SDDATA WD1 WD2 WD3 WD4 DD8 Figure 11. DDR Write Timing MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 16 Freescale Semiconductor PCI Bus DD1 DD2 SDCLK0 DD3 SDCLK1 SDCLK0 SDCLK1 CL=2 DD5 SDCSn,SDWE, RAS, CAS CMD CL=2.5 DD4 SDADDR, SDBA[1:0] ROW COL DQS Read Preamble SDDQS DD9 DQS Read Postamble DD10 SDDATA WD1 WD2 WD3 WD4 DQS Read DQS Read Preamble Postamble SDDQS WD1 WD2 WD3 WD4 SDDATA Figure 12. DDR Read Timing 10 PCI Bus The PCI bus on the MCF547x is PCI 2.2 compliant. The following timing numbers are mostly from the PCI 2.2 spec. Please refer to the PCI 2.2 spec for a more detailed timing analysis. Table 14. PCI Timing Specifications Num Characteristic Frequency of Operation Min Max Unit Notes 30 66 MHz 1 15.15 33.33 ns 2 P1 Clock Period (tCK) P2 Address, Data, and Command (33< PCI ≤ 66 Mhz)—Input Setup (tIS) 3.0 — ns P3 Address, Data, and Command (0 < PCI ≤ 33 Mhz)—Input Setup (tIS) 7.0 — ns P4 Address, Data, and Command (33-66 Mhz) - Output Valid (tDV) — 6.0 ns P5 Address, Data, and Command (0 -33 Mhz) - Output Valid (tDV) — 11.0 ns 3 MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 Freescale Semiconductor 17 Fast Ethernet AC Timing Specifications Table 14. PCI Timing Specifications (continued) Num Characteristic Min Max Unit Notes 4 P6 PCI signals (0 - 66 Mhz) - Output Hold (tDH) 0 — ns P7 PCI signals (0 - 66 Mhz) - Input Hold (tIH) 0 — ns 5 P8 PCI REQ/GNT (33 < PCI ≤ 66Mhz) - Output valid (tDV) — 6 ns 6 P9 PCI REQ/GNT (0 < PCI ≤ 33Mhz) - Output valid (tDV) — 12 ns P10 PCI REQ/GNT (33 < PCI ≤ 66Mhz) - Input Setup (tIS) — 5 ns P11 PCI REQ (0 < PCI ≤ 33Mhz) - Input Setup (tIS) 12 — ns P12 PCI GNT (0 < PCI ≤ 33Mhz) - Input Setup (tIS) 10 — ns NOTES: Please see Section 2.2.6, “Reset Configuration Pins,” for more information on setting the PCI clock rate. Also specific guidelines may need to be followed when operating the system PLL below certain frequencies. 2 Max cycle rate is determined by CLKIN and how the user has the system PLL configured. 3 All signals defined as PCI bused signals. Does not include PTP (point-to-point) signals. 4 PCI 2.2 spec does not require an output hold time. Although the MCF547X may provide a slight amount of hold, it is not required or guaranteed. 5 PCI 2.2 spec requires zero input hold. 6 These signals are defined at PTP (Point-to-point) in the PCI 2.2 spec. 1 P1 CLKIN P4 Output Valid/Hold P6 Output Valid P2 Input Setup/Hold Input Valid P7 Figure 13. PCI Timing 11 Fast Ethernet AC Timing Specifications 11.1 MII/7-WIRE Interface Timing Specs The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the EMAC_10_100 I/O signals. The following timing specs meet the requirements for both MII and 7-Wire style interfaces for a range of transceiver devices. If this interface is to be used with a specific transceiver device the timing specs may be altered to match that specific transceiver. MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 18 Freescale Semiconductor Fast Ethernet AC Timing Specifications Table 15. MII Receive Signal Timing Num Characteristic Min Max Unit M1 RXD[3:0], RXDV, RXER to RXCLK setup 5 — ns M2 RXCLK to RXD[3:0], RXDV, RXER hold 5 — ns M3 RXCLK pulse width high 35% 65% RXCLK period M4 RXCLK pulse width low 35% 65% RXCLK period Min Max Unit M3 RXCLK (Input) M1 M4 RXD[3:0] (Inputs) RXDV, RXER M2 Figure 14. MII Receive Signal Timing Diagram 11.2 MII Transmit Signal Timing Table 16. MII Transmit Signal Timing Num Characteristic M5 TXCLK to TXD[3:0], TXEN, TXER invalid 0 — ns M6 TXCLK to TXD[3:0], TXEN, TXER valid — 25 ns M7 TXCLK pulse width high 35% 65% TXCLK period M8 TXCLK pulse width low 35% 65% TXCLK period M7 TXCLK (Input) M5 M8 TXD[3:0] (Outputs) TXEN, TXER M6 Figure 15. MII Transmit Signal Timing Diagram MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 Freescale Semiconductor 19 Fast Ethernet AC Timing Specifications 11.3 MII Async Inputs Signal Timing (CRS, COL) Table 17. MII Transmit Signal Timing Num M9 Characteristic CRS, COL minimum pulse width Min Max Unit 1.5 — TX_CLK period CRS, COL M9 Figure 16. MII Async Inputs Timing Diagram 11.4 MII Serial Management Channel Timing (MDIO,MDC) Table 18. MII Serial Management Channel Signal Timing Num Characteristic Min Max Unit M10 MDC falling edge to MDIO output invalid (min prop delay) 0 — ns M11 MDC falling edge to MDIO output valid (max prop delay) — 25 ns M12 MDIO (input) to MDC rising edge setup 10 — ns M13 MDIO (input) to MDC rising edge hold 0 — ns M14 MDC pulse width high 40% 60% MDC period M15 MDC pulse width low 40% 60% MDC period M14 M15 MDC (Output) M10 MDIO (Output) M12 M11 MDIO (Input) M13 Figure 17. MII Serial Management Channel TIming Diagram MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 20 Freescale Semiconductor General Timing Specifications 12 General Timing Specifications Table 19 lists timing specifications for the GPIO, PSC, DREQ, DACK, and external interrupts. Table 19. General AC Timing Specifications Name Characteristic Min Max Unit G1 CLKIN high to signal output valid — 2 PSTCLK G2 CLKIN high to signal invalid (output hold) 0 — ns G3 Signal input pulse width 2 — PSTCLK 13 I2C Input/Output Timing Specifications Table 20 lists specifications for the I2C input timing parameters shown in Figure 18. Table 20. I2C Input Timing Specifications between SCL and SDA Num Characteristic Min Max Units I1 Start condition hold time 2 — Bus clocks I2 Clock low period 8 — Bus clocks I3 SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V) — 1 mS I4 Data hold time 0 — ns I5 SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V) — 1 mS I6 Clock high time 4 — Bus clocks I7 Data setup time 0 — ns I8 Start condition setup time (for repeated start condition only) 2 — Bus clocks I9 Stop condition setup time 2 — Bus clocks Table 21 lists specifications for the I2C output timing parameters shown in Figure 18. MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 Freescale Semiconductor 21 I2C Input/Output Timing Specifications Table 21. I2C Output Timing Specifications between SCL and SDA Num Characteristic Min Max Units I11 Start condition hold time 6 — Bus clocks I2 1 Clock low period 10 — Bus clocks I3 2 SCL/SDA rise time (VIL = 0.5 V to VIH = 2.4 V) — — µS I4 1 Data hold time 7 — Bus clocks I5 3 SCL/SDA fall time (VIH = 2.4 V to VIL = 0.5 V) — 3 ns I6 1 Clock high time 10 — Bus clocks I7 1 Data setup time 2 — Bus clocks I8 1 Start condition setup time (for repeated start condition only) 20 — Bus clocks Stop condition setup time 10 — Bus clocks I9 1 NOTES: 1 Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 21. The I2C interface is designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 21 are minimum values. 2 Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load. Figure 18 shows timing for the values in Table 20 and Table 21. I2 I6 I5 SCL I1 I3 I7 I4 I8 I9 SDA Figure 18. I2C Input/Output Timings MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 22 Freescale Semiconductor JTAG and Boundary Scan Timing 14 JTAG and Boundary Scan Timing Table 22. JTAG and Boundary Scan Timing Characteristics1 Num Symbol Min Max Unit J1 TCLK Frequency of Operation fJCYC DC 10 MHz J2 TCLK Cycle Period tJCYC 2 — tCK J3 TCLK Clock Pulse Width tJCW 15.15 — ns J4 TCLK Rise and Fall Times tJCRF 0.0 3.0 ns J5 Boundary Scan Input Data Setup Time to TCLK Rise tBSDST 5.0 — ns J6 Boundary Scan Input Data Hold Time after TCLK Rise tBSDHT 24.0 — ns J7 TCLK Low to Boundary Scan Output Data Valid tBSDV 0.0 15.0 ns J8 TCLK Low to Boundary Scan Output High Z tBSDZ 0.0 15.0 ns J9 TMS, TDI Input Data Setup Time to TCLK Rise tTAPBST 5.0 — ns J10 TMS, TDI Input Data Hold Time after TCLK Rise tTAPBHT 10.0 — ns J11 TCLK Low to TDO Data Valid tTDODV 0.0 15.0 ns J12 TCLK Low to TDO High Z tTDODZ 0.0 15.0 ns J13 TRST Assert Time tTRSTAT 100.0 — ns J14 TRST Setup Time (Negation) to TCLK High tTRSTST 10.0 — ns NOTES: 1 MTMOD is expected to be a static signal. Hence, it is not associated with any timing J2 J3 TCLK (Input) J3 VIH VIL J4 J4 Figure 19. Test Clock Input Timing MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 Freescale Semiconductor 23 JTAG and Boundary Scan Timing TCLK VIH VIL 5 Data Inputs 6 Input Data Valid 7 Output Data Valid Data Outputs 8 Data Outputs 7 Data Outputs Output Data Valid Figure 20. Boundary Scan (JTAG) Timing TCLK VIH VIL 9 TDI, TMS, BKPT 10 Input Data Valid 11 TDO Output Data Valid 12 TDO 11 TDO Output Data Valid Figure 21. Test Access Port Timing TCLK 14 TRST 13 Figure 22. TRST Timing Debug AC Timing Specifications MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 24 Freescale Semiconductor JTAG and Boundary Scan Timing Table 23 lists specifications for the debug AC timing parameters shown in Figure 24. Table 23. Debug AC Timing Specification 66 MHz Num Characteristic Units Min Max D1 PSTDDATA to PSTCLK setup 4.5 ns D2 PSTCLK to PSTDDATA hold 4.5 ns D3 DSI-to-DSCLK setup 1 PSTCLKs D4 1 DSCLK-to-DSO hold 4 PSTCLKs DSCLK cycle time 5 PSTCLKs D5 NOTES: 1 DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of CLKOUT. Figure 23 shows real-time trace timing for the values in Table 23. PSTCLK D1 D2 PSTDDATA[7:0] Figure 23. Real-Time Trace AC Timing Figure 24 shows BDM serial port AC timing for the values in Table 23. D5 DSCLK D3 DSI Current Next D4 DSO Past Current Figure 24. BDM Serial Port AC Timing MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 Freescale Semiconductor 25 DSPI Electrical Specifications 15 DSPI Electrical Specifications Table 24 lists DSPI timings. Table 24. DSPI Modules AC Timing Specifications Name Characteristic Min Max Unit 1 × tck 510 × tck ns DS1 DSPI_CS[3:0] to DSPI_CLK DS2 DSPI_CLK high to DSPI_DOUT valid. — 12 ns DS3 DSPI_CLK high to DSPI_DOUT invalid. (Output hold) 2 — ns DS4 DSPI_DIN to DSPI_CLK (Input setup) 10 — ns DS5 DSPI_DIN to DSPI_CLK (Input hold) 10 — ns The values in Table 24 correspond to Figure 25. DSPI_CS[3:0] DS1 DSPI_CLK DS2 DSPI_DOUT DS3 DS4 DS5 DSPI_DIN Figure 25. DSPI Timing 16 Timer Module AC Timing Specifications Table 25 lists timer module AC timings. Table 25. Timer Module AC Timing Specifications 0–66 MHz Name Characteristic Unit Min Max T1 TIN0 / TIN1 / TIN2 / TIN3 cycle time 3 — PSTCLK T2 TIN0 / TIN1 / TIN2 / TIN3 pulse width 1 — PSTCLK MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 26 Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK MCF547x Integrated Microprocessor Electrical Characteristics, Rev. 2 Freescale Semiconductor 27 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 [email protected] Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) [email protected] Japan: Freescale Semiconductor Japan Ltd. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.© Freescale Semiconductor, Inc. 2004. All rights reserved. MCF5475EC Rev. 2 10/2004