ETC MX25L8006E

MX25L8006E
MX25L1606E
MX25L8006E, MX25L1606E
DATASHEET
P/N: PM1548
1
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Contents
FEATURES................................................................................................................................................................... 5
GENERAL DESCRIPTION.......................................................................................................................................... 6
PIN CONFIGURATIONS .............................................................................................................................................. 7
PIN DESCRIPTION....................................................................................................................................................... 7
BLOCK DIAGRAM........................................................................................................................................................ 8
MEMORY ORGANIZATION.......................................................................................................................................... 9
Table 1-1. Memory Organization (8Mb)................................................................................................................ 9
Table 1-2. Memory Organization (16Mb).............................................................................................................. 9
DEVICE OPERATION................................................................................................................................................. 10
Figure 1. Serial Modes Supported........................................................................................................ 10
DATA PROTECTION................................................................................................................................................... 11
Table 2. Protected Area Sizes............................................................................................................................. 12
Table 3. 512 bit Secured OTP Definition............................................................................................................ 13
HOLD FEATURES...................................................................................................................................................... 14
Figure 2. Hold Condition Operation ........................................................................................................ 14
COMMAND DESCRIPTION........................................................................................................................................ 15
Table 4. COMMAND DEFINITION...................................................................................................................... 15
(1) Write Enable (WREN).................................................................................................................................... 16
(2) Write Disable (WRDI)..................................................................................................................................... 16
(3) Read Status Register (RDSR)....................................................................................................................... 16
(4) Write Status Register (WRSR)....................................................................................................................... 17
Table 5. Protection Modes................................................................................................................................... 18
(5) Read Data Bytes (READ).............................................................................................................................. 19
(6) Read Data Bytes at Higher Speed (FAST_READ)........................................................................................ 19
(7) Dual Output Mode (DREAD).......................................................................................................................... 19
(8) Sector Erase (SE).......................................................................................................................................... 19
(9) Block Erase (BE)............................................................................................................................................ 20
(10) Chip Erase (CE)........................................................................................................................................... 20
(11) Page Program (PP)...................................................................................................................................... 20
(12) Deep Power-down (DP)............................................................................................................................... 21
(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES) .............................................. 21
(14) Read Identification (RDID)........................................................................................................................... 22
(15) Read Electronic Manufacturer ID & Device ID (REMS)............................................................................... 22
Table 6. ID DEFINITIONS .................................................................................................................................. 23
(16) Enter Secured OTP (ENSO)........................................................................................................................ 23
(17) Exit Secured OTP (EXSO)........................................................................................................................... 23
(18) Read Security Register (RDSCUR)............................................................................................................. 24
Table 7. SECURITY REGISTER DEFINITION.................................................................................................... 24
P/N: PM1548
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REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
(19) Write Security Register (WRSCUR)............................................................................................................. 24
(20) Read DMC mode (RDDMC)........................................................................................................................ 25
Discoverable Memory Capabilities (DMC) Signature and Parameter Identification Data Values........................ 25
Parameter ID (0).................................................................................................................................................. 26
Parameter ID (1).................................................................................................................................................. 27
Parameter ID (2).................................................................................................................................................. 27
POWER-ON STATE.................................................................................................................................................... 28
ELECTRICAL SPECIFICATIONS............................................................................................................................... 29
ABSOLUTE MAXIMUM RATINGS...................................................................................................................... 29
Figure 3.Maximum Negative Overshoot Waveform............................................................................................ 29
CAPACITANCE TA = 25°C, f = 1.0 MHz.............................................................................................................. 29
Figure 4. Maximum Positive Overshoot Waveform............................................................................................. 29
Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL............................................................... 30
Figure 6. OUTPUT LOADING............................................................................................................................ 30
Table 8. DC CHARACTERISTICS....................................................................................................................... 31
Table 9. AC CHARACTERISTICS....................................................................................................................... 32
Timing Analysis......................................................................................................................................................... 33
Figure 7. Serial Input Timing............................................................................................................................... 33
Figure 8. Output Timing....................................................................................................................................... 33
Figure 9. Hold Timing.......................................................................................................................................... 34
Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1................................................ 34
Figure 11. Write Enable (WREN) Sequence (Command 06).............................................................................. 35
Figure 12. Write Disable (WRDI) Sequence (Command 04)............................................................................... 35
Figure 13. Read Status Register (RDSR) Sequence (Command 05)................................................................. 36
Figure 14. Write Status Register (WRSR) Sequence (Command 01)................................................................ 36
Figure 15. Read Data Bytes (READ) Sequence (Command 03)....................................................................... 36
Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B).................................................... 37
Figure 17. Dual Output Read Mode Sequence (Command 3B).......................................................................... 38
Figure 18. Sector Erase (SE) Sequence (Command 20)................................................................................... 38
Figure 19. Block Erase (BE) Sequence (Command D8).................................................................................... 38
Figure 20. Chip Erase (CE) Sequence (Command 60 or C7)............................................................................ 39
Figure 21. Page Program (PP) Sequence (Command 02)................................................................................. 39
Figure 22. Deep Power-down (DP) Sequence (Command B9).......................................................................... 39
Figure 23. Release from Deep Power-down (RDP) Sequence (Command AB)................................................ 40
Figure 24. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB).40
Figure 25. Read Identification (RDID) Sequence (Command 9F)....................................................................... 41
Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF)..................... 41
Figure 27. Power-up Timing................................................................................................................................ 42
Table 10. Power-Up Timing ................................................................................................................................ 42
RECOMMENDED OPERATING CONDITIONS.......................................................................................................... 43
P/N: PM1548
3
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 44
DATA RETENTION..................................................................................................................................................... 44
LATCH-UP CHARACTERISTICS............................................................................................................................... 44
ORDERING INFORMATION....................................................................................................................................... 45
PART NAME DESCRIPTION...................................................................................................................................... 46
PACKAGE INFORMATION......................................................................................................................................... 47
REVISION HISTORY ................................................................................................................................................. 53
P/N: PM1548
4
REV. 0.01, JAN. 28, 2010
PRELIMINARY
MX25L8006E
MX25L1606E
FEATURES
8M-BIT [x 1 / x 2] CMOS SERIAL FLASH
16M-BIT [x 1 / x 2] CMOS SERIAL FLASH
GENERAL
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 8M: 8,388,608 x 1 bit structure or 4,194,304 x 2 bits (Dual Output mode) structure
16M: 16,777,216 x 1 bit structure or 8,388,608 x 2 bits (Dual Output mode) structure
• 256 Equal Sectors with 4K byte each (8Mb)
512 Equal Sectors with 4K byte each (16Mb)
- Any Sector can be erased individually
• 16 Equal Blocks with 64K byte each (8Mb)
32 Equal Blocks with 64K byte each (16Mb)
- Any Block can be erased individually
• Program Capability
- Byte base
- Page base (256 bytes)
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast access time: 86MHz serial clock
- Serial clock of Dual Output mode : 80MHz
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page
- Byte program time: 9us (typical)
- Fast erase time: 60ms(typ.) /sector ; 0.7s(typ.) /block
• Low Power Consumption
- Low active read current: 16Mb: 25mA(max.) at 86MHz; 8Mb: 12mA(max.) at 86MHz
- Low active programming current: 20mA (max.)
- Low active erase current: 20mA (max.)
- Low standby current: 50uA (max.)
- Deep power-down mode 5uA (typical)
• Typical 100,000 erase/program cycles
• 20 years of data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP3-BP0(16Mb) ; BP2-BP0(8Mb) status bit defines the size of the area to be software protection against
program and erase instructions
- Additional 512 bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
P/N: PM1548
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REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
- REMS commands for 1-byte manufacturer ID and 1-byte device ID
• Support Discoverable Memory Capabilities (DMC) Signature
HARDWARE FEATURES
• PACKAGE
- 16-pin SOP (300mil), MX25L1606E only
- 8-pin SOP (150mil)
- 8-pin SOP (200mil)
- 8-pin PDIP (300mil)
- 8-land WSON (6x5mm)
- 8-land USON (4x4mm)
- All Pb-free devices are RoHS Compliant
GENERAL DESCRIPTION
The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.
The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access
to the device is enabled by CS# input.
When it is in Dual Output read mode, the SI pin and SO pin become SIO0 pin for data output.
The device provides sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page basis,
or word basis for Continuously program mode, and erase command is executes on sector, or block, or whole chip
basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
When the device is not in operation and CS# is high, it is put in standby mode.
The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after typical
100,000 program and erase cycles.
P/N: PM1548
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REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
PIN CONFIGURATIONS
16-PIN SOP (300mil) for MX25L1606E only
HOLD#
VCC
NC
NC
NC
NC
CS#
SO/SIO1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
8-PIN SOP (200mil, 150mil)
SCLK
SI/SIO0
NC
NC
NC
NC
GND
WP#
CS#
SO/SIO1
WP#
GND
1
2
3
4
8
7
6
5
8
7
6
5
VCC
HOLD#
SCLK
SI/SIO0
8-PIN PDIP (300mil)
8-LAND WSON (6x5mm), USON (4x4mm)
CS#
SO/SIO1
WP#
GND
1
2
3
4
VCC
HOLD#
SCLK
SI/SIO0
CS#
SO/SIO1
WP#
GND
1
2
3
4
8
7
6
5
VCC
HOLD#
SCLK
SI/SIO0
PIN DESCRIPTION
SYMBOL DESCRIPTION
CS#
Chip Select
Serial Data Input (for 1 x I/O)/ Serial Data
SI/SIO0
Input & Output (for Dual Output mode)
Serial Data Output (for 1 x I/O)/ Serial Data
SO/SIO1
Output (for Dual Output mode)
SCLK Clock Input
WP# Write protection
Hold, to pause the device without
HOLD#
deselecting the device
VCC
+ 3.3V Power Supply
GND Ground
P/N: PM1548
7
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
BLOCK DIAGRAM
X-Decoder
Address
Generator
Memory Array
Page Buffer
SI/SIO0
Data
Register
Y-Decoder
SO/SIO1
CS#,
WP#,
HOLD#
SCLK
SRAM
Buffer
Mode
Logic
State
Machine
Sense
Amplifier
HV
Generator
Clock Generator
Output
Buffer
P/N: PM1548
8
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
MEMORY ORGANIZATION
Table 1-2. Memory Organization (16Mb)
Table 1-1. Memory Organization (8Mb)
Block
15
14
Sector
255
:
240
239
:
224
Address Range
0FF000h
0FFFFFh
:
:
0F0000h
0F0FFFh
0EF000h
0EFFFFh
:
:
0E0000h
0E0FFFh
:
:
:
:
:
:
:
:
0
15
:
3
2
1
0
00F000h
:
003000h
002000h
001000h
000000h
00FFFFh
:
003FFFh
002FFFh
001FFFh
000FFFh
P/N: PM1548
Block
31
30
9
Sector
511
:
496
495
:
480
Address Range
1FF000h
1FFFFFh
:
:
1F0000h
1F0FFFh
1EF000h
1EFFFFh
:
:
1E0000h
1E0FFFh
:
:
:
:
:
:
:
:
0
15
:
3
2
1
0
00F000h
:
003000h
002000h
001000h
000000h
00FFFFh
:
003FFFh
002FFFh
001FFFh
000FFFh
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown in Figure 1.
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, DREAD, RES, REMS and RDDMC
the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out,
the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP, DP, ENSO,
EXSO,and WRSCUR, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
CPOL
CPHA
shift in
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
shift out
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM1548
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REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
DATA PROTECTION
The device is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only
occurs after successful completion of specific command sequences. The device also incorporates several features
to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Signature command (RES).
• Advanced Security Features: there are some protection and security features which protect content from inadvertent write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM):
MX25L8006E: use (BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The proected area
definition is shown as table of "Protected Area Sizes", the protected areas are more flexible which may protect
various area by setting value of BP0-BP2 bits.
MX25L1606E: use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected as read only. The proected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible which may
protect various area by setting value of BP0-BP3 bits.
Please refer to table of "protected area sizes".
- The Hardware Proteced Mode (HPM) uses WP# to protect the MX25L8006E:BP2-BP0 / MX25L1606E:BP3BP0 bits and SRWD bit.
P/N: PM1548
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REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Table 2. Protected Area Sizes
BP2
0
0
0
0
1
1
1
1
BP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
P/N: PM1548
Status bit
BP1
0
0
1
1
0
0
1
1
Status bit
BP2
BP1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
BP0
0
1
0
1
0
1
0
1
BP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Protect Level
MX25L8006E (8Mb)
0 (none)
1 (1block, block 15th)
2 (2blocks, block 14th-15th)
3 (3blocks, block 12th-15th)
4 (4blocks, block 8th-15th)
5 (All)
6 (All)
7 (All)
Protect Level
MX25L1606E (16Mb)
0 (none)
1 (1block, block 31th)
2 (2blocks, block 30th-31th)
3 (4blocks, block 28th-31th)
4 (8blocks, block 24th-31th)
5 (16blocks, block 16th-31th)
6 (32blocks, all)
7 (32blocks, all)
8 (32blocks, all)
9 (32blocks, all)
10 (16blocks, block 0th-15th)
11 (24blocks, block 0th-23th)
12 (28blocks, block 0th-27th)
13 (30blocks, block 0th-29th)
14 (31blocks, block 0th-30th)
15 (32blocks, all)
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REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
II. Additional 512 bit secured OTP for unique identifier: to provide 512 bit one-time program area for setting
device unique serial number - Which may be set by factory or system customer. Please refer to table 3. 512 bitsecured OTP definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 512 bit secured OTP by entering 512 bit secured OTP mode (with ENSO command), and going
through normal program procedure, and then exiting 512 bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "security register definition" for security
register bit definition and table of "512 bit secured OTP definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 512 bit secured OTP mode, array access is not allowed.
Table 3. 512 bit Secured OTP Definition
Address range
Size
Standard Factory Lock
Customer Lock
xxxx00~xxxx0F
128-bit
ESN (electrical serial number)
Determined by customer
xxxx10~xxxx3F
384-bit
N/A
P/N: PM1548
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REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
HOLD FEATURES
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal
while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start
until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial
Clock being low), see Figure 1.
Figure 2. Hold Condition Operation
CS#
SCLK
HOLD#
Hold
Condition
(standard)
Hold
Condition
(non-standard)
The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care
during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of
the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.
P/N: PM1548
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REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
COMMAND DESCRIPTION
Table 4. COMMAND DEFINITION
Command WREN (write WRDI (write
(byte)
enable)
disable)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
06 (hex)
sets the (WEL) resets the
write enable (WEL) write
latch bit
enable latch
bit
Command
(byte)
SE (sector
erase)
1st byte
2nd byte
3rd byte
4th byte
5th byte
20 (hex)
AD1
AD2
AD3
Action
04 (hex)
to erase the
selected
sector
BE (block
erase)
DREAD
FAST READ
(Double
(fast read
Output Mode
data)
command)
05 (hex)
01 (hex)
03 (hex)
0B (hex)
3B (hex)
AD1
AD1
AD1
AD2
AD2
AD2
AD3
AD3
AD3
Dummy
Dummy
to read out to write new n bytes read n bytes read n bytes read
the values values to the out until CS# out until CS# out by Dual
of the status status register goes high
goes high
Output until
register
CS# goes
high
RDSR
(read status
register)
WRSR
(write status
register)
READ (read
data)
CE (chip
erase)
PP (page
program)
DP (Deep
power down)
02 (hex)
AD1
AD2
AD3
B9 (hex)
RDP (Release
RES (read
from deep
electronic ID)
power down)
AB (hex)
AB (hex)
x
x
x
to program
the selected
page
enters deep
power down
mode
release from to read out
deep power 1-byte Device
down mode
ID
52 or D8 (hex) 60 or C7 (hex)
AD1
AD2
AD3
to erase the
selected
block
REMS (read
RDID
electronic
Command
(read identificmanufacturer
(byte)
ation)
& device ID)
1st byte
9F (hex)
90 (hex)
2nd byte
x
3rd byte
x
4th byte
ADD (Note 1)
5th byte
outputs
output the
JEDEC
Manufacturer
ID: 1-byte
ID & Device
Action
Manufact-urer
ID
ID & 2-byte
Device ID
to erase
whole chip
RDSCUR
WRSCUR
RDDMC
ENSO (enter EXSO (exit
(read security (write security
(Read DMC)
secured OTP) secured OTP)
register)
register)
B1 (hex)
C1 (hex)
2B (hex)
2F (hex)
to exit the 512 to read value
to set the
to enter
of security lock-down bit
the 512 bit bit secured
register
as "1" (once
secured OTP OTP mode
lock-down,
mode
cannot be
updated)
5A (hex)
AD1
AD2
AD3
Dummy
read DMC
mode
Note 1: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.
Note 2: It is not recommended to adopt any other code not in the command definition table, which will potentially
enter the hidden mode.
P/N: PM1548
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REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE,
BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit.
The sequence is shown as Figure 11.
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence is shown as Figure 12.
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
(3) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence is shown as Figure 13.
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. The program/erase command will be ignored and
not affect value of WEL bit if it is applied to a protected memory area.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3-BP0(16Mb) ; BP2-BP0(8Mb)) bits, non-volatile bits, indicate the
protected area(as defined in table 2) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP3-BP0(16Mb) ; BP2-BP0(8Mb)) bits requires the Write Status
Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page
Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits
set to 0, the CE instruction can be executed).
P/N: PM1548
16
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection
(WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and
WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no
longer accepted for execution and the SRWD bit and Block Protect bits (BP3-BP0(16Mb) ; BP2-BP0(8Mb)) are read
only.
Status Register for MX25L8006E
bit7
bit6
bit5
SRWD (status
register write
protect)
0
0
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
1=status
register write
disable
0
0
(note 1)
(note 1)
(note 1)
Non-volatile
bit
0
0
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
bit1
bit0
WEL
WIP
(write enable
(write in
latch)
progress bit)
1=write
1=write
operation
enable
0=not write 0=not in write
operation
enable
volatile bit
volatile bit
bit1
bit0
note 1: see the table "Protected Area Size".
Status Register for MX25L1606E
bit7
bit6
bit5
BP3
SRWD (status
(level of
register write
0
protected
protect)
block)
1=status
register write
disable
0
(note 1)
(note 1)
(note 1)
(note 1)
Non-volatile
bit
0
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
Non-volatile
bit
WEL
WIP
(write enable
(write in
latch)
progress bit)
1=write
1=write
enable
operation
0=not write 0=not in write
enable
operation
volatile bit
volatile bit
note 1: see the table "Protected Area Size".
(4) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3-BP0(16Mb) ; BP2-BP0(8Mb)) bits to define the protected area of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write
Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.
The sequence is shown as Figure 14.
The WRSR instruction has no effect on b6, b1, b0 of the status register.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
P/N: PM1548
17
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Table 5. Protection Modes
Mode
Software protection
mode (SPM)
Hardware protection
mode (HPM)
Status register condition
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP3-BP0(16Mb) ;
BP2-BP0(8Mb)
bits can be changed
The SRWD, BP3-BP0(16Mb) ;
BP2-BP0(8Mb) of
status register bits cannot be
changed
WP# and SRWD bit status
Memory
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
WP#=0, SRWD bit=1
The protected area
cannot
be program or erase.
Note:
1. As defined by the values in the Block Protect (BP3-BP0(16Mb) ; BP2-BP0(8Mb)) bits of the Status Register, as
shown in Table 1.
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change
the values of SRWD, BP3-BP0(16Mb) ; BP2-BP0(8Mb). The protected area, which is defined by BP3BP0(16Mb) ; BP2-BP0(8Mb) is at software protected mode (SPM).
- When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP3-BP0(16Mb) ; BP2-BP0(8Mb). The protected area, which is defined by BP3-BP0(16Mb) ; BP2BP0(8Mb), is at software protected mode (SPM)
Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected
mode (HPM). The data of the protected area is protected by software protected mode by BP3-BP0(16Mb) ; BP2BP0(8Mb) and hardware protected mode by the WP# to against data modification.
Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered.
If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use
software protected mode via BP3-BP0(16Mb) ; BP2-BP0(8Mb).
P/N: PM1548
18
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
(5) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence is shown as Figure 15.
(6) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence is shown as Figure 16.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle.
(7) Dual Output Mode (DREAD)
The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits(interleave on 1I/2O pins) shift out on the falling edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once writing DREAD instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence is shown as Figure 17.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
The DREAD only perform read operation. Program/Erase /Read ID/Read status/Read ID....operation do not support
DREAD throughputs.
(8) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE)
instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);
otherwise, the instruction will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence is shown as Figure 18.
P/N: PM1548
19
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP3-BP0(16Mb) ; BP2-BP0(8Mb) bits, the Sector Erase (SE) instruction will not be executed
on the page.
(9) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte sector erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE)
instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);
otherwise, the instruction will be rejected and not executed.
The sequence is shown as Figure 19.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP3-BP0(16Mb) ; BP2-BP0(8Mb) bits, the Block Erase (BE) instruction will not be executed on
the page.
(10) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the
sector (see table 3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte
boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence is shown as Figure 20.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is
protected by BP3-BP0(16Mb) ; BP2-BP0(8Mb) bits, the Chip Erase (CE) instruction will not be executed. It will be
only executed when BP3-BP0(16Mb) ; BP2-BP0(8Mb) all set to "0".
(11) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eight least significant address bits (A7-A0) are not all 0, all transmitted data which goes beyond the end of the current page are
programmed from the start address if the same page (from the address whose 8 least significant address bits (A7A0) are all 0). The CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the
byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not
executed. If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request
page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed
at the request address of the page without effect on other address of the same page.
The sequence is shown as Figure 21.
P/N: PM1548
20
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP3-BP0(16Mb) ; BP2-BP0(8Mb) bits, the Page Program (PP) instruction will not be executed.
(12) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode
requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep
power-down mode. It's different from Standby mode.
The sequence is shown as Figure 22.
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (those instructions allow the ID being reading out). When Powerdown, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction
code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay
of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the
device waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID
Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design,
please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed,
only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/
write cycle in progress.
The sequence is shown in Figure 23 and 24.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute
instruction.
The RDP instruction is for releasing from Deep Power Down Mode.
P/N: PM1548
21
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
(14) Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC
Manufacturer ID and Device ID are listed as table of "ID Definitions".
The sequence is shown as Figure 25.
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
(15) Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the
JEDEC assigned manufacturer ID and the specific device ID.
The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated by driving the CS# pin low and shift the instruction code "90h" or "EFh" followed by two dummy bytes and one
bytes address (A7~A0). After which, the Manufacturer ID for MXIC and the Device ID are shifted out on the falling
edge of SCLK with most significant bit (MSB) first as shown in figure 26. The Device ID values are listed in Table of
ID Definitions. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by
the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other.
The instruction is completed by driving CS# high.
P/N: PM1548
22
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Table 6. ID DEFINITIONS
Command Type
RDID Command
MX25L8006E
manufacturer ID
C2
RES Command
REMS
manufacturer ID
C2
memory type
20
electronic ID
13
device ID
13
memory
density
14
MX25L1606E
manufacturer ID
C2
manufacturer ID
C2
memory type
20
electronic ID
14
device ID
14
memory
density
15
(16) Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 512 bit secured OTP mode. The additional 512 bit secured OTP
is independent from main array, which may use to store unique serial number for system identifier. After entering the
Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data. The
Secured OTP data cannot be updated again once it is lock-down.
Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once security OTP is lock down, only read related commands are valid.
(17) Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 512 bit secured OTP mode.
P/N: PM1548
23
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
(18) Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The definition of the Security Register bits is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or
not. When it is "0", it indicates non- factory lock; "1" indicates factory- lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 512 bit Secured OTP
area cannot be update any more. While it is in 512 bit secured OTP mode, array access is not allowed.
Table 7. SECURITY REGISTER DEFINITION
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
x
x
x
x
x
x
LDSO
(indicate if
lock-down
Secrured OTP
indicator bit
0 = nonfactory
lock
1 = factory
lock
non-volatile bit
reserved
reserved
reserved
reserved
reserved
reserved
0 = not lockdown
1 = lock-down
(cannot
program/erase
OTP)
volatile bit
volatile bit
volatile bit
volatile bit
volatile bit
volatile bit
non-volatile bit
(19) Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN
instruction is not required before sending WRSCUR instruction. The WRSCUR instruction may change the values
of bit1 (LDSO bit) for customer to lock-down the 512 bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area cannot be updated any more.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
P/N: PM1548
24
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
(20) Read DMC mode (RDDMC)
MX25L8006E/1606E features DMC mode. Host system can retrieve the operating characteristics, structure and
vendor-specified information such as identifying information, memory size, operating voltages and timing information of this device by DMC mode. Writes the DMC Query command "5AH". The system can read DMC information
at the addresses given. A reset command is required to exit DMC mode and go back to ready array mode. The system can write the DMC Query command only when the device is in read mode. The DMC information at the address
given in DMC code table.
The identification data values in under TBD status. The sequence of issuing RDDMC instruction is CS# goes
low→send RDDMC (5A) instruction→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read DMC
code→CS# goes high.
Discoverable Memory Capabilities (DMC) Signature and Parameter Identification Data Values
Address (h)
(Byte Mode)
00h
01h
SPI Flash Discoverability Parameters (SFDP)
Signature
02h
03h
Minor Revision
04h
SFDP Revision
Major Revision
05h
Number of Parameter Header
06h
Reserved
07h
Parameter ID(0)
08h
Parameter Minor Revision
09h
Parameter Major Revision
0Ah
Parameter Length (in DW)
0Bh
Parameter Table Pointer
0Eh:0Ch
Reserved
0Fh
Parameter ID(1)
10h
Parameter Minor Revision
11h
Parameter Major Revision
12h
Parameter Length (in DW)
13h
Parameter Table Pointer
16h:14h
Reserved
17h
Parameter ID(2)
18h
Parameter Minor Revision
19h
Parameter Major Revision
1Ah
Parameter Length (in DW)
1Bh
Parameter Table Pointer
1Eh:1Ch
Reserved
1Fh
Description
P/N: PM1548
25
Address (Bit)
Data
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
23:00
31:24
7:0
15:8
23:16
31:24
23:00
31:24
7:0
15:8
23:16
31:24
23:00
31:24
53h
46h
44h
50h
00h
01h
02h
Reserved
00h
00h
01h
02h
000020h
Reserved
01h
00h
01h
Reserved
Reserved
Reserved
02h
00h
01h
02h
000030h
Reserved
Comment
Hex: 50444653
Start from 0x00
Start from 0x01
Start from 0x00
Start from 0x01
Based on Intel draft
Start from 0x00
Start from 0x01
Reserved
Address reserved
Start from 0x00
Start from 0x01
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Parameter ID (0)
Description
Address (h)
(Byte Mode)
Minimum Block/Sector Erase sizes
Address (Bit)
Data
01:00
01
02
1
Write Enable Command Required for
Writing to Volatile Status Registers
04:03
00
Reserved
07:05
Reserved
15:08
20h
16
1
18:17
00
19
0
20
0
21
0
23h
23:22
31:24
24h to 27h
31:00
Reserved
Reserved
00FFFFFFh
007FFFFFh
Write Granularity
4KB Erase Opcode
20h
21h
Supports Single Input Address Dual Output
Fast read
Number of bytes used in addressing for
flash array read, write and erase
Supports Dual Transfer Rate Clocking
22h
Supports Dual Input Address Dual Output
Fast read
Supports Quad Input Address Quad Output
Fast read
Reserved
Flash Size in bits
P/N: PM1548
26
Comment
00=reserved
01=4KB erase
10=reserved
11=64KB erase
0= 1Byte 1=64Byte
00=N/A
01=use 50h opcode
11=use 06h opcode
Reserved
4KB Erase Support
(00h=not supported)
0=not supported
1=support
00=3Byte 01=4Byte
10=reserved
11=reserved
0=not supported
1=support
0=not supported
1=support
0=not supported
1=support
Reserved
16Mb
8Mb
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Parameter ID (1)
Address (h)
(Byte Mode)
Undefined.
Address (Bit)
Data
Comment
31:00
Reserved
Reserved
Address (h)
(Byte Mode)
Address (Bit)
Data
Comment
Vcc Supply Maximum Voltage
31h:30h
15:00
3600h
Vcc Supply Minimum Voltage
33h:32h
23:15
2700h
01:00
03:02
00
00
04
0
05
1
07:06
Reserved
Parallel Mode Capable
08
0
Supports Single Input Address Quad Output
Fast read
09
0
Supports Continuous Program Mode
10
0
11
1
12
1
Supports Sector Group Protect
13
1
Supports independent Block Protect
14
0
Supports boot Sector Protect
15
0
Supports 64KB Block Erase
16
1
17
0
23:18
31:24
Reserved
Description
Reserved
Parameter ID (2)
Description
Vpp Supply Maximum Voltage
Vpp Supply Minimum Voltage
Supports Vio Function
34h
Supports HOLD# Function
Reserved
Supports Deep Power Down Mode
OTP Capable
Supports 32KB Block Erase
Reserved
P/N: PM1548
35h
36h
37h
27
200h=2.00V
280h=2.80V
360h=3.60V
165h=1.65V
225h=2.25V
235h=2.35V
270h=2.70V
00=not supported
00=not supported
0=not supported
1=support
0=not supported
1=support
reserved
0=not supported
1=support
0=not supported
1=support
0=not supported
1=support
0=not supported
1=support
0=not supported
1=support
0=not supported
1=support
0=not supported
1=support
0=not supported
1=support
0=not supported
1=support
0=not supported
1=support
Reserved
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
POWER-ON STATE
The device is at below states when power-up:
- Standby mode ( please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the figure of "power-up timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended.(generally around 0.1uF)
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
P/N: PM1548
28
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient Operating Temperature
Industrial grade
-40°C to 85°C
Storage Temperature
-55°C to 125°C
Applied Input Voltage
-0.5V to 4.6V
Applied Output Voltage
-0.5V to 4.6V
VCC to Ground Potential
-0.5V to 4.6V
NOTICE:
1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended period may affect reliability.
2.Specifications contained within the following tables are subject to change.
3.During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 3 and 4.
Figure 3.Maximum Negative Overshoot Waveform
20ns
Figure 4. Maximum Positive Overshoot Waveform
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
CAPACITANCE TA = 25°C, f = 1.0 MHz
SYMBOL
CIN
COUT
P/N: PM1548
PARAMETER
Input Capacitance
Output Capacitance
MIN.
TYP
29
MAX.
6
8
UNIT
pF
pF
CONDITIONS
VIN = 0V
VOUT = 0V
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing referance level
0.8VCC
0.2VCC
Output timing referance level
0.7VCC
AC
Measurement
Level
0.3VCC
0.5VCC
Note: Input pulse rise and fall time are <5ns
Figure 6. OUTPUT LOADING
DEVICE UNDER
TEST
2.7K ohm
CL
6.2K ohm
+3.3V
DIODES=IN3064
OR EQUIVALENT
CL=30pF/15pF Including jig capacitance
P/N: PM1548
30
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Table 8. DC CHARACTERISTICS
SYMBOL PARAMETER
Notes
MIN.
TYP.
MAX.
UNITS TEST CONDITIONS
ILI
Input Load Current
1
±2
uA
VCC = VCC Max,
VIN = VCC or GND
ILO
Output Leakage Current
1
±2
uA
VCC = VCC Max,
VIN = VCC or GND
ISB1
VCC Standby Current
1
50
uA
VIN = VCC or GND,
CS# = VCC
ISB2
Deep Power-down
Current
ICC1
VCC Read
8Mb
5
10
uA
16Mb
5
20
uA
8Mb
1
12
mA
16Mb
1
25
mA
8Mb
1
12
mA
16Mb
1
20
mA
8Mb
1
4
mA
16Mb
1
10
mA
ICC2
VCC Program Current (PP)
1
20
mA
ICC3
VCC Write Status
Register (WRSR)
Current
8Mb
1
15
mA
16Mb
1
20
mA
ICC4
VCC Sector Erase
Current (SE)
8Mb
1
15
mA
16Mb
1
20
mA
ICC5
VCC Chip Erase Current (CE)
1
20
mA
VIN = VCC or GND,
CS# = VCC
f=86MHz
fT=80MHz (2 x I/O read)
SCLK=0.1VCC/0.9VCC,
SO=Open
f=66MHz,
SCLK=0.1VCC/0.9VCC,
SO=Open
f=33MHz,
SCLK=0.1VCC/0.9VCC,
SO=Open
Program in Progress,
CS# = VCC
Program status register
in progress, CS#=VCC
Erase in Progress,
CS#=VCC
Erase in Progress,
CS#=VCC
VIL
Input Low Voltage
-0.5
0.3VCC
V
VIH
Input High Voltage
0.7VCC
VCC+0.4
V
VOL
Output Low Voltage
0.4
V
IOL = 1.6mA
VOH
Output High Voltage
V
IOH = -100uA
VCC-0.2
Notes :
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Not 100% tested.
P/N: PM1548
31
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Table 9. AC CHARACTERISTICS
Symbol
fSCLK
fRSCLK
fTSCLK
tCH(1)
tCL(1)
tCLCH(2)
tCHCL(2)
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tSHQZ(2)
tCLQV
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tHHQX(2)
tHLQZ(2)
tWHSL(4)
tSHWL (4)
tDP(2)
tRES1(2)
tRES2(2)
tW
tBP
tPP
tSE
tBE
tCE
Alt. Parameter
Min.
Clock Frequency for the following instructions:
fC FAST_READ, PP, SE, BE, CE, DP, RES, RDP,
10KHz
WREN, WRDI, RDID, RDSR, WRSR
fR Clock Frequency for READ instructions
10KHz
fT Clock Frequency for 2READ instructions
10KHz
fC=86MHz
5.5
tCLH Clock High Time
fR=33MHz
13
fC=86MHz
5.5
tCLL Clock Low Time
fR=33MHz
13
Clock Rise Time (3) (peak to peak)
0.1
Clock Fall Time (3) (peak to peak)
0.1
tCSS CS# Active Setup Time (relative to SCLK)
5
CS# Not Active Hold Time (relative to SCLK)
5
tDSU Data In Setup Time
2
tDH Data In Hold Time
5
CS# Active Hold Time (relative to SCLK)
5
CS# Not Active Setup Time (relative to SCLK)
5
Read
15
tCSH CS# Deselect Time
Write
40
tDIS Output Disable Time
tV Clock Low to Output Valid, Loading 30pF/15pF
tHO Output Hold Time
0
HOLD# Setup Time (relative to SCLK)
5
HOLD# Hold Time (relative to SCLK)
5
HOLD Setup Time (relative to SCLK)
5
HOLD Hold Time (relative to SCLK)
5
tLZ HOLD to Output Low-Z
tHZ HOLD# to Output High-Z
Write Protect Setup Time
20
Write Protect Hold Time
100
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic Signature
Read
CS# High to Standby Mode with Electronic Signature
Read
Write Status Register Cycle Time
Byte-Program
Page Program Cycle Time
Sector Erase Cycle Time
Block Erase Cycle Time
8Mb
Chip Erase Cycle Time
16Mb
Typ.
Max.
Unit
86
MHz
33
80
10
MHz
MHz
ns
ns
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
8.8
us
8.8
us
100
300
5
300
2
15
30
ms
us
ms
ms
s
s
s
6
8/6
6
6
40
9
1.4
60
0.7
7
14
Notes:
1. tCH + tCL must be greater than or equal to 1/ fC. For Fast Read, tCL/tCH=5.5/5.5.
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. Test condition is shown as Figure 5.
P/N: PM1548
32
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Timing Analysis
Figure 7. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB
MSB
SI
High-Z
SO
Figure 8. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQX
tCL
tCLQV
tSHQZ
tCLQX
LSB
SO
tQLQH
tQHQL
SI
P/N: PM1548
ADDR.LSB IN
33
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Figure 9. Hold Timing
CS#
tHLCH
tCHHL
tHHCH
SCLK
tCHHH
tHLQZ
tHHQX
SO
HOLD#
* SI is "don't care" during HOLD operation.
Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
01
SI
SO
P/N: PM1548
High-Z
34
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Figure 11. Write Enable (WREN) Sequence (Command 06)
CS#
1
0
2
3
4
5
6
7
SCLK
Command
SI
06
High-Z
SO
Figure 12. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
SO
P/N: PM1548
04
High-Z
35
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Figure 13. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
05
SI
Status Register Out
High-Z
SO
7
6
5
4
3
2
Status Register Out
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 14. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
SI
Status
Register In
01
7
5
4
3
2
0
1
MSB
High-Z
SO
6
Figure 15. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
command
SI
03
24-Bit Address
23 22 21
3
2
1
0
MSB
SO
Data Out 1
High-Z
7
6
5
4
3
2
Data Out 2
1
0
7
MSB
P/N: PM1548
36
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Figure 16. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24 BIT ADDRESS
23 22 21
0B
3
2
1
0
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
SO
7
6
5
3
2
1
0
7
MSB
MSB
P/N: PM1548
4
37
6
5
4
3
2
1
0
7
MSB
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Figure 17. Dual Output Read Mode Sequence (Command 3B)
CS#
0
1
2
3
4
5
6
7
8
9 10 11
39 40 41 42 43
30 31 32
SCLK
8 Bit Instruction
SO/SO1
address
bit23, bit22, bit21...bit0
3B(hex)
SI/SO0
8 dummy
cycle
24 BIT Address
dummy
High Impedance
Data Output
data
bit6, bit4, bit2...bit0, bit6, bit4....
data
bit7, bit5, bit3...bit1, bit7, bit5....
Figure 18. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
24 Bit Address
Command
SI
23 22
20
2
1
0
MSB
Note: SE command is 20(hex).
Figure 19. Block Erase (BE) Sequence (Command D8)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24 Bit Address
23 22
D8
2
1
0
MSB
Note: BE command is D8(hex).
P/N: PM1548
38
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Figure 20. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
60 or C7
Note: CE command is 60(hex) or C7(hex).
Figure 21. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
1
0
7
6
5
3
2
1
0
2079
2
2078
3
2077
23 22 21
02
SI
Data Byte 1
2076
24-Bit Address
2075
Command
4
1
0
MSB
MSB
2074
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
CS#
SCLK
Data Byte 2
7
SI
6
5
4
3
Data Byte 3
2
0
1
MSB
7
6
5
4
3
2
Data Byte 256
1
0
MSB
7
6
5
4
3
2
MSB
Figure 22. Deep Power-down (DP) Sequence (Command B9)
CS#
0
1
2
3
4
5
6
tDP
7
SCLK
Command
SI
B9
Stand-by Mode
P/N: PM1548
39
Deep Power-down Mode
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Figure 23. Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
tRES1
7
SCLK
Command
SI
AB
High-Z
SO
Deep Power-down Mode
Stand-by Mode
Figure 24. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
SI
AB
tRES2
3 Dummy Bytes
23 22 21
3
2
1
0
MSB
SO
Electronic Signature Out
High-Z
7
6
5
4
3
2
1
0
MSB
Deep Power-down Mode
P/N: PM1548
40
Stand-by Mode
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Figure 25. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
Command
SI
9F
Manufacturer Identification
High-Z
SO
7
6
5
3
2
1
MSB
Device Identification
0 15 14 13
3
2
1
0
MSB
Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF)
CS#
0
1
2
3
4
5
6
7
8
9 10
SCLK
Command
SI
2 Dummy Bytes
15 14 13
90
3
2
1
0
High-Z
SO
CS#
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
ADD (1)
SI
7
6
5
4
3
2
1
0
Manufacturer ID
SO
7
6
5
4
3
2
1
Device ID
0
7
6
5
4
3
MSB
MSB
2
1
0
7
MSB
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first
(2) Instruction is either 90(hex) or EF(hex).
P/N: PM1548
41
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Figure 27. Power-up Timing
VCC
VCC(max)
Chip Selection is Not Allowed
VCC(min)
Device is fully accessible
tVSL
time
Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.
Table 10. Power-Up Timing
Symbol
Parameter
Min.
tVSL(1)
VCC(min) to CS# low
200
Max.
Unit
us
Note: 1. The parameter is characterized only.
P/N: PM1548
42
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
VCC
VCC(min)
GND
tSHSL
tVR
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
LSB IN
MSB IN
SI
High Impedance
SO
Figure A. AC Timing at Device Power-Up
Symbol
Parameter
tVR
VCC Rise Time
Notes
Min.
Max.
Unit
1
20
500000
us/V
Notes :
1.Sampled, not 100% tested.
2.For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"AC CHARACTERISTICS" table.
P/N: PM1548
43
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
ERASE AND PROGRAMMING PERFORMANCE
PARAMETER
TYP. (1)
Max. (2)
UNIT
Write Status Register Time
40
100
ms
Sector Erase Time
60
300
ms
Block Erase Time
0.7
2
s
8Mb
7
15
s
16Mb
14
30
s
9
300
us
1.4
5
ms
Chip Erase Time
Min.
Byte Program Time (via page program command)
Page Program Time
Erase/Program Cycle
100,000
cycles
Note:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern.
2. Under worst conditions of 85°C and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.
4. Erase/Program cycles comply with JEDEC JESD-47E & A117A standard.
DATA RETENTION
PARAMETER
Condition
Min.
Data retention
55˚C
20
Max.
UNIT
years
LATCH-UP CHARACTERISTICS
MIN.
MAX.
Input Voltage with respect to GND on all power pins, SI, CS#
-1.0V
2 VCCmax
Input Voltage with respect to GND on SO
-1.0V
VCC + 1.0V
-100mA
+100mA
Current
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N: PM1548
44
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
ORDERING INFORMATION
8Mb
CLOCK
(MHz)
OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (uA)
Temperature
MX25L8006EM1I-12G
86
12
50
-40°C~85°C
MX25L8006EM2I-12G
86
12
50
-40°C~85°C
MX25L8006EPI-12G
86
12
50
-40°C~85°C
MX25L8006EZNI-12G
86
12
50
-40°C~85°C
MX25L8006EZUI-12G
86
12
50
-40°C~85°C
CLOCK
(MHz)
OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (uA)
Temperature
MX25L1606EMI-12G
86
25
50
-40°C~85°C
MX25L1606EM1I-12G
86
25
50
-40°C~85°C
MX25L1606EM2I-12G
86
25
50
-40°C~85°C
MX25L1606EPI-12G
86
25
50
-40°C~85°C
MX25L1606EZNI-12G
86
25
50
-40°C~85°C
MX25L1606EZUI-12G
86
25
50
-40°C~85°C
PART NO.
PACKAGE
8-SOP
(150mil)
8-SOP
(200mil)
8-PDIP
(300mil)
8-WSON
(6x5mm)
8-USON
(4x4mm)
Remark
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
16Mb
PART NO.
P/N: PM1548
45
PACKAGE
16-SOP
(300mil)
8-SOP
(150mil)
8-SOP
(200mil)
8-PDIP
(300mil)
8-WSON
(6x5mm)
8-USON
(4x4mm)
Remark
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
PART NAME DESCRIPTION
MX 25
L 1606E
ZN
I
12 G
OPTION:
G: Pb-free
SPEED:
12: 86MHz
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
ZN: WSON (0.8mm package height)
ZU: USON (0.6mm package height)
M: 300mil 16-SOP
M1: 150mil 8-SOP
M2: 200mil 8-SOP
P: 300mil 8-PDIP
DENSITY & MODE:
8006E: 8Mb
1606E: 16Mb
TYPE:
L: 3V
DEVICE:
25: Serial Flash
P/N: PM1548
46
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
PACKAGE INFORMATION
P/N: PM1548
47
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
P/N: PM1548
48
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
P/N: PM1548
49
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
P/N: PM1548
50
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
P/N: PM1548
51
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
P/N: PM1548
52
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
REVISION HISTORY
Revision No.
0.01
P/N: PM1548
Description
Page
1. Document status: changed from Advanced Information to PreliminaryP5
2. Table 2. Protected Area Sizes: Modified content
P12
3. DATA PROTECTION-Block Lock Protection: Revised description
P11
4. Table 4. COMMAND DESCRIPTION: Modified RDDMC
P15
5. PERFORMANCE: Revised Low Power Consumption (low active read P5,31
current and low standby current)
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Date
JAN/28/2010
REV. 0.01, JAN. 28, 2010
MX25L8006E
MX25L1606E
Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which
the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft
and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims,
injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications.
Copyright© Macronix International Co., Ltd. 2009~2010. All Rights Reserved. Macronix, MXIC, MXIC Logo,
MX Logo, are trademarks or registered trademarks of Macronix International Co., Ltd. The names and brands
of other companies are for identification purposes only and may be claimed as the property of the respective
companies.
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