AZM AZ100LVEL16VVL+ Dual frequency ecl/pecl oscillator gain stage & buffer with enable Datasheet

ARIZONA MICROTEK, INC.
AZ100LVEL16VV
Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer with Enable
FEATURES
•
•
•
•
•
•
High Bandwidth for ≥1GHz
Similar Operation as AZ100EL16VR
except with selectable data input pairs
Operating Range of 3.0V to 5.5V
Minimizes External Components
Available in a 3x3mm MLP Package
S–Parameter (.s2p) and IBIS Model
Files Available on Arizona
Microtek Website
PACKAGE AVAILABILITY
PACKAGE
MLP 16 (3x3) RoHS
Compliant / Lead (Pb)
Free
DIE
1
2
3
PART NUMBER
AZ100LVEL16VVL+
AZ100LVEL16VVXP
MARKING
AZM+
16K
<Date Code>
N/A
NOTES
1,2
3
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape
& Reel.
Date code format: “Y” for year followed by “WW” for week.
Waffle Pack
DESCRIPTION
The AZ100LVEL16VV is a specialized oscillator gain stage with two selectable data input pairs and a high gain
output buffer including an enable. The QHG/Q̄HG outputs have a voltage gain several times greater than the Q/Q̄
outputs.
The AZ100LVEL16VV provides two selectable data input pairs that permit switching between two different
oscillator frequencies. When the select pin (SEL) is LOW or open (NC) data from the D0/D0
¯¯ is selected. When the
SEL pin is HIGH data from the D1/D1
¯¯ is selected. Allowing continuous oscillator operation, the (EN) enable works
with either data input pair. When EN is HIGH or open (NC), input data is passed to both sets of outputs. When EN
is LOW, the QHG/Q̄HG outputs will be forced LOW/HIGH respectively, while input data will continue to be passed to
the Q/Q̄ outputs. The EN and SEL inputs can be driven with an ECL/PECL signal or a full supply swing CMOS
type logic signal.
The AZ100LVEL16VV also provides a VBB with a 1.5mA sink/source current. Each data input is separately
connected to VBB with a 470Ω internal bias resistor. Bypassing VBB to ground with a 0.01 μF capacitor is
recommended.
Each Q/Q̄ output has a 4 mA on-chip pull-down current source. External resistors may also be used to increase
pull-down current of the Q/Q̄ to a maximum of 25mA each (includes a 4 mA on-chip current source).
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
AZ100LVEL16VV
PIN DESCRIPTION
PIN
D0/D0
¯¯ , D1/D1
¯¯
Q/Q̄
QHG/Q̄HG
VBB
SEL
EN
VCC
VEE
4mA EA.
FUNCTION
Data Inputs
Data Outputs
Data Outputs w/High Gain
Reference Voltage Output
Selects Data Inputs
Enable Input
Positive Supply
Negative Supply
Q
Q
D0
EN
D0
QHG
D1
QHG
D1
470
TRUTH TABLE
EN
High/
Open
High/
Open
Low
Low
SEL
Low/
Open
High
Low/
Open
High
VBB
Q
Q̄
QHG
Q̄HG
D0/D0
¯¯
D0/D0
¯¯
D0/D0
¯¯
D0/D0
¯¯
D1/D1
¯¯
D1/D1
¯¯
D1/D1
¯¯
D1/D1
¯¯
D0/D0
¯¯
D0/D0
¯¯
Low
High
D1/D1
¯¯
D1/D1
¯¯
Low
High
VEE
SEL
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
VCC
VI
VD/D̄
VEE
VI
VD/D̄
IOUT
TA
TSTG
1.
Characteristic
Rating
PECL Power Supply (VEE = 0V)
0 to +6.0
PECL Input Voltage (VEE = 0V)
0 to +6.0
PECL D/D̄ Input Voltage
(VEE = 0V)
±0.75 with respect to VBB
ECL Power Supply
(VCC = 0V)
-6.0 to 0
ECL Input Voltage
(VCC = 0V)
-6.0 to 0
ECL D/D̄ Input Voltage
(VCC = 0V)
±0.75 with respect to VBB
Output Current
--- Continuous
Q/Q̄
25
--- Surge
Q/Q̄
50
--- Continuous QHG/Q̄HG
50
--- Surge
QHG/Q̄HG
100
Operating Temperature Range
-40 to +85
Storage Temperature Range
-65 to +150
This voltage is the difference between each input pin (D/D̄) and VBB.
Unit
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
mA
°C
°C
100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND)
Symbol
VOH
VOL
Characteristic
0°C
25°C
85°C
Unit
Max
-835
-1555
Min
-1025
-1900
Max
-835
-1620
Min
-1025
-1900
Max
-835
-1620
Min
-1025
-1900
Max
-835
-1620
D/D̄
EN, SEL
-1165
-1165
-740
VCC
-1165
-1165
-740
VCC
-1165
-1165
-740
VCC
-1165
-1165
-740
VCC
mV
D/D̄
EN, SEL
-1900
VEE
-1390
-100
-1475
-1475
-1250
-1900
VEE
-1390
-100
-1475
-1475
-1250
-1900
VEE
-1390
-100
-1475
-1475
-1250
-1900
VEE
-1390
-100
-1475
-1475
-1250
mV
Output HIGH Voltage1
Output LOW Voltage1
Input HIGH Voltage
VIH
-40°C
Min
-1045
-1925
mV
mV
Input LOW Voltage
VIL
VBB
Reference Voltage
Input LOW Current EN/SEL
IIL
150
150
Input HIGH Current EN/SEL
IIH
IEE
Power Supply Current1
47
47
1.
Specified with Q/Q̄ open and each QHG/Q̄HG output terminated through a 50Ω resistor to VCC-2V.
April 2007 * REV - 9
www.azmicrotek.com
2
150
47
150
51
mV
μA
μA
mA
AZ100LVEL16VV
100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V)
Symbol
-40°C
Characteristic
1,2
VOH
VOL
Output HIGH Voltage
Output LOW Voltage1,2
Input HIGH Voltage1
VIH
D/D̄
EN/SEL
0°C
25°C
85°C
Unit
Min
2255
1375
Max
2465
1745
Min
2275
1400
Max
2465
1680
Min
2275
1400
Max
2465
1680
Min
2275
1400
Max
2465
1680
2135
2135
2560
VCC
2135
2135
2560
VCC
2135
2135
2560
VCC
2135
2135
2660
VCC
mV
1050
VEE
1910
-400
1825
18251
2050
1050
VEE
1910
-400
1825
1825
2050
1050
VEE
1910
-400
1825
1825
2050
1050
VEE
1910
-500
1825
1825
2050
mV
mV
mV
Input LOW Voltage1
VIL
D/D̄
EN/SEL
VBB
Reference Voltage1
Input LOW Current3 EN/SEL
IIL
Input HIGH Current EN/SEL
150
150
IIH
IEE
Power Supply Current
47
47
1.
Voltage levels vary 1:1 with VCC.
2.
Specified with Q/Q̄ open and each QHG/Q̄HG output terminated through a 50Ω resistor to VCC-2V.
3.
Specified with EN and SEL forced to VEE.
150
47
150
51
mV
μA
μA
mA
100K PECL DC Characteristics (VEE = GND, VCC = +5.0V)
Symbol
-40°C
Characteristic
Output HIGH Voltage1,2
Output LOW Voltage1,2
Input HIGH Voltage1
VOH
VOL
VIH
D/D̄
EN/SEL
0°C
25°C
85°C
Unit
Min
3955
3075
Max
4165
3445
Min
3975
3100
Max
4165
3380
Min
3975
3100
Max
4165
3380
Min
3975
3100
Max
4165
3380
3835
3835
4260
VCC
3835
3835
4260
VCC
3835
3835
4260
VCC
3835
3835
4260
VCC
mV
3100
VEE
3610
-1000
3525
3525
3750
3100
VEE
3610
-1000
3525
3525
3750
3100
VEE
3610
-1000
3525
3525
3750
3100
VEE
3610
-1200
3525
3525
3750
mV
mV
mV
Input LOW Voltage1
VIL
D/D̄
EN/SEL
VBB
Reference Voltage1
Input LOW Current3 EN/SEL
IIL
Input HIGH Current EN/SEL
150
150
IIH
IEE
Power Supply Current
47
47
1.
Voltage levels vary 1:1 with VCC.
2.
Specified with Q/Q̄ open and each QHG/Q̄HG output terminated through a 50Ω resistor to VCC-2V.
3.
Specified with EN and SEL forced to VEE.
150
47
150
51
mV
μA
μA
mA
AC Characteristics (VEE = -3.0V to -5.5V, VCC = GND or VEE = GND, VCC = +3.0V to +5.5V)
Symbol
Characteristic
Min
-40°C
Typ
Max
Min
0°C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Unit
1
Propagation Delay
400
400
400
430
D to Q/Q̄ Output
(SE)
550
550
550
630
D to QHG/Q̄HG Outputs (SE)
2
tSKEW
Duty Cycle Skew
(SE)
5
20
5
20
5
20
5
20
VPP (AC) Minimum Input Swing3
80
1000
80
1000
80
1000
80
1000
Output Rise/Fall Times1
tr / t f
100
260
100
260
100
260
100
260
(20% - 80%)
1.
Specified with each output terminated through a 50Ω resistor to VCC-2V.
2.
Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.
3.
VPP is the minimum peak-to-peak input swing for which AC parameters guaranteed. The device has a voltage gain of ≈20 to Q/Q̄ outputs and a
voltage gain of ≈100 to QHG/Q̄HG outputs.
tPLH / tPHL
AC PP INPUT
D
D
V PP (AC)
April 2007 * REV - 9
www.azmicrotek.com
3
ps
ps
mV
ps
AZ100LVEL16VV
0.00
0.95
-5.00
0.9
-10.00
0.85
-15.00
0.8
-20.00
0.75
-25.00
0.7
Phase
Magnitude
1
S11 MAG
S11 PHASE
-30.00
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
Frequency (MHz)
250.00
0.0175
225.00
0.015
200.00
0.0125
175.00
0.01
150.00
0.0075
125.00
0.005
100.00
0.0025
75.00
Magnitude
0.02
0
50.00
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
Frequency (MHz)
S12, D0/D1 to Q̄, 50 Ω AC load on Q̄
April 2007 * REV - 9
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4
Phase
S11, D0/D1 to Q̄, 50 Ω AC load on Q̄
S12 MAG
S12 PHASE
200.00
25
150.00
20
100.00
15
50.00
10
Phase
30
S21 MAG
S21 PHASE
Phase
Magnitude
AZ100LVEL16VV
S22 MAG
S22 PHASE
0.00
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
Frequency (MHz)
Magnitude
S21, D0/D1 to Q̄, 50 Ω AC load on Q̄
0.8
30.00
0.7
25.00
0.6
20.00
0.5
15.00
0.4
10.00
0.3
5.00
0.2
0.00
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
Frequency (MHz)
S22, D0/D1 to Q̄, 50 Ω AC load on Q̄
April 2007 * REV - 9
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5
AZ100LVEL16VV
TIMING DIAGRAM
D0
D1
EN
SEL
Q
Q
QHG
QHG
PINOUTS FOR MLP16 PACKAGE
Q
Q
NC
VCC
16
15
14
13
D0 1
12 SEL
2
11 QHG
D0
MLP16
D1
10 QHG
3
D1 4
9
5
6
7
8
VBB
NC
VEE
NC
Bottom Center Pad may be left open or tied to VEE
April 2007 * REV - 9
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6
EN
AZ100LVEL16VV
AZ100LVEL16VV DIE:
EL16VV
B
L
M
A
J
DIE SIZE: 950u X 940u
DIE THICKNESS: 14 mils
C
K
BOND PAD: 85u X 85u
D
E
F
I
H
G
PAD COORDINATES1
NAME
1.
A
B
C
D
E
F
G
H
I
J
K
L
M
0, 0 is center of die.
April 2007 * REV - 9
PAD DESIGNATION
D0
D0
¯¯
D1
D1
¯¯
VBB
VEE
EN
Q̄HG
QHG
SEL
VCC
Q
Q̄
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7
PAD CENTERS
X(Microns)
Y(Microns)
-342.5
312.5
-342.5
144.5
-342.5
-87.0
-342.5
-255.0
-33.5
-312.5
126.5
-312.5
312.5
-248.5
312.5
-98.5
312.5
51.5
312.5
201.5
302.5
342.5
142.5
342.5
-140.5
342.5
AZ100LVEL16VV
PACKAGE DIAGRAM
MLP 16
A
D
D
2
2.
INDEX AREA
(D/2 x E/2)
D2
D2/2
B
E2/2
E2
E
2
3x
E
e
2
e
2x
1
aaa C
2x
aaa C
TOP VIEW
bbb M C A B
5.
16 x b
L
3.
3x e
BOTTOM VIEW
ccc C
A3
A
4.
0.08 C
A1
SIDE
VIEW
C
SEATING
PLANE
MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING
CONFORM TO ASME T14-1994.
2. THE TERMINAL #1 AND PAD
NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012.
3. DIMENSION b APPLIES TO METALLIZED
PAD AND IS MEASURED BETWEEN 0.25
AND 0.30 mm FROM PAD TIP.
4. COPLANARITY APPLIES TO THE
EXPOSED PADS AS WELL AS THE
TERMINALS.
5. INSIDE CORNERS OF METALLIZED PAD
MAY BE SQUARE OR ROUNDED
April 2007 * REV - 9
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8
DIM
A
A1
A3
b
D
D2
E
E2
e
L
aaa
bbb
ccc
MIN
MAX
0.80
1.00
0.05
0.00
0.25 REF
0.18
0.30
3.10
2.90
1.95
0.25
3.10
2.90
1.95
0.25
0.50 BSC
0.50
0.30
0.25
0.10
0.10
AZ100LVEL16VV
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc.
makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona
Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license
rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly
or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
April 2007 * REV - 9
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9
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