FUJITSU SEMICONDUCTOR DATA SHEET DS06-20209-2E Semicustom CMOS Standard cell CS86 Series ■ DESCRIPTION The CS86 series of 0.18 µm standard cells is a line of CMOS ASICs based on higher integration implemented by introducing wiring pitch reduction technology and on I/O pad placement technology to the conventional CS81 series. The CS86 series has three types of cell sets (CS86MN, CS86MZ, and CS86ML), covering a variety of applications, from portable devices requiring low power consumption to image processors requiring large-scale circuitry and high speed.The three types of cell sets can be contained on one chip, allowing those system LSIs to be implemented which require low power consumption as well as high-speed operation for certain types of processing. ■ FEATURES : 0.18 µm silicon-gate CMOS, 4- to 6-layer wiring The same chip can therefore incorporate the standard transistor cell and the ultrahighspeed or low-leakage process cell together. Supply voltage : +1.8 V ± 0.15 V (normal) to +1.1 V ± 0.1 V Junction temperature range : −40 °C to +125 °C Cell set CS86MN : Offers standard transistor characteristics. Designed as a library for products requiring higher throughputs. CS86MZ : Offers transistor characteristics for ultra high-speed operation. Designed as a library for products that require higher processing speeds than those provided by CS86MN. CS86ML : Offers transistor charactersistics with less leak current. Designed as a library for mobile devices and other products requiring lower power consumption. Cell Specifications : Cell set name CS86MZ CS86MN CS86ML • Technology • • • • Delay time*1 Power consumption* 3 Leak power* 2 70 ps 88 ps 136 ps 42.7 nW/MHz 40.1 nW/MHz 38.3 nW/MHz 3.922 nW 0.023 nW 0.0067 nW *1 : 2 input NAND cell (low-power type) , F/O = 2, normal load, Power supply voltage 1.8 V, Temperature = +25 °C *2 : 2 input NAND cell (low-power type) , F/O = 1, 4 Grid, Power supply voltage 1.8 V, Temperature = +25 °C *3 : 2 input NAND cell (low-power type) , F/O = 0, non load, Power supply voltage 1.8 V, Temperature = +25 °C (Continued) CS86 Series (Continued) • Output buffer cells with noise reduction circuits • Input buffer cells and bidirectional buffer cells with on-chip input pull-up/pull-down resistors • Buffer cells for crystal oscillation circuits • Special interfaces : SSTL2, PCI, P-CML, T-LVTTL, USB 2.0, IEEE1394, and others. • IP macros : CPU (ARM9, FR-V, and others) , DSP, PCI, IEEE1394, USB 2.0, IrDA, PLL, DAC, ADC, and others. • Capable of incorporating compiled cells (RAM/ROM/Register file/Delay line) • Configurable internal bus circuits • Advanced hardware/software co-design environment • Short-term development using Physical Synthesis tool • Low power consumption using Low Power Synthesis tool • Short-term development using a timing driven layout tool • Hierarchical design environment for supporting large-scale circuits • Support for Signal-Integrity • Support for Memory (RAM, ROM) SCAN • Support for Memory (RAM) BIST • Support for Boundary SCAN • Support for path delay test • A variety of package options : QFP, TQFP, LQFP, HQFP, PBGA, FBGA, FLGA, EBGA 2 CS86 Series ■ MACRO LIBRARY (Including macros being prepared) 1. Logic cells • Adder • AND-OR Inverter • Clock Buffer • Latch • NAND • AND • NOR • OR-AND • Scan Flip Flop • ENOR • Boundary Scan Register • Bus Driver • AND-OR • Decoder • NON-Scan Flip Flop • Inverter • Buffer • OR-AND Inverter • OR • Delay Buffer • Selector • EOR • Dummy Clock Buffer • Others 2. IP macro CPU FR-V, ARM9, and others. DSP Communications DSP, DSP for Digital AV, and others. Peripheral Macro Interval timer, Interruption controller, DMA controller, RTC, Calender, UART, and others. Interface macro PCI, IEEE1394, USB 2.0, IrDA, and others. Multimedia processing macros JPEG, MPEG 4.0, and others. Mixed signal macros ADC, DAC, OPAMP, and others. Compiled macros RAM (1 port, 2 port) , ROM, Delay Line, Register file, and others. PLL Analog PLL I/O macro Compatible with various interface levels between 1.1 V and 5 V; SSTL2, PCI, P-CML, T-LVTTL, USB, IEEE1394, and others. 3 CS86 Series ■ COMPILED CELLS Compiled cells are macro cells which are automatically generated with the bit/word configuration specified. The CS86 series has the following types of compiled cells. (Note that each macro is different in word/bit range depending on the column type.) 1. Clock synchronous single-port RAM (1 address : 1 RW) • High density type/High density partial write type Column type Memory capacity Word range Bit range Unit 4 16 to 72 K 16 to 1 K 1 to 72 bit 16 64 to 72 K 64 to 4 K 1 to 18 bit Bit range Unit 32 to 2 K 2 to 72 bit Word range Bit range Unit 4K to 16 K 6 to 72 bit Bit range Unit • Super high density type/Super high density partial write type Column type Memory capacity Word range 4 64 to 144 K • Large scale partial write type Column type Memory capacity 16 24 to 1152 K • Super high density large scale partial write type Column type Memory capacity Word range 16 • High speed type Column type 8 2 to 1152 K 512 to 16 K 4 to 72 bit Memory capacity Word range Bit range Unit 256 to 144 K 64 to 2 K 4 to 72 bit 2. Clock synchronous dual-port RAM (2 addresses : 1 RW, 1 R) • High density type/Partial write type Column type Memory capacity Word range Bit range Unit 4 16 to 72 K 16 to 1 K 1 to 72 bit 16 64 to 72 K 64 to 4 K 1 to 18 bit 3. Clock synchronous register file (3 addresses : 1 W, 2 R) Column type Memory capacity Word range Bit range Unit 1 4 to 4608 4 to 64 1 to 72 bit 4. Clock synchronous register file (4 addresses : 2 W, 2 R) 4 Column type Memory capacity Word range Bit range Unit 1 4 to 4608 4 to 64 1 to 72 bit CS86 Series 5. Clock synchronous ROM (1 addresses : 1 R) Column type Memory capacity Word range Bit range Unit 16 256 to 1024 K 128 to 8 K 2 to 128 bit 64 1 to 1024 K 512 to 32 K 2 to 32 bit 6. Clock synchronous delay line memory (2 addresses : 1 W, 1 R) Column type Memory capacity Word range Bit range Unit 8 256 to 32 K 32 to 1 K 8 to 32 bit 16 384 to 32 K 64 to 2 K 6 to 16 bit 32 512 to 32 K 128 to 4 K 4 to 8 bit 5 CS86 Series ■ ABSOLUTE MAXIMUM RATINGS (VSS = 0 V) Parameter Rating Symbol Min Unit Max 2.5 *1 VDD − 0.5 Input voltage VI − 0.5 Output voltage VO − 0.5 Storage temperature Tst −55 +125 °C Junction temperature Tj −40 +125 °C Output current*3 IO Input signal transmitting rate RI Clock input*4 : 200 Normal input : 100 Mbps*5 Output signal transmitting rate RO 100 Mbps*5 Output load capacitance CO 3000/RO pF Supply pin current ID Supply voltage V 4.0 *2 VDD+0.5 ( ≤ 2.5 V) *1 VDD+0.5 ( ≤ 4.0 V) *2 VDD+0.5 ( ≤ 2.5 V) *1 VDD+0.5 ( ≤ 4.0 V) *2 ±10 (3.3 VCMOS, 2.5 VCMOS) V V mA ± 7.5 (1.8 VCMOS) See “• Supply pin current for one VDD/GND pin (mA) “ mA *1 : Internal gate part in case of single power supply or dual power supply *2 : I/O part in case 3.3 V I/F or 2.5 V I/F is used by dual power supply. *3 : DC current which continues more than 10 ms, or average DC current *4 : in case of I/O cell for clock input *5 : bps = bit per second • Supply pin current value for one VDD/GND pin (mA) Tj = +125 °C*2 (a) Maximum current for one I/O*1 Frame YH 6 Source type Maximum current (at standard source) (mA) Number of layers VDDE 68 4 VDDE 59 5 VDDE 59 6 VDDI, VDD, VSS 68 4 VDDI, VDD, VSS 93 5 VDDI, VDD, VSS 118 6 CS86 Series Tj = +125°C*2 (b) Current value that one I/O can provide to the core Frame YH Source type Maximum current (at standard source) (mA) Number of layers VDDI, VDD, VSS 34 4 VDDI, VDD, VSS 34 5 VDDI, VDD, VSS 59 6 *1 : Maximum current for one I/O includes the supply current to the I/O part and the core part. *2 : The current values change according to the junction temperature. When the junction temperature is not +125°C, multiply the value by the following coefficients. Tj = +111°C to +125°C : 1.0 Tj = + 91°C to +110°C : 1.4 Tj = + 90°C : 2.8 Note : How to calculate the number of required supply pins In case of a frame with 6-layer wiring (2 power supplies) • Maximum current for one VDD/GND pin VDDE = 59 mA/pin calucurated using the value in “(a) Maximum supply pin current for one I/O” VDDI = VSS = 59 mA/pin calucurated using the value in “(b) Current value that one I/O can provide to the core” • Needed supply pin count (internal power supply/external power supply/VSS) : Ni/Ne/Ns DC internal maximum power-supply current : Iimax, DC external maximum power-supply current : Iemax Ni = Iimax/59mA, Ne = Iemax/59mA, Ns = Iimax/59mA + Iemax/59mA WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 7 CS86 Series ■ RECOMMENDED OPERATING CONDITIONS • Single power supply (VDD = 1.8 V ± 0.15 V) Parameter (VSS = 0 V) Symbol Value Min Typ Max Unit Supply voltage VDD 1.65 1.8 1.95 V “H” level input voltage VIH VDD × 0.65 VDD + 0.3 V “L” level input voltage VIL −0.3 VDD × 0.35 V Junction temperature Tj −40 +125 °C • Dual power supply (VDDE = 3.3 V ± 0.3 V, VDDI = 1.8 V ± 0.15 V/VDDI = 1.5 V ± 0.1 V/VDDI = 1.1 V ± 0.1 V*) (VSS = 0 V) Parameter Symbol VDDE Supply voltage VDDI “H” level input voltage “L” level input voltage 1.8 V CMOS 3.3 V CMOS 1.8 V CMOS 3.3 V CMOS Junction temperature VIH VIL Tj Value Min Typ Max 3.0 3.3 3.6 1.65 1.8 1.95 1.4 1.5 1.6 1.0 1.1 1.2 VDDI × 0.65 VDDI + 0.3 2.0 VDDE + 0.3 −0.3 VDDI × 0.35 −0.3 0.8 −40 +125 Unit V V V °C * : VDDI = 1.1 V±0.1 V is being prepared. • Dual power supply (VDDE = 2.5 V ± 0.2 V, VDDI = 1.8 V ± 0.15 V/VDDI = 1.5 V ± 0.1 V/VDDI = 1.1 V ± 0.1 V*) (VSS = 0 V) Parameter Symbol VDDE Supply voltage “H” level input voltage “L” level input voltage VDDI 1.8 V CMOS 2.5 V CMOS 1.8 V CMOS 2.5 V CMOS Junction temperature * : VDDI = 1.1 V±0.1 V is being prepared. 8 VIH VIL Tj Value Min Typ Max 2.3 2.5 2.7 1.65 1.8 1.95 1.4 1.5 1.6 1.0 1.1 1.2 VDDI × 0.65 VDDI + 0.3 1.7 VDDE + 0.3 −0.3 VDDI × 0.35 −0.3 0.7 −40 +125 Unit V V V °C CS86 Series WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 9 CS86 Series ■ ELECTRICAL CHARACTERISTICS 1. DC characteristics • Single power supply : VDD = 1.8 V standard Parameter Symbol (VDD = 1.8 V ± 0.15 V, VSS = 0 V, Tj = −40 °C to +125 °C) Conditions Value Unit Min Typ Max VDD−0.2 VDD V 0 0.2 V “H” level output voltage VOH IOH = −100 µA “L” level output voltage VOL IOL = 100 µA “H” level output V-I characteristics 1.8 V VDD = 1.8 V±0.15 V * “L” level output V-I characteristics 1.8 V VDD = 1.8 V±0.15 V * Input leakage current IL Pull up/Pull down resistance RP Pull up VIL = 0, Pull down VIH = VDD ±5 µA 8 18 40 kΩ * : Refer to “ (1) 1.8 V” in ■V-I CHARACTERISTICS. • Dual power supply : VDDE = 3.3 V, VDDI = 1.8 V/1.5 V/1.1 V (VDDE = 3.3 V±0.3 V/VDDI = 1.8 V ± 0.15 V, VDDI = 1.5 V ± 0.1 V, VDDI = 1.1 V ± 0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter “H” level output voltage “L” level output voltage Symbol Min Typ Max 3.3 V Output IOH = −100 µA VDDE−0.2 VDDE VOH2 1.8 V Output IOH = −100 µA VDDI−0.2 VDDI VOL4 3.3 V Output IOL = 100 µA 0 0.2 VOL2 1.8 V Output IOL = 100 µA 0 0.2 “L” level output V-I characteristics Input leakage current IL RP 3.3 V VDDE = 3.3 V±0.3 V *1 1.8 V VDDI = 1.8 V±0.15 V *2 3.3 V VDDE = 3.3 V±0.3 V *1 1.8 V VDDI = 1.8 V±0.15 V *2 V V ±5 3.3 V Pull up VIL = 0, Pull down VIH = VDDI 10 33 80 1.8 V Pull up VIL = 0, Pull down VIH = VDDI 8 *2 : Refer to “ (1) 1.8 V” in ■V-I CHARACTERISTICS. Unit *1 : Refer to “ (2) 3.3 V” in ■V-I CHARACTERISTICS. 10 Value VOH4 “H” level output V-I characteristics Pull up/Pull down resistance Conditions µA kΩ 18 40 CS86 Series • Dual power supply : VDDE = 2.5 V, VDDI = 1.8 V/1.5 V/1.1 V (VDDE = 2.5 V±0.2 V, VDDI = 1.8 V ± 0.15 V/VDDI = 1.5 V ± 0.1 V/VDDI = 1.1 V ± 0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C) Parameter Symbol “H” level output voltage Value Conditions Min Typ Max VOH3 2.5 V Output IOH = −100 µA VDDE−0.2 VDDE VOH2 1.8 V Output IOH = −100 µA VDDI−0.2 VDDI VOL3 2.5 V Output IOL = 100 µA 0 0.2 VOL2 1.8 V Output IOL = 100 µA 0 0.2 “L” level output voltage “H” level output V-I characteristics “L” level output V-I characteristics Input leakage current IL Pull up/Pull down resistance RP 2.5 V VDDE = 2.5 V±0.2 V 1.8 V VDDI = 1.8 V±0.15 V * 2.5 V VDDE = 2.5 V±0.2 V 1.8 V VDDI = 1.8 V±0.15 V * Unit V V ±5 2.5 V Pull up VIL = 0, Pull down VIH = VDDE 25 1.8 V Pull up VIL = 0, Pull down VIH = VDDI 8 µA kΩ 18 40 * : Refer to “ (1) 1.8 V” in ■V-I CHARACTERISTICS. 2. AC CHARACTERISTICS Parameter Delay time Symbol pd 1 t * Min VSS = 0 V, Tj = − 40 °C to +125 °C. (Standard specification) Value Unit Typ Max typ* × tmin*3 2 typ*2 × ttyp*3 typ*2 × tmax*3 ns *1 : Delay time = propagation delay time, enable time, disable time. *2 : “typ” is calculated based on the cell specifications. *3 : Measurement conditions Measurement condition tmin ttyp tmax VDD = 1.8 V ± 0.15 V, VSS = 0 V, Tj = −40 °C to +125 °C 0.62 1.00 1.88 VDD = 1.5 V ± 0.10 V, VSS = 0 V, Tj = −40 °C to +125 °C 0.76 1.25 2.42 VDD = 1.1 V ± 0.1 V, VSS = 0 V, Tj = −40 °C to +125 °C 1.08 2.14 6.22 Note : AC characteristics are determined based on junction temperature, voltage conditions, and process variation. 11 CS86 Series ■ V - I CHARACTERISTICS (1) 1.8 V Conditions VOH−VDD (V) −1.0 −2.0 Min : Process = Slow, Tj = +125 °C, VDD = 1.65 V Typ : Process = Typical, Tj = +25 °C, VDD = 1.80 V Max : Process = Fast, Tj = −40 °C, VDD = 1.95 V 40 0.0 0 Max 30 −10 Typ Typ IOL (mA) −20 IOH (mA) Min 20 Min 10 −30 Max 0 0.0 −40 1.0 2.0 VOL (V) 1.8 V CMOS “L” level output (L, M type) 1.8 V CMOS “H” level output (L, M type) VOH−VDD (V) −1.0 −2.0 60 0.0 0 50 Max −10 −30 Typ IOL (mA) Typ 40 −20 IOH (mA) Min 30 Min 20 −40 10 Max −50 −60 0 0.0 1.0 VOL (V) 1.8 V CMOS “H” level output (H, V type) 12 1.8 V CMOS “L” level output (H, V type) 2.0 CS86 Series (2) 3.3 V Conditions −4.0 −3.0 VOH−VDDE (V) −1.0 −2.0 Min : Process = Slow, Tj = +125 °C, VDDE = 3.0 V Typ : Process = Typical, Tj = +25 °C, VDDE = 3.3 V Max : Process = Fast, Tj = −40 °C, VDDE = 3.6 V 0.0 0 80 Max 60 −20 Typ IOL (mA) −40 Typ IOH (mA) Min 40 Min 20 −60 Max −80 0 0.0 0.0 0 100 −40 80 −60 Typ Max 3.3 V CMOS “H” level output (H, V type) Typ 60 Min −80 40 −100 20 −120 4.0 Max −20 IOL (mA) Min 3.0 120 IOH (mA) VOH−VDDE (V) −2.0 −1.0 −3.0 2.0 VOL (V) 3.3 V CMOS “L” level output (L, M type) 3.3 V CMOS “H” level output (L, M type) −4.0 1.0 0 0.0 1.0 2.0 VOL (V) 3.0 4.0 3.3 V CMOS “L” level output (H, V type) 13 CS86 Series ■ INPUT/OUTPUT PIN CAPACITANCE (Tj = +25 °C, VDD = VI = 0 V, f = 1 MHz) Parameter Input pin Symbol Requirements Unit CIN Max 16 pF Output pin L, M, H, V type COUT Max 16 pF I/O pin L, M, H, V type CI/O Max 16 pF Note : Capacitance varies according to the package and the location of the pin. ■ DESIGN METHOD The integrated standard-cell design environment, SCCAD2, provided for conventional models now supports the CS86 series. This allows you to design ASICs that operate at up to 500 MHz with up to 40 million gates and to halve the layout design period. The Fujitsu’s tool GLOSCAD also supports the satandard cell design for CS86 series. • Physical Synthesis Physical Synthesis tool support is provided on a consulting business basis. A conventional style of ASIC development has a problem that iterations between logic synthesis and layout processing are caused by wiring congestion and the difference between actual and estimated wiring capacities. Supporting logic synthesis based on physical information reduces such iterations and contributes to convergence of ASIC design within the scheduled development period. • Low Power Synthesis The Low Power Synthesis tool is supported, which enables the use of gated clock buffers of hard macro type incorporating sequential cells, such as latches. The use of gated clock buffers of hard macro type provides low power consumption by the clock line. It also provides reliable operation, reduction in script complexity, and shorter turnaround time (TAT) for processing. • Timing Driven Layout Performing automatic placement and wiring based on chip-level timing constraints. This prevents post-layout timing problems from developing, which are prominent in particular in the field of deep submicron designs. In addition, all of remaining timing errors are automatically corrected by the Fujitsu’s automatic timing correction system. This shortens the development time from the end of creating a net list to the beginning of the prototyping stage. • Hierarchical Design A top-down hierarchical design approach is taken consistently from logic design to physical design to support larger-scale circuit integration based on deep submicron designing. This enables multiple blocks to be designed logically and physically at the same time and timing convergence to be attained in a short period, providing a design environment capable of easily supporting ultra-large-scale integration of circuits. • Support for Signal Integrity Automated power wiring enables layout satisfying the design specifications within a short period. The power width automatic adjustment function designed taking account of internal power consumption and clock frequencies can produce chips satisfying the current density and voltage drop restrictions without human intervention. Also, a verification system is prepared to check the signal noise or delay penalty owing to capacitive coupling between signal conductors and the voltage drop caused by simultaneous local switching. 14 CS86 Series ■ PACKAGES Package Pin count Material QFP 176, 208, 240 Plastic TQFP 100, 120 Plastic LQFP 144, 176, 208, 256 Plastic HQFP 208, 240, 256, 304 Plastic PBGA 256, 352, 420 Plastic FBGA 112, 144, 168, 176, 192, 224, 240, 272, 288, 304, 368 Plastic FLGA 144, 176, 208, 224, 288 Plastic EBGA 660 Plastic Note : Consult Fujitsu for the combination of each package and the time of availability. 15 CS86 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party’s intellectual property right or other right by using such information. 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