Cypress CY62126BVLL-70BAI 64k x 16 static ram Datasheet

CY62126BV
64K x 16 Static RAM
Features
• 2.7V–3.6V operation
• CMOS for optimum speed/power
• Low active power (70 ns, LL version)
— 54 mW (max.) (15 mA)
• Low standby power (70 ns, LL version)
— 54 µW (max.) (15 µA)
• Automatic power-down when deselected
• Independent control of Upper and Lower Bytes
• Available in 44-pin TSOP II (forward) and fBGA
Functional Description
The CY62126BV is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power
consumption by 99% when deselected. The device enters
power-down mode when CE is HIGH.
(BLE) is LOW, then data from I/O pins (I/O 1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O 9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the write
enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O1 to I/O 8. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O 9 to I/O16. See the
truth table at the back of this data sheet for a complete description of read and write modes.
The input/output pins (I/O 1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY62126BV is available in standard 44-pin TSOP Type II
(forward pinout) and fBGA packages.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
Logic Block Diagram
Pin Configurations
TSOP II (Forward)
Top View
SENSE AMPS
A12
A11
A10
A9
A7
A6
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
64K x 16
RAM Array
1024 X 1024
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NC
I/O1 – I/O8
I/O9 – I/O16
COLUMN DECODER
A4
A5
A8
A13
A14
A15
BHE
WE
CE
OE
BLE
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
62126BV–1
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
A5
A6
A7
OE
BHE
BLE
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
62126BV–2
•
CA 95134
•
408-943-2600
June 14, 2000
CY62126BV
Pin Configurations (continued)
fBGA
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O9
BHE
A3
A4
CE
I/O1
B
A5
A6
I/O2
I/O3
C
VSS
I/O12 NC
A7
I/O4
VCC
D
VCC
I/O13 NC
NC
I/O5
VSS
E
I/O10 I/O11
I/O15 I/O14
A14
A15
I/O6
I/O7
F
I/O16 NC
A12
A13
WE
I/O8
G
A9
A10
A11
NC
H
NC
A8
62126BV–3
Selection Guide
CY62126BV-55
CY62126BV-70
Units
Maximum Access Time
55
70
ns
Maximum Operating Current
20
15
mA
Maximum CMOS Standby Current
15
15
µA
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current .................................................... >200 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V
Range
DC Voltage Applied to Outputs
in High Z State[1] .....................................–0.5V to VCC +0.5V
Industrial
DC Input Voltage[1]..................................–0.5V to VCC +0.5V
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “Instant On” case temperature.
2
Ambient
Temperature[2]
VCC
–40°C to +85°C
2.7V–3.6V
CY62126BV
Electrical Characteristics Over the Operating Range
62126BV
Parameter
Description
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage [1]
IIX
Input Load Current
IOZ
ICC
Test Conditions
Typ.[3]
Min.
VCC = Min., IOH = –1.0 mA
VCC = Min., IOL = 2.1 mA
Max.
Unit
2.2
V
0.4
V
2.0
VCC +
0.3
V
–0.3
0.4
V
GND ≤ V I ≤ VCC
–1
+1
µA
Output Leakage Current
GND ≤ V I ≤ VCC,
Output Disabled
–1
+1
µA
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
55 ns
20
mA
70 ns
15
mA
ISB1
Automatic CE
Power-Down Current
— TTL Inputs
Max. V CC, CE ≥ VIH
VIN ≥ VIH or
VIN ≤ VIL, f = fMAX
2
mA
ISB2
Automatic CE
Power-Down Current
— CMOS Inputs
Max. V CC,
CE ≥ VCC – 0.3V,
VIN ≥ VCC – 0.3V,
or V IN ≤ 0.3V, f=0
15
µA
0.5
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
9
pF
9
pF
TA = 25°C, f = 1 MHz,
VCC = 3.3V
AC Test Loads and Waveforms
R1 1076Ω
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R1 1076 Ω
3.0V
3.0V
ALL INPUT PULSES
3.0V
90%
OUTPUT
R2
5 pF
1262 Ω
INCLUDING
JIG AND
SCOPE
(b)
OUTPUT
Equivalent to: THÉVENIN
EQUIVALENT
581 Ω
R2
1262 Ω
GND
Rise TIme:
1 V/ns
10%
90%
10%
Fall TIme
1 V/ns
1.62V
62126BV-4
Notes:
3. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal
conditions (TA = 25°C, VCC=3.0V). Parameters are guaranteed by design and characterization, and not 100% tested.
4. Tested initially and after any design or process changes that may affect these parameters.
3
CY62126BV
Switching Characteristics[5] Over the Operating Range
Parameter
Description
62126BV–55
62126BV–70
Min.
Min.
Max.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
tLZOE
OE LOW to Low Z
55
55
10
[7]
OE HIGH to High Z
tLZCE
CE LOW to Low Z[7]
70
20
ns
25
10
ns
ns
tHZCE
CE HIGH to High Z
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
55
70
ns
tDBE
Byte Enable to Data Valid
25
35
ns
tLZBE
tHZBE
WRITE CYCLE
Byte Enable to LOW Z
20
ns
ns
5
10
[6, 7]
ns
10
5
[6, 7]
tHZOE
70
0
[7]
Byte Disable to HIGH Z
0
5
[6,7]
25
ns
5
20
ns
ns
25
ns
[8]
tWC
Write Cycle Time
55
70
ns
tSCE
CE LOW to Write End
45
60
ns
tAW
Address Set-Up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
40
50
ns
tSD
Data Set-Up to Write End
25
30
ns
tHD
Data Hold from Write End
0
0
ns
tLZWE
WE HIGH to Low Z[7]
5
5
ns
[6,7]
tHZWE
WE LOW to High Z
tBW
Byte Enable to End of Write
25
45
25
60
ns
ns
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I OL/IOH and 30-pF load capacitance.
6. t HZOE, tHZCE, tHZWE, and tHZBE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, t HZCE is less than tLZCE, tHZOE is less than tLZOE, tHZWE is less than tLZWE, and tHZBE is less than tLZBE, for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. Refer to truth table for
further conditions from BHE and BLE.
4
CY62126BV
Data Retention Characteristics (Over the Operating Range for “L” and “LL” version only)
Parameter
Conditions[9]
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[4]
Chip Deselect to Data Retention Time
tR
Operation Recovery Time
Min.
Typ
Max.
Unit
3.6
V
15
µA
2.0
VCC=VDR=2.0V,
CE ≥VCC – 0.3V,
VIN ≥ VCC – 0.3V or,
VIN ≤ 0.3V
0.5
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
3.0V
VCC
3.0V
VDR > 2V
tR
tCDR
CE
62126BV–5
Switching Waveforms
Read Cycle No.1[10, 11]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
62126BV-6
Read Cycle No. 2 (OE Controlled)[11, 12, 13]
ADDRESS
tRC
CE
tACE
OE
BHE, BLE
tDBE
tHZBE
tLZBE
DATA OUT
tHZOE
tDOE
tLZOE
HIGH IMPEDANCE
tHZCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
ICC
50%
50%
ISB
62126BV-7
Notes:
9. No input may exceed VCC + 0.3V.
10. Device is continuously selected. OE, CE, BHE, BLE = VIL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O is high impedance if OE = VIH or BHE and BLE = VIH.
5
CY62126BV
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[13, 14]
tWC
ADDRESS
tSCE
CE
tSA
tHA
tAW
BHE, BLE
tBW
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
62126BV-8
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13,14]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
OE
tHZOE
DATA I/O
t SD
t HD
DATAIN VALID
NOTE 15
62126BV-9
Notes:
14. If CE, BHE, or BLE go HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
15. During this period the I/Os are in the output state and input signals should not be applied.
6
CY62126BV
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW)[13, 14]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
tBW
BHE, BLE
t
tHZWE
DATAI/O
tSD
NOTE 15
HD
DATA VALID
tLZWE
62126BV-10
Truth Table
CE
OE
WE
BLE
BHE
I/O 1–I/O8
I/O9–I/O16
Mode
Power
H
X
X
X
X
High Z
High Z
Power Down
L
L
H
L
L
Data Out
Data Out
Read All bits
Standby (ISB)
Active (ICC)
L
L
H
L
H
Data Out
High Z
Read Lower bits only
Active (ICC)
L
L
H
H
L
High Z
Data Out
Read Upper bits only
Active (ICC)
L
X
L
L
L
Data In
Data In
Write All bits
Active (ICC)
L
X
L
L
H
Data In
High Z
Write Lower bits only
Active (ICC)
L
X
L
H
L
High Z
Data In
Write Upper bits only
Active (ICC)
L
H
H
X
X
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
7
CY62126BV
Ordering Information
Speed
(ns)
55
Ordering Code
CY62126BVLL-55ZI
CY62126BVLL-55BAI
70
CY62126BVLL-70ZI
CY62126BVLL-70BAI
Package
Name
Z44
BA48
Z44
BA48
Package Type
44-Lead TSOP II
Operating
Range
Industrial
48-ball Fine Pitch Ball Grid Array
44-Lead TSOP II
48-ball Fine Pitch Ball Grid Array
Document #: 38-00584-**
Package Diagrams
44-Pin TSOP II Z44
51-85087-A
8
CY62126BV
Package Diagrams (continued)
48-Ball (7.00 mm x 7.00 mm) FBGA BA48
51-85096-C
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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