Cypress CY62148V 4m (512k x 8) static ram Datasheet

CY62148V MoBL
4M (512K x 8) Static RAM
Features
•
•
•
•
•
•
•
Wide voltage range: 2.7V–3.6V
Ultra low active power
Low standby power
TTL-compatible inputs and outputs
Automatic power-down when deselected
CMOS for optimum speed/power
Package available in a 32 pin TSOPII and a 32-pin SOIC
package
Functional Description[1]
The CY62148V is a high-performance CMOS static RAM
organized as 512K words by eight bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life (MoBL) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can be put into standby mode when
deselected (CE HIGH).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW and WE LOW).
Logic Block Diagram
I/O0
Data in Drivers
I/O1
512K x 8
ARRAY
I/O2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O3
I/O4
I/O5
COLUMN
DECODER
CE
I/O6
POWER
DOWN
I/O7
A10
A 11
A 12
A13
A14
A15
A16
A17
A18
WE
OE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05070 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 27, 2002
CY62148V MoBL
TSOPII/SOIC
Top View
Pin Configurations
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
4
32
31
30
29
5
6
28
27
7
8
9
10
11
12
26
25
1
2
3
13
14
15
16
24
23
22
21
20
19
18
17
VCC
A15
A18
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O 5
I/O4
I/O3
DC Input Voltage[2] ................................ –0.5V to VCC + 0.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied............................................... 55°C to +125°C
Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
Range
Ambient Temperature
VCC
DC Voltage Applied to Outputs
in High-Z State[2] ....................................–0.5V to VCC + 0.5V
Industrial
–40°C to +85°C
2.7V to 3.6V
Product Portfolio
Power Dissipation
VCC Range (V)
Product
CY62148VLL
Min.
Typ.[3]
Max.
Speed
(ns)
2.7
3.0
3.6
70
Operating ICC, (mA)
Standby ISB2, (µA)
Typ.[3]
Maximum
Typ.[3]
Maximum
7
15
2
20
Electrical Characteristics Over the Operating Range
CY62148V-70
Parameter
Description
Test Conditions
Min.
Typ.[3]
Max.
Output HIGH Voltage
IOH = –1.0 mA
VCC = 2.7V
VOL
Output LOW Voltage
IOL = 2.1 mA
VCC = 2.7V
0.4
V
VIH
Input HIGH Voltage
VCC = 3.6V
2.2
VCC +
0.5V
V
VIL
Input LOW Voltage
VCC = 2.7V
–0.5
0.8
V
IIX
Input Load Current
IOZ
Output Leakage Current GND < VO < VCC, Output Disabled
ICC
VCC Operating Supply
Current
IOUT = 0 mA, f = 1 MHz CMOS Levels
ISB1
Automatic CE
Power-down Current—
CMOS Inputs
CE > VCC − 0.3V, VIN > VCC − 0.3V or VIN < 0.3V, f =
fMAX
ISB2
Automatic CE
Power-down Current—
CMOS Inputs
CE > VCC − 0.3V
VIN > VCC − 0.3V
or VIN < 0.3V, f = 0
GND < VI < VCC
IOUT = 0 mA, f = fMAX = 1/tRC
CMOS Levels
VCC = 3.6V
2.4
Unit
VOH
V
–1
+1
+1
µA
–1
+1
+1
µA
7
15
mA
1
2
mA
2
20
µA
VCC = 3.6V
Notes:
2. VIL(min.) = –2.0V for pulse durations less than 20 ns.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05070 Rev. *A
Page 2 of 9
CY62148V MoBL
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
6
pF
8
pF
TA = 25°C, f = 1 MHz,
VCC = 3.0V
Thermal Resistance
Parameter
Description
ΘJA
Thermal Resistance[4]
(Junction to Ambient)
ΘJC
Thermal Resistance[4]
(Junction to Case)
Test Conditions
Others
BGA
Units
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer
printed circuit board
TBD
TBD
°C/W
TBD
TBD
°C/W
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
VCC TYP
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
10%
R2
90%
10%
90%
GND
Fall time: 1V/ns
Rise time: 1V/ns
Equivalent to:
THÉVENIN EQUIVALENT
Rth
OUTPUT
Vth
Parameters
3.0V
Unit
R1
1105
Ohms
R2
1550
Ohms
RTH
645
Ohms
VTH
1.75V
Volts
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[4]
Chip Deselect to Data
Retention Time
tR[5]
Operation Recovery Time
Conditions
Min.
Typ.[3]
1.0
VCC = 1.0V, CE > VCC − 0.3V, VIN > VCC − 0.3V or VIN <
0.3V; No input may exceed VCC + 0.3V
0.2
Max.
Unit
3.6
V
5.5
µA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
1.0V
VDR > 1.0 V
tCDR
1.0V
tR
CE
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
5. Full-device AC operation requires linear VCC ramp from VDR to VCC(min.) > 10 µs or stable at VCC(min.) > 10 µs.
Document #: 38-05070 Rev. *A
Page 3 of 9
CY62148V MoBL
Switching Characteristics Over the Operating Range
[6]
CY62148V-70
Parameter
Description
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
70
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low-Z[7]
10
OE HIGH to
tLZCE
CE LOW to Low-Z[7]
tHZCE
CE HIGH to High-Z
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
ns
ns
35
ns
ns
25
10
[7, 8]
ns
70
5
High-Z[8]
tHZOE
ns
70
ns
ns
25
0
ns
ns
70
ns
Write Cycle[9, 10]
tWC
Write Cycle Time
70
ns
tSCE
CE LOW to Write End
60
ns
tAW
Address Set-up to Write End
60
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
WE Pulse Width
50
ns
tSD
Data Set-up to Write End
30
ns
tHD
Data Hold from Write End
0
ns
[7, 8]
tHZWE
WE LOW to High-Z
tLZWE
WE HIGH to Low-Z[7]
25
10
ns
ns
Switching Waveforms
Read Cycle No. 1 [11, 12]
tRC
ADDRESS
tOHA
DATA OUT
PREVIOUS DATA VALID
tAA
DATA VALID
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30 pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05070 Rev. *A
Page 4 of 9
CY62148V MoBL
Switching Waveforms (continued)
Read Cycle No. 2 [12, 13]
tRC
CE
tACE
OE
tHZOE
tHZCE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPD
tPU
ICC
50%
50%
ISB
[9, 14, 15]
Write Cycle No. 1 (WE Controlled)
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
tPWE
OE
tSD
DATA I/O
NOTE 16
tHD
DATAIN VALID
tHZOE
Write Cycle No. 2 (CE Controlled)
[9, 14, 15]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
WE
tSD
DATA I/O
tHD
DATAIN VALID
Notes:
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
14. Data I/O is high impedance if OE = VIH.
15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
16. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05070 Rev. *A
Page 5 of 9
CY62148V MoBL
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
[10, 15]
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 16
tLZWE
tHZWE
Typical DC and AC Characteristics
1.4
Standby Current vs. Supply Voltage
45
Normalized Operating Current
vs. Supply Voltage
40
1.2
35
ISB (µA)
ICC
1.0
0.8
0.6
25
20
0.4
15
0.2
0.0
1.7
30
2.2
2.7
3.2
SUPPLY VOLTAGE (V)
3.7
10
1.0
3.7
2.8
1.9
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
80
70
60
TAA (ns)
50
40
30
20
10
1.0
2.8
1.9
SUPPLY VOLTAGE (V)
Document #: 38-05070 Rev. *A
3.7
Page 6 of 9
CY62148V MoBL
Truth Table
CE
WE
OE
Inputs/Outputs
Mode
Power
H
X
X
High-Z
Deselect/Power-down
Standby (ISB)
L
H
L
Data Out
Read
Active (ICC)
L
L
X
Data In
Write
Active (ICC)
L
H
H
High-Z
Output Disabled
Active (ICC)
Ordering Information
Speed
(ns)
70
Ordering Code
Package
Name
CY62148VLL-70ZI
ZS32
CY62148VLL-70SI
S34
Package Type
32-lead TSOPII
Operating
Range
Industrial
32-lead 450-mil. molded SOIC
Package Diagrams
32-Lead (450-mil) Molded SOIC S34
51-85081-A
Document #: 38-05070 Rev. *A
Page 7 of 9
CY62148V MoBL
Package Diagrams (continued)
32-lead TSOP II ZS32
51-85095
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company
names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05070 Rev. *A
Page 8 of 9
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62148V MoBL
Document Title: CY62148V MoBL 4M (512K x 8) Static RAM
Document Number: 38-05070
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
107263
09/15/01
SZV
Changed from Spec number: 38-00646 to 38-05070
*A
116515
09/04/02
GBI
Added footnote 1.
Deleted fBGA package.
Removed fBGA package (replacement fBGA package is available in
CY62148CV30)
Document #: 38-05070 Rev. *A
Page 9 of 9
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